2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.829332 # Number of seconds simulated
4 sim_ticks 1829332014500 # Number of ticks simulated
5 final_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 3082632 # Simulator instruction rate (inst/s)
8 host_op_rate 3082630 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 93925630949 # Simulator tick rate (ticks/s)
10 host_mem_usage 334080 # Number of bytes of host memory used
11 host_seconds 19.48 # Real time elapsed on the host
12 sim_insts 60038469 # Number of instructions simulated
13 sim_ops 60038469 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
19 system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory
21 system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory
27 system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory
30 system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory
31 system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
44 system.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
45 system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
46 system.cpu_clk_domain.clock 500 # Clock period in ticks
47 system.cpu.dtb.fetch_hits 0 # ITB hits
48 system.cpu.dtb.fetch_misses 0 # ITB misses
49 system.cpu.dtb.fetch_acv 0 # ITB acv
50 system.cpu.dtb.fetch_accesses 0 # ITB accesses
51 system.cpu.dtb.read_hits 9710423 # DTB read hits
52 system.cpu.dtb.read_misses 10329 # DTB read misses
53 system.cpu.dtb.read_acv 210 # DTB read access violations
54 system.cpu.dtb.read_accesses 728856 # DTB read accesses
55 system.cpu.dtb.write_hits 6352496 # DTB write hits
56 system.cpu.dtb.write_misses 1142 # DTB write misses
57 system.cpu.dtb.write_acv 157 # DTB write access violations
58 system.cpu.dtb.write_accesses 291931 # DTB write accesses
59 system.cpu.dtb.data_hits 16062919 # DTB hits
60 system.cpu.dtb.data_misses 11471 # DTB misses
61 system.cpu.dtb.data_acv 367 # DTB access violations
62 system.cpu.dtb.data_accesses 1020787 # DTB accesses
63 system.cpu.itb.fetch_hits 4974637 # ITB hits
64 system.cpu.itb.fetch_misses 5006 # ITB misses
65 system.cpu.itb.fetch_acv 184 # ITB acv
66 system.cpu.itb.fetch_accesses 4979643 # ITB accesses
67 system.cpu.itb.read_hits 0 # DTB read hits
68 system.cpu.itb.read_misses 0 # DTB read misses
69 system.cpu.itb.read_acv 0 # DTB read access violations
70 system.cpu.itb.read_accesses 0 # DTB read accesses
71 system.cpu.itb.write_hits 0 # DTB write hits
72 system.cpu.itb.write_misses 0 # DTB write misses
73 system.cpu.itb.write_acv 0 # DTB write access violations
74 system.cpu.itb.write_accesses 0 # DTB write accesses
75 system.cpu.itb.data_hits 0 # DTB hits
76 system.cpu.itb.data_misses 0 # DTB misses
77 system.cpu.itb.data_acv 0 # DTB access violations
78 system.cpu.itb.data_accesses 0 # DTB accesses
79 system.cpu.numPwrStateTransitions 12714 # Number of power state transitions
80 system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state
81 system.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state
82 system.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state
83 system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state
84 system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state
85 system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
86 system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state
87 system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states
88 system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states
89 system.cpu.numCycles 3658670387 # number of cpu cycles simulated
90 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
91 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
92 system.cpu.kern.inst.arm 0 # number of arm instructions executed
93 system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
94 system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
95 system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
96 system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
97 system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
98 system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
99 system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
100 system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
101 system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
102 system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
103 system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
104 system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
105 system.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl
106 system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
107 system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
108 system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
109 system.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl
110 system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
111 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
112 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
113 system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
114 system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
115 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
116 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
117 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
118 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
119 system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
120 system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
121 system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
122 system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
123 system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
124 system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
125 system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
126 system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
127 system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
128 system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
129 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
130 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
131 system.cpu.kern.callpal::total 192179 # number of callpals executed
132 system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
133 system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
134 system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
135 system.cpu.kern.mode_good::kernel 1908
136 system.cpu.kern.mode_good::user 1737
137 system.cpu.kern.mode_good::idle 171
138 system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
139 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
140 system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
141 system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
142 system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
143 system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
144 system.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode
145 system.cpu.kern.swap_context 4178 # number of times the context was actually changed
146 system.cpu.committedInsts 60038469 # Number of instructions committed
147 system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
148 system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
149 system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
150 system.cpu.num_func_calls 1484182 # number of times a function call or return occured
151 system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
152 system.cpu.num_int_insts 55913692 # number of integer instructions
153 system.cpu.num_fp_insts 324460 # number of float instructions
154 system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
155 system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
156 system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
157 system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
158 system.cpu.num_mem_refs 16115703 # number of memory refs
159 system.cpu.num_load_insts 9747509 # Number of load instructions
160 system.cpu.num_store_insts 6368194 # Number of store instructions
161 system.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles
162 system.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles
163 system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
164 system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
165 system.cpu.Branches 9064428 # Number of branches fetched
166 system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
167 system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
168 system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
169 system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
170 system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
171 system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
172 system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
173 system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
174 system.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction
175 system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
176 system.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction
177 system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
178 system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
179 system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
180 system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
181 system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
182 system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
183 system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
184 system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
185 system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
186 system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
187 system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
188 system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
189 system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
190 system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
191 system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
192 system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
193 system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
194 system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
195 system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
196 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
197 system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
198 system.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction
199 system.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction
200 system.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction
201 system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction
202 system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
203 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
204 system.cpu.op_class::total 60050307 # Class of executed instruction
205 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
206 system.cpu.dcache.tags.replacements 2042708 # number of replacements
207 system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
208 system.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks.
209 system.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks.
210 system.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks.
211 system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
212 system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
213 system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
214 system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
215 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
216 system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
217 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
218 system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
219 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
220 system.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses
221 system.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses
222 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
223 system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
224 system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
225 system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits
226 system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits
227 system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
228 system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
229 system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
230 system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
231 system.cpu.dcache.demand_hits::cpu.data 13655980 # number of demand (read+write) hits
232 system.cpu.dcache.demand_hits::total 13655980 # number of demand (read+write) hits
233 system.cpu.dcache.overall_hits::cpu.data 13655980 # number of overall hits
234 system.cpu.dcache.overall_hits::total 13655980 # number of overall hits
235 system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
236 system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
237 system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses
238 system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses
239 system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
240 system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
241 system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses
242 system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses
243 system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses
244 system.cpu.dcache.overall_misses::total 2026075 # number of overall misses
245 system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
246 system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
247 system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
248 system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
249 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
250 system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
251 system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
252 system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
253 system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
254 system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
255 system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
256 system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
257 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
258 system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
259 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
260 system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
261 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
262 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
263 system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
264 system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
265 system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
266 system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
267 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
268 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
269 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
270 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
271 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
272 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
273 system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks
274 system.cpu.dcache.writebacks::total 833476 # number of writebacks
275 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
276 system.cpu.icache.tags.replacements 919605 # number of replacements
277 system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
278 system.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks.
279 system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks.
280 system.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks.
281 system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
282 system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
283 system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
284 system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
285 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
286 system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
287 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
288 system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
289 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
290 system.cpu.icache.tags.tag_accesses 60970539 # Number of tag accesses
291 system.cpu.icache.tags.data_accesses 60970539 # Number of data accesses
292 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
293 system.cpu.icache.ReadReq_hits::cpu.inst 59130075 # number of ReadReq hits
294 system.cpu.icache.ReadReq_hits::total 59130075 # number of ReadReq hits
295 system.cpu.icache.demand_hits::cpu.inst 59130075 # number of demand (read+write) hits
296 system.cpu.icache.demand_hits::total 59130075 # number of demand (read+write) hits
297 system.cpu.icache.overall_hits::cpu.inst 59130075 # number of overall hits
298 system.cpu.icache.overall_hits::total 59130075 # number of overall hits
299 system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses
300 system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses
301 system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses
302 system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses
303 system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses
304 system.cpu.icache.overall_misses::total 920232 # number of overall misses
305 system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
306 system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
307 system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
308 system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
309 system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
310 system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
311 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
312 system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
313 system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
314 system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
315 system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
316 system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
317 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
318 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
319 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
320 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
321 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
322 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
323 system.cpu.icache.writebacks::writebacks 919605 # number of writebacks
324 system.cpu.icache.writebacks::total 919605 # number of writebacks
325 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
326 system.cpu.l2cache.tags.replacements 992419 # number of replacements
327 system.cpu.l2cache.tags.tagsinuse 65520.104764 # Cycle average of tags in use
328 system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks.
329 system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks.
330 system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks.
331 system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
332 system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor
333 system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732204 # Average occupied blocks per requestor
334 system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654 # Average occupied blocks per requestor
335 system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy
336 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy
337 system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy
338 system.cpu.l2cache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
339 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
340 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
341 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id
342 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id
343 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id
344 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 # Occupied blocks per task id
345 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
346 system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses
347 system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses
348 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
349 system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits
350 system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits
351 system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits
352 system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits
353 system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits
354 system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits
355 system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits
356 system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits
357 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits
358 system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits
359 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits
360 system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits
361 system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits
362 system.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits
363 system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits
364 system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits
365 system.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits
366 system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits
367 system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses
368 system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
369 system.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses
370 system.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses
371 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
372 system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
373 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
374 system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
375 system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
376 system.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses
377 system.cpu.l2cache.demand_misses::total 1057987 # number of demand (read+write) misses
378 system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
379 system.cpu.l2cache.overall_misses::cpu.data 1044698 # number of overall misses
380 system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses
381 system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses)
382 system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses)
383 system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses)
384 system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses)
385 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
386 system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
387 system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses)
388 system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses)
389 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses)
390 system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses)
391 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses)
392 system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses)
393 system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses
394 system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses
395 system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses
396 system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses
397 system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses
398 system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses
399 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses
400 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses
401 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses
402 system.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses
403 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
404 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
405 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses
406 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses
407 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
408 system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses
409 system.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses
410 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
411 system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses
412 system.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses
413 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
414 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
415 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
416 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
417 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
418 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
419 system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
420 system.cpu.l2cache.writebacks::total 74359 # number of writebacks
421 system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter.
422 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data.
423 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
424 system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
425 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
426 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
427 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
428 system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
429 system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution
430 system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
431 system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
432 system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution
433 system.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution
434 system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution
435 system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
436 system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
437 system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution
438 system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution
439 system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution
440 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution
441 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes)
442 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes)
443 system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes)
444 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes)
445 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes)
446 system.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes)
447 system.cpu.toL2Bus.snoops 993442 # Total snoops (count)
448 system.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes)
449 system.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram
450 system.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram
451 system.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram
452 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
453 system.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram
454 system.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram
455 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
456 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
457 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
458 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
459 system.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram
460 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
461 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
462 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
463 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
464 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
465 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
466 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
467 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
468 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
469 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
470 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
471 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
472 system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
473 system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
474 system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
475 system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
476 system.iobus.trans_dist::WriteResp 51390 # Transaction distribution
477 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
478 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
479 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
480 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
481 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
482 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
483 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
484 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
485 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
486 system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
487 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
488 system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
489 system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
490 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
491 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
492 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
493 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
494 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
495 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes)
496 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
497 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
498 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
499 system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes)
500 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
501 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
502 system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
503 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
504 system.iocache.tags.replacements 41686 # number of replacements
505 system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use
506 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
507 system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
508 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
509 system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit.
510 system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
511 system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
512 system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
513 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
514 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
515 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
516 system.iocache.tags.tag_accesses 375534 # Number of tag accesses
517 system.iocache.tags.data_accesses 375534 # Number of data accesses
518 system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
519 system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
520 system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
521 system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
522 system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
523 system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
524 system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
525 system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
526 system.iocache.overall_misses::total 41726 # number of overall misses
527 system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
528 system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
529 system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
530 system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
531 system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
532 system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
533 system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
534 system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
535 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
536 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
537 system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
538 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
539 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
540 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
541 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
542 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
543 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
544 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
545 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
546 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
547 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
548 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
549 system.iocache.writebacks::writebacks 41512 # number of writebacks
550 system.iocache.writebacks::total 41512 # number of writebacks
551 system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter.
552 system.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data.
553 system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
554 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
555 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
556 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
557 system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
558 system.membus.trans_dist::ReadReq 7184 # Transaction distribution
559 system.membus.trans_dist::ReadResp 948291 # Transaction distribution
560 system.membus.trans_dist::WriteReq 9838 # Transaction distribution
561 system.membus.trans_dist::WriteResp 9838 # Transaction distribution
562 system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution
563 system.membus.trans_dist::CleanEvict 917188 # Transaction distribution
564 system.membus.trans_dist::UpgradeReq 133 # Transaction distribution
565 system.membus.trans_dist::UpgradeResp 133 # Transaction distribution
566 system.membus.trans_dist::ReadExReq 116925 # Transaction distribution
567 system.membus.trans_dist::ReadExResp 116925 # Transaction distribution
568 system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
569 system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
570 system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
571 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
572 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes)
573 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes)
574 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
575 system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
576 system.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes)
577 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
578 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes)
579 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes)
580 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
581 system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
582 system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes)
583 system.membus.snoops 0 # Total snoops (count)
584 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
585 system.membus.snoop_fanout::samples 2149798 # Request fanout histogram
586 system.membus.snoop_fanout::mean 0.000529 # Request fanout histogram
587 system.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram
588 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
589 system.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram
590 system.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram
591 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
592 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
593 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
594 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
595 system.membus.snoop_fanout::total 2149798 # Request fanout histogram
596 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
597 system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
598 system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
599 system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
600 system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
601 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
602 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
603 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
604 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
605 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
606 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
607 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
608 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
609 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
610 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
611 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
612 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
613 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
614 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
615 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
616 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
617 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
618 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
619 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
620 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
621 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
622 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
623 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
624 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
625 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
626 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
627 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
628 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
629 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
630 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
631 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
632 system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
633 system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
634 system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
635 system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
636 system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
637 system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
638 system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
639 system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
640 system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
641 system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
642 system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
643 system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
644 system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
645 system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
646 system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
647 system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
648 system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
649 system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
650 system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
651 system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
652 system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
653 system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
654 system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
656 ---------- End Simulation Statistics ----------
projects / gem5.git / blob