2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.829331 # Number of seconds simulated
4 sim_ticks 1829330593000 # Number of ticks simulated
5 final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 2569577 # Simulator instruction rate (inst/s)
8 host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 78294086451 # Simulator tick rate (ticks/s)
10 host_mem_usage 295292 # Number of bytes of host memory used
11 host_seconds 23.37 # Real time elapsed on the host
12 sim_insts 60037737 # Number of instructions simulated
13 sim_ops 60037737 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory
16 system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
17 system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory
18 system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory
19 system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory
20 system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory
21 system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory
22 system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory
24 system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s)
36 system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s)
41 system.iocache.replacements 41686 # number of replacements
42 system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
43 system.iocache.total_refs 0 # Total number of references to valid blocks.
44 system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
45 system.iocache.avg_refs 0 # Average number of references to valid blocks.
46 system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit.
47 system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor
48 system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy
49 system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy
50 system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
51 system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
52 system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
53 system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
54 system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
55 system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
56 system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
57 system.iocache.overall_misses::total 41726 # number of overall misses
58 system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
59 system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
60 system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
61 system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
62 system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
63 system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
64 system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
65 system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
66 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
67 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
68 system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
69 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
70 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
71 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
72 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
73 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
74 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
75 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
76 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
77 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
78 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
79 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
80 system.iocache.fast_writes 0 # number of fast writes performed
81 system.iocache.cache_copies 0 # number of cache copies performed
82 system.iocache.writebacks::writebacks 41512 # number of writebacks
83 system.iocache.writebacks::total 41512 # number of writebacks
84 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
85 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
86 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
87 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
88 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
89 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
90 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
91 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
92 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
93 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
94 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
95 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
96 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
97 system.cpu.dtb.fetch_hits 0 # ITB hits
98 system.cpu.dtb.fetch_misses 0 # ITB misses
99 system.cpu.dtb.fetch_acv 0 # ITB acv
100 system.cpu.dtb.fetch_accesses 0 # ITB accesses
101 system.cpu.dtb.read_hits 9710417 # DTB read hits
102 system.cpu.dtb.read_misses 10329 # DTB read misses
103 system.cpu.dtb.read_acv 210 # DTB read access violations
104 system.cpu.dtb.read_accesses 728856 # DTB read accesses
105 system.cpu.dtb.write_hits 6352487 # DTB write hits
106 system.cpu.dtb.write_misses 1142 # DTB write misses
107 system.cpu.dtb.write_acv 157 # DTB write access violations
108 system.cpu.dtb.write_accesses 291931 # DTB write accesses
109 system.cpu.dtb.data_hits 16062904 # DTB hits
110 system.cpu.dtb.data_misses 11471 # DTB misses
111 system.cpu.dtb.data_acv 367 # DTB access violations
112 system.cpu.dtb.data_accesses 1020787 # DTB accesses
113 system.cpu.itb.fetch_hits 4974615 # ITB hits
114 system.cpu.itb.fetch_misses 5006 # ITB misses
115 system.cpu.itb.fetch_acv 184 # ITB acv
116 system.cpu.itb.fetch_accesses 4979621 # ITB accesses
117 system.cpu.itb.read_hits 0 # DTB read hits
118 system.cpu.itb.read_misses 0 # DTB read misses
119 system.cpu.itb.read_acv 0 # DTB read access violations
120 system.cpu.itb.read_accesses 0 # DTB read accesses
121 system.cpu.itb.write_hits 0 # DTB write hits
122 system.cpu.itb.write_misses 0 # DTB write misses
123 system.cpu.itb.write_acv 0 # DTB write access violations
124 system.cpu.itb.write_accesses 0 # DTB write accesses
125 system.cpu.itb.data_hits 0 # DTB hits
126 system.cpu.itb.data_misses 0 # DTB misses
127 system.cpu.itb.data_acv 0 # DTB access violations
128 system.cpu.itb.data_accesses 0 # DTB accesses
129 system.cpu.numCycles 3658661078 # number of cpu cycles simulated
130 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
131 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
132 system.cpu.committedInsts 60037737 # Number of instructions committed
133 system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed
134 system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses
135 system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
136 system.cpu.num_func_calls 1484174 # number of times a function call or return occured
137 system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls
138 system.cpu.num_int_insts 55912968 # number of integer instructions
139 system.cpu.num_fp_insts 324460 # number of float instructions
140 system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read
141 system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written
142 system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
143 system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
144 system.cpu.num_mem_refs 16115688 # number of memory refs
145 system.cpu.num_load_insts 9747503 # Number of load instructions
146 system.cpu.num_store_insts 6368185 # Number of store instructions
147 system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles
148 system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles
149 system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
150 system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
151 system.cpu.kern.inst.arm 0 # number of arm instructions executed
152 system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
153 system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed
154 system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
155 system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
156 system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
157 system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl
158 system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl
159 system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
160 system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
161 system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
162 system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
163 system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
164 system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl
165 system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
166 system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
167 system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl
168 system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl
169 system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
170 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
171 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
172 system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl
173 system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl
174 system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
175 system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
176 system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
177 system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
178 system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
179 system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
180 system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
181 system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
182 system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
183 system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
184 system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
185 system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
186 system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
187 system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
188 system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
189 system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
190 system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
191 system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
192 system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
193 system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
194 system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
195 system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
196 system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
197 system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
198 system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
199 system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
200 system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
201 system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
202 system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
203 system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
204 system.cpu.kern.syscall::total 326 # number of syscalls executed
205 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
206 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
207 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
208 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
209 system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
210 system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
211 system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
212 system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed
213 system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
214 system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
215 system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
216 system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
217 system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
218 system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
219 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
220 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
221 system.cpu.kern.callpal::total 192177 # number of callpals executed
222 system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches
223 system.cpu.kern.mode_switch::user 1735 # number of protection mode switches
224 system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
225 system.cpu.kern.mode_good::kernel 1906
226 system.cpu.kern.mode_good::user 1735
227 system.cpu.kern.mode_good::idle 171
228 system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches
229 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
230 system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches
231 system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches
232 system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode
233 system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode
234 system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode
235 system.cpu.kern.swap_context 4178 # number of times the context was actually changed
236 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
237 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
238 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
239 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
240 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
241 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
242 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
243 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
244 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
245 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
246 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
247 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
248 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
249 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
250 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
251 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
252 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
253 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
254 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
255 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
256 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
257 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
258 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
259 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
260 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
261 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
262 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
263 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
264 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
265 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
266 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
267 system.cpu.icache.replacements 919577 # number of replacements
268 system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use
269 system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks.
270 system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks.
271 system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks.
272 system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
273 system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor
274 system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
275 system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
276 system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits
277 system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits
278 system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits
279 system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits
280 system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits
281 system.cpu.icache.overall_hits::total 59129371 # number of overall hits
282 system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses
283 system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses
284 system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses
285 system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses
286 system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses
287 system.cpu.icache.overall_misses::total 920204 # number of overall misses
288 system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses)
289 system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses)
290 system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses
291 system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses
292 system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses
293 system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses
294 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
295 system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
296 system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
297 system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
298 system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
299 system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
300 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
301 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
302 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
303 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
304 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
305 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
306 system.cpu.icache.fast_writes 0 # number of fast writes performed
307 system.cpu.icache.cache_copies 0 # number of cache copies performed
308 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
309 system.cpu.dcache.replacements 2042708 # number of replacements
310 system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
311 system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks.
312 system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks.
313 system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks.
314 system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
315 system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
316 system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
317 system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
318 system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits
319 system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits
320 system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
321 system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
322 system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
323 system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
324 system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
325 system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
326 system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits
327 system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits
328 system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits
329 system.cpu.dcache.overall_hits::total 13655967 # number of overall hits
330 system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses
331 system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses
332 system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
333 system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
334 system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
335 system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
336 system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses
337 system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses
338 system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses
339 system.cpu.dcache.overall_misses::total 2026075 # number of overall misses
340 system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
341 system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
342 system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
343 system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
344 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
345 system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
346 system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
347 system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
348 system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
349 system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
350 system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
351 system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
352 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
353 system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
354 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
355 system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
356 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
357 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
358 system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
359 system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
360 system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
361 system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
362 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
363 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
364 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
365 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
366 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
367 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
368 system.cpu.dcache.fast_writes 0 # number of fast writes performed
369 system.cpu.dcache.cache_copies 0 # number of cache copies performed
370 system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
371 system.cpu.dcache.writebacks::total 833491 # number of writebacks
372 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
373 system.cpu.l2cache.replacements 992297 # number of replacements
374 system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
375 system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks.
376 system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks.
377 system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks.
378 system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
379 system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor
380 system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor
381 system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor
382 system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
383 system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
384 system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
385 system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
386 system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits
387 system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits
388 system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits
389 system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
390 system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
391 system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
392 system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
393 system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits
394 system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits
395 system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits
396 system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits
397 system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits
398 system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits
399 system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits
400 system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits
401 system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses
402 system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
403 system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses
404 system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
405 system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
406 system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses
407 system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses
408 system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses
409 system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses
410 system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses
411 system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses
412 system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses
413 system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses
414 system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses)
415 system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses)
416 system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses)
417 system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
418 system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
419 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
420 system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
421 system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses)
422 system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses)
423 system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses
424 system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses
425 system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses
426 system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses
427 system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses
428 system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses
429 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses
430 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
431 system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses
432 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
433 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
434 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses
435 system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses
436 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses
437 system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses
438 system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
439 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses
440 system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses
441 system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
442 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
443 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
444 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
445 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
446 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
447 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
448 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
449 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
450 system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks
451 system.cpu.l2cache.writebacks::total 74287 # number of writebacks
452 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
454 ---------- End Simulation Statistics ----------
projects / gem5.git / blob