tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxAlphaSystem
  13 children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
  14 boot_cpu_frequency=500
  15 boot_osflags=root=/dev/hda1 console=ttyS0
  16 cache_line_size=64
  17 clk_domain=system.clk_domain
  18 console=/arm/projectscratch/randd/systems/dist/binaries/console
  19 default_p_state=UNDEFINED
  20 eventq_index=0
  21 exit_on_work_items=false
  22 init_param=0
  23 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
  24 kernel_addr_check=true
  25 load_addr_mask=1099511627775
  26 load_offset=0
  27 mem_mode=atomic
  28 mem_ranges=0:134217727
  29 memories=system.physmem
  30 mmap_using_noreserve=false
  31 multi_thread=false
  32 num_work_ids=16
  33 p_state_clk_gate_bins=20
  34 p_state_clk_gate_max=1000000000000
  35 p_state_clk_gate_min=1000
  36 pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
  37 power_model=Null
  38 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  39 symbolfile=
  40 system_rev=1024
  41 system_type=34
  42 thermal_components=
  43 thermal_model=Null
  44 work_begin_ckpt_count=0
  45 work_begin_cpu_id_exit=-1
  46 work_begin_exit_count=0
  47 work_cpus_ckpt_count=0
  48 work_end_ckpt_count=0
  49 work_end_exit_count=0
  50 work_item_id=-1
  51 system_port=system.membus.slave[0]
  52
  53 [system.bridge]
  54 type=Bridge
  55 clk_domain=system.clk_domain
  56 default_p_state=UNDEFINED
  57 delay=50000
  58 eventq_index=0
  59 p_state_clk_gate_bins=20
  60 p_state_clk_gate_max=1000000000000
  61 p_state_clk_gate_min=1000
  62 power_model=Null
  63 ranges=8796093022208:18446744073709551615
  64 req_size=16
  65 resp_size=16
  66 master=system.iobus.slave[0]
  67 slave=system.membus.master[0]
  68
  69 [system.clk_domain]
  70 type=SrcClockDomain
  71 clock=1000
  72 domain_id=-1
  73 eventq_index=0
  74 init_perf_level=0
  75 voltage_domain=system.voltage_domain
  76
  77 [system.cpu0]
  78 type=AtomicSimpleCPU
  79 children=dcache dtb icache interrupts isa itb tracer
  80 branchPred=Null
  81 checker=Null
  82 clk_domain=system.cpu_clk_domain
  83 cpu_id=0
  84 default_p_state=UNDEFINED
  85 do_checkpoint_insts=true
  86 do_quiesce=true
  87 do_statistics_insts=true
  88 dtb=system.cpu0.dtb
  89 eventq_index=0
  90 fastmem=false
  91 function_trace=false
  92 function_trace_start=0
  93 interrupts=system.cpu0.interrupts
  94 isa=system.cpu0.isa
  95 itb=system.cpu0.itb
  96 max_insts_all_threads=0
  97 max_insts_any_thread=0
  98 max_loads_all_threads=0
  99 max_loads_any_thread=0
 100 numThreads=1
 101 p_state_clk_gate_bins=20
 102 p_state_clk_gate_max=1000000000000
 103 p_state_clk_gate_min=1000
 104 power_model=Null
 105 profile=0
 106 progress_interval=0
 107 simpoint_start_insts=
 108 simulate_data_stalls=false
 109 simulate_inst_stalls=false
 110 socket_id=0
 111 switched_out=false
 112 system=system
 113 tracer=system.cpu0.tracer
 114 width=1
 115 workload=
 116 dcache_port=system.cpu0.dcache.cpu_side
 117 icache_port=system.cpu0.icache.cpu_side
 118
 119 [system.cpu0.dcache]
 120 type=Cache
 121 children=tags
 122 addr_ranges=0:18446744073709551615
 123 assoc=4
 124 clk_domain=system.cpu_clk_domain
 125 clusivity=mostly_incl
 126 default_p_state=UNDEFINED
 127 demand_mshr_reserve=1
 128 eventq_index=0
 129 hit_latency=2
 130 is_read_only=false
 131 max_miss_count=0
 132 mshrs=4
 133 p_state_clk_gate_bins=20
 134 p_state_clk_gate_max=1000000000000
 135 p_state_clk_gate_min=1000
 136 power_model=Null
 137 prefetch_on_access=false
 138 prefetcher=Null
 139 response_latency=2
 140 sequential_access=false
 141 size=32768
 142 system=system
 143 tags=system.cpu0.dcache.tags
 144 tgts_per_mshr=20
 145 write_buffers=8
 146 writeback_clean=false
 147 cpu_side=system.cpu0.dcache_port
 148 mem_side=system.toL2Bus.slave[1]
 149
 150 [system.cpu0.dcache.tags]
 151 type=LRU
 152 assoc=4
 153 block_size=64
 154 clk_domain=system.cpu_clk_domain
 155 default_p_state=UNDEFINED
 156 eventq_index=0
 157 hit_latency=2
 158 p_state_clk_gate_bins=20
 159 p_state_clk_gate_max=1000000000000
 160 p_state_clk_gate_min=1000
 161 power_model=Null
 162 sequential_access=false
 163 size=32768
 164
 165 [system.cpu0.dtb]
 166 type=AlphaTLB
 167 eventq_index=0
 168 size=64
 169
 170 [system.cpu0.icache]
 171 type=Cache
 172 children=tags
 173 addr_ranges=0:18446744073709551615
 174 assoc=1
 175 clk_domain=system.cpu_clk_domain
 176 clusivity=mostly_incl
 177 default_p_state=UNDEFINED
 178 demand_mshr_reserve=1
 179 eventq_index=0
 180 hit_latency=2
 181 is_read_only=true
 182 max_miss_count=0
 183 mshrs=4
 184 p_state_clk_gate_bins=20
 185 p_state_clk_gate_max=1000000000000
 186 p_state_clk_gate_min=1000
 187 power_model=Null
 188 prefetch_on_access=false
 189 prefetcher=Null
 190 response_latency=2
 191 sequential_access=false
 192 size=32768
 193 system=system
 194 tags=system.cpu0.icache.tags
 195 tgts_per_mshr=20
 196 write_buffers=8
 197 writeback_clean=true
 198 cpu_side=system.cpu0.icache_port
 199 mem_side=system.toL2Bus.slave[0]
 200
 201 [system.cpu0.icache.tags]
 202 type=LRU
 203 assoc=1
 204 block_size=64
 205 clk_domain=system.cpu_clk_domain
 206 default_p_state=UNDEFINED
 207 eventq_index=0
 208 hit_latency=2
 209 p_state_clk_gate_bins=20
 210 p_state_clk_gate_max=1000000000000
 211 p_state_clk_gate_min=1000
 212 power_model=Null
 213 sequential_access=false
 214 size=32768
 215
 216 [system.cpu0.interrupts]
 217 type=AlphaInterrupts
 218 eventq_index=0
 219
 220 [system.cpu0.isa]
 221 type=AlphaISA
 222 eventq_index=0
 223 system=system
 224
 225 [system.cpu0.itb]
 226 type=AlphaTLB
 227 eventq_index=0
 228 size=48
 229
 230 [system.cpu0.tracer]
 231 type=ExeTracer
 232 eventq_index=0
 233
 234 [system.cpu1]
 235 type=AtomicSimpleCPU
 236 children=dcache dtb icache interrupts isa itb tracer
 237 branchPred=Null
 238 checker=Null
 239 clk_domain=system.cpu_clk_domain
 240 cpu_id=1
 241 default_p_state=UNDEFINED
 242 do_checkpoint_insts=true
 243 do_quiesce=true
 244 do_statistics_insts=true
 245 dtb=system.cpu1.dtb
 246 eventq_index=0
 247 fastmem=false
 248 function_trace=false
 249 function_trace_start=0
 250 interrupts=system.cpu1.interrupts
 251 isa=system.cpu1.isa
 252 itb=system.cpu1.itb
 253 max_insts_all_threads=0
 254 max_insts_any_thread=0
 255 max_loads_all_threads=0
 256 max_loads_any_thread=0
 257 numThreads=1
 258 p_state_clk_gate_bins=20
 259 p_state_clk_gate_max=1000000000000
 260 p_state_clk_gate_min=1000
 261 power_model=Null
 262 profile=0
 263 progress_interval=0
 264 simpoint_start_insts=
 265 simulate_data_stalls=false
 266 simulate_inst_stalls=false
 267 socket_id=0
 268 switched_out=false
 269 system=system
 270 tracer=system.cpu1.tracer
 271 width=1
 272 workload=
 273 dcache_port=system.cpu1.dcache.cpu_side
 274 icache_port=system.cpu1.icache.cpu_side
 275
 276 [system.cpu1.dcache]
 277 type=Cache
 278 children=tags
 279 addr_ranges=0:18446744073709551615
 280 assoc=4
 281 clk_domain=system.cpu_clk_domain
 282 clusivity=mostly_incl
 283 default_p_state=UNDEFINED
 284 demand_mshr_reserve=1
 285 eventq_index=0
 286 hit_latency=2
 287 is_read_only=false
 288 max_miss_count=0
 289 mshrs=4
 290 p_state_clk_gate_bins=20
 291 p_state_clk_gate_max=1000000000000
 292 p_state_clk_gate_min=1000
 293 power_model=Null
 294 prefetch_on_access=false
 295 prefetcher=Null
 296 response_latency=2
 297 sequential_access=false
 298 size=32768
 299 system=system
 300 tags=system.cpu1.dcache.tags
 301 tgts_per_mshr=20
 302 write_buffers=8
 303 writeback_clean=false
 304 cpu_side=system.cpu1.dcache_port
 305 mem_side=system.toL2Bus.slave[3]
 306
 307 [system.cpu1.dcache.tags]
 308 type=LRU
 309 assoc=4
 310 block_size=64
 311 clk_domain=system.cpu_clk_domain
 312 default_p_state=UNDEFINED
 313 eventq_index=0
 314 hit_latency=2
 315 p_state_clk_gate_bins=20
 316 p_state_clk_gate_max=1000000000000
 317 p_state_clk_gate_min=1000
 318 power_model=Null
 319 sequential_access=false
 320 size=32768
 321
 322 [system.cpu1.dtb]
 323 type=AlphaTLB
 324 eventq_index=0
 325 size=64
 326
 327 [system.cpu1.icache]
 328 type=Cache
 329 children=tags
 330 addr_ranges=0:18446744073709551615
 331 assoc=1
 332 clk_domain=system.cpu_clk_domain
 333 clusivity=mostly_incl
 334 default_p_state=UNDEFINED
 335 demand_mshr_reserve=1
 336 eventq_index=0
 337 hit_latency=2
 338 is_read_only=true
 339 max_miss_count=0
 340 mshrs=4
 341 p_state_clk_gate_bins=20
 342 p_state_clk_gate_max=1000000000000
 343 p_state_clk_gate_min=1000
 344 power_model=Null
 345 prefetch_on_access=false
 346 prefetcher=Null
 347 response_latency=2
 348 sequential_access=false
 349 size=32768
 350 system=system
 351 tags=system.cpu1.icache.tags
 352 tgts_per_mshr=20
 353 write_buffers=8
 354 writeback_clean=true
 355 cpu_side=system.cpu1.icache_port
 356 mem_side=system.toL2Bus.slave[2]
 357
 358 [system.cpu1.icache.tags]
 359 type=LRU
 360 assoc=1
 361 block_size=64
 362 clk_domain=system.cpu_clk_domain
 363 default_p_state=UNDEFINED
 364 eventq_index=0
 365 hit_latency=2
 366 p_state_clk_gate_bins=20
 367 p_state_clk_gate_max=1000000000000
 368 p_state_clk_gate_min=1000
 369 power_model=Null
 370 sequential_access=false
 371 size=32768
 372
 373 [system.cpu1.interrupts]
 374 type=AlphaInterrupts
 375 eventq_index=0
 376
 377 [system.cpu1.isa]
 378 type=AlphaISA
 379 eventq_index=0
 380 system=system
 381
 382 [system.cpu1.itb]
 383 type=AlphaTLB
 384 eventq_index=0
 385 size=48
 386
 387 [system.cpu1.tracer]
 388 type=ExeTracer
 389 eventq_index=0
 390
 391 [system.cpu_clk_domain]
 392 type=SrcClockDomain
 393 clock=500
 394 domain_id=-1
 395 eventq_index=0
 396 init_perf_level=0
 397 voltage_domain=system.voltage_domain
 398
 399 [system.disk0]
 400 type=IdeDisk
 401 children=image
 402 delay=1000000
 403 driveID=master
 404 eventq_index=0
 405 image=system.disk0.image
 406
 407 [system.disk0.image]
 408 type=CowDiskImage
 409 children=child
 410 child=system.disk0.image.child
 411 eventq_index=0
 412 image_file=
 413 read_only=false
 414 table_size=65536
 415
 416 [system.disk0.image.child]
 417 type=RawDiskImage
 418 eventq_index=0
 419 image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
 420 read_only=true
 421
 422 [system.disk2]
 423 type=IdeDisk
 424 children=image
 425 delay=1000000
 426 driveID=master
 427 eventq_index=0
 428 image=system.disk2.image
 429
 430 [system.disk2.image]
 431 type=CowDiskImage
 432 children=child
 433 child=system.disk2.image.child
 434 eventq_index=0
 435 image_file=
 436 read_only=false
 437 table_size=65536
 438
 439 [system.disk2.image.child]
 440 type=RawDiskImage
 441 eventq_index=0
 442 image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
 443 read_only=true
 444
 445 [system.dvfs_handler]
 446 type=DVFSHandler
 447 domains=
 448 enable=false
 449 eventq_index=0
 450 sys_clk_domain=system.clk_domain
 451 transition_latency=100000000
 452
 453 [system.intrctrl]
 454 type=IntrControl
 455 eventq_index=0
 456 sys=system
 457
 458 [system.iobus]
 459 type=NoncoherentXBar
 460 clk_domain=system.clk_domain
 461 default_p_state=UNDEFINED
 462 eventq_index=0
 463 forward_latency=1
 464 frontend_latency=2
 465 p_state_clk_gate_bins=20
 466 p_state_clk_gate_max=1000000000000
 467 p_state_clk_gate_min=1000
 468 power_model=Null
 469 response_latency=2
 470 use_default_range=false
 471 width=16
 472 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 473 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 474
 475 [system.iocache]
 476 type=Cache
 477 children=tags
 478 addr_ranges=0:134217727
 479 assoc=8
 480 clk_domain=system.clk_domain
 481 clusivity=mostly_incl
 482 default_p_state=UNDEFINED
 483 demand_mshr_reserve=1
 484 eventq_index=0
 485 hit_latency=50
 486 is_read_only=false
 487 max_miss_count=0
 488 mshrs=20
 489 p_state_clk_gate_bins=20
 490 p_state_clk_gate_max=1000000000000
 491 p_state_clk_gate_min=1000
 492 power_model=Null
 493 prefetch_on_access=false
 494 prefetcher=Null
 495 response_latency=50
 496 sequential_access=false
 497 size=1024
 498 system=system
 499 tags=system.iocache.tags
 500 tgts_per_mshr=12
 501 write_buffers=8
 502 writeback_clean=false
 503 cpu_side=system.iobus.master[27]
 504 mem_side=system.membus.slave[2]
 505
 506 [system.iocache.tags]
 507 type=LRU
 508 assoc=8
 509 block_size=64
 510 clk_domain=system.clk_domain
 511 default_p_state=UNDEFINED
 512 eventq_index=0
 513 hit_latency=50
 514 p_state_clk_gate_bins=20
 515 p_state_clk_gate_max=1000000000000
 516 p_state_clk_gate_min=1000
 517 power_model=Null
 518 sequential_access=false
 519 size=1024
 520
 521 [system.l2c]
 522 type=Cache
 523 children=tags
 524 addr_ranges=0:18446744073709551615
 525 assoc=8
 526 clk_domain=system.cpu_clk_domain
 527 clusivity=mostly_incl
 528 default_p_state=UNDEFINED
 529 demand_mshr_reserve=1
 530 eventq_index=0
 531 hit_latency=20
 532 is_read_only=false
 533 max_miss_count=0
 534 mshrs=20
 535 p_state_clk_gate_bins=20
 536 p_state_clk_gate_max=1000000000000
 537 p_state_clk_gate_min=1000
 538 power_model=Null
 539 prefetch_on_access=false
 540 prefetcher=Null
 541 response_latency=20
 542 sequential_access=false
 543 size=4194304
 544 system=system
 545 tags=system.l2c.tags
 546 tgts_per_mshr=12
 547 write_buffers=8
 548 writeback_clean=false
 549 cpu_side=system.toL2Bus.master[0]
 550 mem_side=system.membus.slave[1]
 551
 552 [system.l2c.tags]
 553 type=LRU
 554 assoc=8
 555 block_size=64
 556 clk_domain=system.cpu_clk_domain
 557 default_p_state=UNDEFINED
 558 eventq_index=0
 559 hit_latency=20
 560 p_state_clk_gate_bins=20
 561 p_state_clk_gate_max=1000000000000
 562 p_state_clk_gate_min=1000
 563 power_model=Null
 564 sequential_access=false
 565 size=4194304
 566
 567 [system.membus]
 568 type=CoherentXBar
 569 children=badaddr_responder snoop_filter
 570 clk_domain=system.clk_domain
 571 default_p_state=UNDEFINED
 572 eventq_index=0
 573 forward_latency=4
 574 frontend_latency=3
 575 p_state_clk_gate_bins=20
 576 p_state_clk_gate_max=1000000000000
 577 p_state_clk_gate_min=1000
 578 point_of_coherency=true
 579 power_model=Null
 580 response_latency=2
 581 snoop_filter=system.membus.snoop_filter
 582 snoop_response_latency=4
 583 system=system
 584 use_default_range=false
 585 width=16
 586 default=system.membus.badaddr_responder.pio
 587 master=system.bridge.slave system.physmem.port
 588 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 589
 590 [system.membus.badaddr_responder]
 591 type=IsaFake
 592 clk_domain=system.clk_domain
 593 default_p_state=UNDEFINED
 594 eventq_index=0
 595 fake_mem=false
 596 p_state_clk_gate_bins=20
 597 p_state_clk_gate_max=1000000000000
 598 p_state_clk_gate_min=1000
 599 pio_addr=0
 600 pio_latency=100000
 601 pio_size=8
 602 power_model=Null
 603 ret_bad_addr=true
 604 ret_data16=65535
 605 ret_data32=4294967295
 606 ret_data64=18446744073709551615
 607 ret_data8=255
 608 system=system
 609 update_data=false
 610 warn_access=
 611 pio=system.membus.default
 612
 613 [system.membus.snoop_filter]
 614 type=SnoopFilter
 615 eventq_index=0
 616 lookup_latency=1
 617 max_capacity=8388608
 618 system=system
 619
 620 [system.physmem]
 621 type=SimpleMemory
 622 bandwidth=73.000000
 623 clk_domain=system.clk_domain
 624 conf_table_reported=true
 625 default_p_state=UNDEFINED
 626 eventq_index=0
 627 in_addr_map=true
 628 latency=30000
 629 latency_var=0
 630 null=false
 631 p_state_clk_gate_bins=20
 632 p_state_clk_gate_max=1000000000000
 633 p_state_clk_gate_min=1000
 634 power_model=Null
 635 range=0:134217727
 636 port=system.membus.master[1]
 637
 638 [system.simple_disk]
 639 type=SimpleDisk
 640 children=disk
 641 disk=system.simple_disk.disk
 642 eventq_index=0
 643 system=system
 644
 645 [system.simple_disk.disk]
 646 type=RawDiskImage
 647 eventq_index=0
 648 image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
 649 read_only=true
 650
 651 [system.terminal]
 652 type=Terminal
 653 eventq_index=0
 654 intr_control=system.intrctrl
 655 number=0
 656 output=true
 657 port=3456
 658
 659 [system.toL2Bus]
 660 type=CoherentXBar
 661 children=snoop_filter
 662 clk_domain=system.cpu_clk_domain
 663 default_p_state=UNDEFINED
 664 eventq_index=0
 665 forward_latency=0
 666 frontend_latency=1
 667 p_state_clk_gate_bins=20
 668 p_state_clk_gate_max=1000000000000
 669 p_state_clk_gate_min=1000
 670 point_of_coherency=false
 671 power_model=Null
 672 response_latency=1
 673 snoop_filter=system.toL2Bus.snoop_filter
 674 snoop_response_latency=1
 675 system=system
 676 use_default_range=false
 677 width=32
 678 master=system.l2c.cpu_side
 679 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 680
 681 [system.toL2Bus.snoop_filter]
 682 type=SnoopFilter
 683 eventq_index=0
 684 lookup_latency=0
 685 max_capacity=8388608
 686 system=system
 687
 688 [system.tsunami]
 689 type=Tsunami
 690 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 691 eventq_index=0
 692 intrctrl=system.intrctrl
 693 system=system
 694
 695 [system.tsunami.backdoor]
 696 type=AlphaBackdoor
 697 clk_domain=system.clk_domain
 698 cpu=system.cpu0
 699 default_p_state=UNDEFINED
 700 disk=system.simple_disk
 701 eventq_index=0
 702 p_state_clk_gate_bins=20
 703 p_state_clk_gate_max=1000000000000
 704 p_state_clk_gate_min=1000
 705 pio_addr=8804682956800
 706 pio_latency=100000
 707 platform=system.tsunami
 708 power_model=Null
 709 system=system
 710 terminal=system.terminal
 711 pio=system.iobus.master[24]
 712
 713 [system.tsunami.cchip]
 714 type=TsunamiCChip
 715 clk_domain=system.clk_domain
 716 default_p_state=UNDEFINED
 717 eventq_index=0
 718 p_state_clk_gate_bins=20
 719 p_state_clk_gate_max=1000000000000
 720 p_state_clk_gate_min=1000
 721 pio_addr=8803072344064
 722 pio_latency=100000
 723 power_model=Null
 724 system=system
 725 tsunami=system.tsunami
 726 pio=system.iobus.master[0]
 727
 728 [system.tsunami.ethernet]
 729 type=NSGigE
 730 BAR0=1
 731 BAR0LegacyIO=false
 732 BAR0Size=256
 733 BAR1=0
 734 BAR1LegacyIO=false
 735 BAR1Size=4096
 736 BAR2=0
 737 BAR2LegacyIO=false
 738 BAR2Size=0
 739 BAR3=0
 740 BAR3LegacyIO=false
 741 BAR3Size=0
 742 BAR4=0
 743 BAR4LegacyIO=false
 744 BAR4Size=0
 745 BAR5=0
 746 BAR5LegacyIO=false
 747 BAR5Size=0
 748 BIST=0
 749 CacheLineSize=0
 750 CapabilityPtr=0
 751 CardbusCIS=0
 752 ClassCode=2
 753 Command=0
 754 DeviceID=34
 755 ExpansionROM=0
 756 HeaderType=0
 757 InterruptLine=30
 758 InterruptPin=1
 759 LatencyTimer=0
 760 LegacyIOBase=0
 761 MSICAPBaseOffset=0
 762 MSICAPCapId=0
 763 MSICAPMaskBits=0
 764 MSICAPMsgAddr=0
 765 MSICAPMsgCtrl=0
 766 MSICAPMsgData=0
 767 MSICAPMsgUpperAddr=0
 768 MSICAPNextCapability=0
 769 MSICAPPendingBits=0
 770 MSIXCAPBaseOffset=0
 771 MSIXCAPCapId=0
 772 MSIXCAPNextCapability=0
 773 MSIXMsgCtrl=0
 774 MSIXPbaOffset=0
 775 MSIXTableOffset=0
 776 MaximumLatency=52
 777 MinimumGrant=176
 778 PMCAPBaseOffset=0
 779 PMCAPCapId=0
 780 PMCAPCapabilities=0
 781 PMCAPCtrlStatus=0
 782 PMCAPNextCapability=0
 783 PXCAPBaseOffset=0
 784 PXCAPCapId=0
 785 PXCAPCapabilities=0
 786 PXCAPDevCap2=0
 787 PXCAPDevCapabilities=0
 788 PXCAPDevCtrl=0
 789 PXCAPDevCtrl2=0
 790 PXCAPDevStatus=0
 791 PXCAPLinkCap=0
 792 PXCAPLinkCtrl=0
 793 PXCAPLinkStatus=0
 794 PXCAPNextCapability=0
 795 ProgIF=0
 796 Revision=0
 797 Status=656
 798 SubClassCode=0
 799 SubsystemID=0
 800 SubsystemVendorID=0
 801 VendorID=4107
 802 clk_domain=system.clk_domain
 803 config_latency=20000
 804 default_p_state=UNDEFINED
 805 dma_data_free=false
 806 dma_desc_free=false
 807 dma_no_allocate=true
 808 dma_read_delay=0
 809 dma_read_factor=0
 810 dma_write_delay=0
 811 dma_write_factor=0
 812 eventq_index=0
 813 hardware_address=00:90:00:00:00:01
 814 host=system.tsunami.pchip
 815 intr_delay=10000000
 816 p_state_clk_gate_bins=20
 817 p_state_clk_gate_max=1000000000000
 818 p_state_clk_gate_min=1000
 819 pci_bus=0
 820 pci_dev=1
 821 pci_func=0
 822 pio_latency=30000
 823 power_model=Null
 824 rss=false
 825 rx_delay=1000000
 826 rx_fifo_size=524288
 827 rx_filter=true
 828 rx_thread=false
 829 system=system
 830 tx_delay=1000000
 831 tx_fifo_size=524288
 832 tx_thread=false
 833 dma=system.iobus.slave[2]
 834 pio=system.iobus.master[26]
 835
 836 [system.tsunami.fake_OROM]
 837 type=IsaFake
 838 clk_domain=system.clk_domain
 839 default_p_state=UNDEFINED
 840 eventq_index=0
 841 fake_mem=false
 842 p_state_clk_gate_bins=20
 843 p_state_clk_gate_max=1000000000000
 844 p_state_clk_gate_min=1000
 845 pio_addr=8796093677568
 846 pio_latency=100000
 847 pio_size=393216
 848 power_model=Null
 849 ret_bad_addr=false
 850 ret_data16=65535
 851 ret_data32=4294967295
 852 ret_data64=18446744073709551615
 853 ret_data8=255
 854 system=system
 855 update_data=false
 856 warn_access=
 857 pio=system.iobus.master[8]
 858
 859 [system.tsunami.fake_ata0]
 860 type=IsaFake
 861 clk_domain=system.clk_domain
 862 default_p_state=UNDEFINED
 863 eventq_index=0
 864 fake_mem=false
 865 p_state_clk_gate_bins=20
 866 p_state_clk_gate_max=1000000000000
 867 p_state_clk_gate_min=1000
 868 pio_addr=8804615848432
 869 pio_latency=100000
 870 pio_size=8
 871 power_model=Null
 872 ret_bad_addr=false
 873 ret_data16=65535
 874 ret_data32=4294967295
 875 ret_data64=18446744073709551615
 876 ret_data8=255
 877 system=system
 878 update_data=false
 879 warn_access=
 880 pio=system.iobus.master[19]
 881
 882 [system.tsunami.fake_ata1]
 883 type=IsaFake
 884 clk_domain=system.clk_domain
 885 default_p_state=UNDEFINED
 886 eventq_index=0
 887 fake_mem=false
 888 p_state_clk_gate_bins=20
 889 p_state_clk_gate_max=1000000000000
 890 p_state_clk_gate_min=1000
 891 pio_addr=8804615848304
 892 pio_latency=100000
 893 pio_size=8
 894 power_model=Null
 895 ret_bad_addr=false
 896 ret_data16=65535
 897 ret_data32=4294967295
 898 ret_data64=18446744073709551615
 899 ret_data8=255
 900 system=system
 901 update_data=false
 902 warn_access=
 903 pio=system.iobus.master[20]
 904
 905 [system.tsunami.fake_pnp_addr]
 906 type=IsaFake
 907 clk_domain=system.clk_domain
 908 default_p_state=UNDEFINED
 909 eventq_index=0
 910 fake_mem=false
 911 p_state_clk_gate_bins=20
 912 p_state_clk_gate_max=1000000000000
 913 p_state_clk_gate_min=1000
 914 pio_addr=8804615848569
 915 pio_latency=100000
 916 pio_size=8
 917 power_model=Null
 918 ret_bad_addr=false
 919 ret_data16=65535
 920 ret_data32=4294967295
 921 ret_data64=18446744073709551615
 922 ret_data8=255
 923 system=system
 924 update_data=false
 925 warn_access=
 926 pio=system.iobus.master[9]
 927
 928 [system.tsunami.fake_pnp_read0]
 929 type=IsaFake
 930 clk_domain=system.clk_domain
 931 default_p_state=UNDEFINED
 932 eventq_index=0
 933 fake_mem=false
 934 p_state_clk_gate_bins=20
 935 p_state_clk_gate_max=1000000000000
 936 p_state_clk_gate_min=1000
 937 pio_addr=8804615848451
 938 pio_latency=100000
 939 pio_size=8
 940 power_model=Null
 941 ret_bad_addr=false
 942 ret_data16=65535
 943 ret_data32=4294967295
 944 ret_data64=18446744073709551615
 945 ret_data8=255
 946 system=system
 947 update_data=false
 948 warn_access=
 949 pio=system.iobus.master[11]
 950
 951 [system.tsunami.fake_pnp_read1]
 952 type=IsaFake
 953 clk_domain=system.clk_domain
 954 default_p_state=UNDEFINED
 955 eventq_index=0
 956 fake_mem=false
 957 p_state_clk_gate_bins=20
 958 p_state_clk_gate_max=1000000000000
 959 p_state_clk_gate_min=1000
 960 pio_addr=8804615848515
 961 pio_latency=100000
 962 pio_size=8
 963 power_model=Null
 964 ret_bad_addr=false
 965 ret_data16=65535
 966 ret_data32=4294967295
 967 ret_data64=18446744073709551615
 968 ret_data8=255
 969 system=system
 970 update_data=false
 971 warn_access=
 972 pio=system.iobus.master[12]
 973
 974 [system.tsunami.fake_pnp_read2]
 975 type=IsaFake
 976 clk_domain=system.clk_domain
 977 default_p_state=UNDEFINED
 978 eventq_index=0
 979 fake_mem=false
 980 p_state_clk_gate_bins=20
 981 p_state_clk_gate_max=1000000000000
 982 p_state_clk_gate_min=1000
 983 pio_addr=8804615848579
 984 pio_latency=100000
 985 pio_size=8
 986 power_model=Null
 987 ret_bad_addr=false
 988 ret_data16=65535
 989 ret_data32=4294967295
 990 ret_data64=18446744073709551615
 991 ret_data8=255
 992 system=system
 993 update_data=false
 994 warn_access=
 995 pio=system.iobus.master[13]
 996
 997 [system.tsunami.fake_pnp_read3]
 998 type=IsaFake
 999 clk_domain=system.clk_domain
1000 default_p_state=UNDEFINED
1001 eventq_index=0
1002 fake_mem=false
1003 p_state_clk_gate_bins=20
1004 p_state_clk_gate_max=1000000000000
1005 p_state_clk_gate_min=1000
1006 pio_addr=8804615848643
1007 pio_latency=100000
1008 pio_size=8
1009 power_model=Null
1010 ret_bad_addr=false
1011 ret_data16=65535
1012 ret_data32=4294967295
1013 ret_data64=18446744073709551615
1014 ret_data8=255
1015 system=system
1016 update_data=false
1017 warn_access=
1018 pio=system.iobus.master[14]
1019
1020 [system.tsunami.fake_pnp_read4]
1021 type=IsaFake
1022 clk_domain=system.clk_domain
1023 default_p_state=UNDEFINED
1024 eventq_index=0
1025 fake_mem=false
1026 p_state_clk_gate_bins=20
1027 p_state_clk_gate_max=1000000000000
1028 p_state_clk_gate_min=1000
1029 pio_addr=8804615848707
1030 pio_latency=100000
1031 pio_size=8
1032 power_model=Null
1033 ret_bad_addr=false
1034 ret_data16=65535
1035 ret_data32=4294967295
1036 ret_data64=18446744073709551615
1037 ret_data8=255
1038 system=system
1039 update_data=false
1040 warn_access=
1041 pio=system.iobus.master[15]
1042
1043 [system.tsunami.fake_pnp_read5]
1044 type=IsaFake
1045 clk_domain=system.clk_domain
1046 default_p_state=UNDEFINED
1047 eventq_index=0
1048 fake_mem=false
1049 p_state_clk_gate_bins=20
1050 p_state_clk_gate_max=1000000000000
1051 p_state_clk_gate_min=1000
1052 pio_addr=8804615848771
1053 pio_latency=100000
1054 pio_size=8
1055 power_model=Null
1056 ret_bad_addr=false
1057 ret_data16=65535
1058 ret_data32=4294967295
1059 ret_data64=18446744073709551615
1060 ret_data8=255
1061 system=system
1062 update_data=false
1063 warn_access=
1064 pio=system.iobus.master[16]
1065
1066 [system.tsunami.fake_pnp_read6]
1067 type=IsaFake
1068 clk_domain=system.clk_domain
1069 default_p_state=UNDEFINED
1070 eventq_index=0
1071 fake_mem=false
1072 p_state_clk_gate_bins=20
1073 p_state_clk_gate_max=1000000000000
1074 p_state_clk_gate_min=1000
1075 pio_addr=8804615848835
1076 pio_latency=100000
1077 pio_size=8
1078 power_model=Null
1079 ret_bad_addr=false
1080 ret_data16=65535
1081 ret_data32=4294967295
1082 ret_data64=18446744073709551615
1083 ret_data8=255
1084 system=system
1085 update_data=false
1086 warn_access=
1087 pio=system.iobus.master[17]
1088
1089 [system.tsunami.fake_pnp_read7]
1090 type=IsaFake
1091 clk_domain=system.clk_domain
1092 default_p_state=UNDEFINED
1093 eventq_index=0
1094 fake_mem=false
1095 p_state_clk_gate_bins=20
1096 p_state_clk_gate_max=1000000000000
1097 p_state_clk_gate_min=1000
1098 pio_addr=8804615848899
1099 pio_latency=100000
1100 pio_size=8
1101 power_model=Null
1102 ret_bad_addr=false
1103 ret_data16=65535
1104 ret_data32=4294967295
1105 ret_data64=18446744073709551615
1106 ret_data8=255
1107 system=system
1108 update_data=false
1109 warn_access=
1110 pio=system.iobus.master[18]
1111
1112 [system.tsunami.fake_pnp_write]
1113 type=IsaFake
1114 clk_domain=system.clk_domain
1115 default_p_state=UNDEFINED
1116 eventq_index=0
1117 fake_mem=false
1118 p_state_clk_gate_bins=20
1119 p_state_clk_gate_max=1000000000000
1120 p_state_clk_gate_min=1000
1121 pio_addr=8804615850617
1122 pio_latency=100000
1123 pio_size=8
1124 power_model=Null
1125 ret_bad_addr=false
1126 ret_data16=65535
1127 ret_data32=4294967295
1128 ret_data64=18446744073709551615
1129 ret_data8=255
1130 system=system
1131 update_data=false
1132 warn_access=
1133 pio=system.iobus.master[10]
1134
1135 [system.tsunami.fake_ppc]
1136 type=IsaFake
1137 clk_domain=system.clk_domain
1138 default_p_state=UNDEFINED
1139 eventq_index=0
1140 fake_mem=false
1141 p_state_clk_gate_bins=20
1142 p_state_clk_gate_max=1000000000000
1143 p_state_clk_gate_min=1000
1144 pio_addr=8804615848891
1145 pio_latency=100000
1146 pio_size=8
1147 power_model=Null
1148 ret_bad_addr=false
1149 ret_data16=65535
1150 ret_data32=4294967295
1151 ret_data64=18446744073709551615
1152 ret_data8=255
1153 system=system
1154 update_data=false
1155 warn_access=
1156 pio=system.iobus.master[7]
1157
1158 [system.tsunami.fake_sm_chip]
1159 type=IsaFake
1160 clk_domain=system.clk_domain
1161 default_p_state=UNDEFINED
1162 eventq_index=0
1163 fake_mem=false
1164 p_state_clk_gate_bins=20
1165 p_state_clk_gate_max=1000000000000
1166 p_state_clk_gate_min=1000
1167 pio_addr=8804615848816
1168 pio_latency=100000
1169 pio_size=8
1170 power_model=Null
1171 ret_bad_addr=false
1172 ret_data16=65535
1173 ret_data32=4294967295
1174 ret_data64=18446744073709551615
1175 ret_data8=255
1176 system=system
1177 update_data=false
1178 warn_access=
1179 pio=system.iobus.master[2]
1180
1181 [system.tsunami.fake_uart1]
1182 type=IsaFake
1183 clk_domain=system.clk_domain
1184 default_p_state=UNDEFINED
1185 eventq_index=0
1186 fake_mem=false
1187 p_state_clk_gate_bins=20
1188 p_state_clk_gate_max=1000000000000
1189 p_state_clk_gate_min=1000
1190 pio_addr=8804615848696
1191 pio_latency=100000
1192 pio_size=8
1193 power_model=Null
1194 ret_bad_addr=false
1195 ret_data16=65535
1196 ret_data32=4294967295
1197 ret_data64=18446744073709551615
1198 ret_data8=255
1199 system=system
1200 update_data=false
1201 warn_access=
1202 pio=system.iobus.master[3]
1203
1204 [system.tsunami.fake_uart2]
1205 type=IsaFake
1206 clk_domain=system.clk_domain
1207 default_p_state=UNDEFINED
1208 eventq_index=0
1209 fake_mem=false
1210 p_state_clk_gate_bins=20
1211 p_state_clk_gate_max=1000000000000
1212 p_state_clk_gate_min=1000
1213 pio_addr=8804615848936
1214 pio_latency=100000
1215 pio_size=8
1216 power_model=Null
1217 ret_bad_addr=false
1218 ret_data16=65535
1219 ret_data32=4294967295
1220 ret_data64=18446744073709551615
1221 ret_data8=255
1222 system=system
1223 update_data=false
1224 warn_access=
1225 pio=system.iobus.master[4]
1226
1227 [system.tsunami.fake_uart3]
1228 type=IsaFake
1229 clk_domain=system.clk_domain
1230 default_p_state=UNDEFINED
1231 eventq_index=0
1232 fake_mem=false
1233 p_state_clk_gate_bins=20
1234 p_state_clk_gate_max=1000000000000
1235 p_state_clk_gate_min=1000
1236 pio_addr=8804615848680
1237 pio_latency=100000
1238 pio_size=8
1239 power_model=Null
1240 ret_bad_addr=false
1241 ret_data16=65535
1242 ret_data32=4294967295
1243 ret_data64=18446744073709551615
1244 ret_data8=255
1245 system=system
1246 update_data=false
1247 warn_access=
1248 pio=system.iobus.master[5]
1249
1250 [system.tsunami.fake_uart4]
1251 type=IsaFake
1252 clk_domain=system.clk_domain
1253 default_p_state=UNDEFINED
1254 eventq_index=0
1255 fake_mem=false
1256 p_state_clk_gate_bins=20
1257 p_state_clk_gate_max=1000000000000
1258 p_state_clk_gate_min=1000
1259 pio_addr=8804615848944
1260 pio_latency=100000
1261 pio_size=8
1262 power_model=Null
1263 ret_bad_addr=false
1264 ret_data16=65535
1265 ret_data32=4294967295
1266 ret_data64=18446744073709551615
1267 ret_data8=255
1268 system=system
1269 update_data=false
1270 warn_access=
1271 pio=system.iobus.master[6]
1272
1273 [system.tsunami.fb]
1274 type=BadDevice
1275 clk_domain=system.clk_domain
1276 default_p_state=UNDEFINED
1277 devicename=FrameBuffer
1278 eventq_index=0
1279 p_state_clk_gate_bins=20
1280 p_state_clk_gate_max=1000000000000
1281 p_state_clk_gate_min=1000
1282 pio_addr=8804615848912
1283 pio_latency=100000
1284 power_model=Null
1285 system=system
1286 pio=system.iobus.master[21]
1287
1288 [system.tsunami.ide]
1289 type=IdeController
1290 BAR0=1
1291 BAR0LegacyIO=false
1292 BAR0Size=8
1293 BAR1=1
1294 BAR1LegacyIO=false
1295 BAR1Size=4
1296 BAR2=1
1297 BAR2LegacyIO=false
1298 BAR2Size=8
1299 BAR3=1
1300 BAR3LegacyIO=false
1301 BAR3Size=4
1302 BAR4=1
1303 BAR4LegacyIO=false
1304 BAR4Size=16
1305 BAR5=1
1306 BAR5LegacyIO=false
1307 BAR5Size=0
1308 BIST=0
1309 CacheLineSize=0
1310 CapabilityPtr=0
1311 CardbusCIS=0
1312 ClassCode=1
1313 Command=0
1314 DeviceID=28945
1315 ExpansionROM=0
1316 HeaderType=0
1317 InterruptLine=31
1318 InterruptPin=1
1319 LatencyTimer=0
1320 LegacyIOBase=0
1321 MSICAPBaseOffset=0
1322 MSICAPCapId=0
1323 MSICAPMaskBits=0
1324 MSICAPMsgAddr=0
1325 MSICAPMsgCtrl=0
1326 MSICAPMsgData=0
1327 MSICAPMsgUpperAddr=0
1328 MSICAPNextCapability=0
1329 MSICAPPendingBits=0
1330 MSIXCAPBaseOffset=0
1331 MSIXCAPCapId=0
1332 MSIXCAPNextCapability=0
1333 MSIXMsgCtrl=0
1334 MSIXPbaOffset=0
1335 MSIXTableOffset=0
1336 MaximumLatency=0
1337 MinimumGrant=0
1338 PMCAPBaseOffset=0
1339 PMCAPCapId=0
1340 PMCAPCapabilities=0
1341 PMCAPCtrlStatus=0
1342 PMCAPNextCapability=0
1343 PXCAPBaseOffset=0
1344 PXCAPCapId=0
1345 PXCAPCapabilities=0
1346 PXCAPDevCap2=0
1347 PXCAPDevCapabilities=0
1348 PXCAPDevCtrl=0
1349 PXCAPDevCtrl2=0
1350 PXCAPDevStatus=0
1351 PXCAPLinkCap=0
1352 PXCAPLinkCtrl=0
1353 PXCAPLinkStatus=0
1354 PXCAPNextCapability=0
1355 ProgIF=133
1356 Revision=0
1357 Status=640
1358 SubClassCode=1
1359 SubsystemID=0
1360 SubsystemVendorID=0
1361 VendorID=32902
1362 clk_domain=system.clk_domain
1363 config_latency=20000
1364 ctrl_offset=0
1365 default_p_state=UNDEFINED
1366 disks=system.disk0 system.disk2
1367 eventq_index=0
1368 host=system.tsunami.pchip
1369 io_shift=0
1370 p_state_clk_gate_bins=20
1371 p_state_clk_gate_max=1000000000000
1372 p_state_clk_gate_min=1000
1373 pci_bus=0
1374 pci_dev=0
1375 pci_func=0
1376 pio_latency=30000
1377 power_model=Null
1378 system=system
1379 dma=system.iobus.slave[1]
1380 pio=system.iobus.master[25]
1381
1382 [system.tsunami.io]
1383 type=TsunamiIO
1384 clk_domain=system.clk_domain
1385 default_p_state=UNDEFINED
1386 eventq_index=0
1387 frequency=976562500
1388 p_state_clk_gate_bins=20
1389 p_state_clk_gate_max=1000000000000
1390 p_state_clk_gate_min=1000
1391 pio_addr=8804615847936
1392 pio_latency=100000
1393 power_model=Null
1394 system=system
1395 time=Thu Jan  1 00:00:00 2009
1396 tsunami=system.tsunami
1397 year_is_bcd=false
1398 pio=system.iobus.master[22]
1399
1400 [system.tsunami.pchip]
1401 type=TsunamiPChip
1402 clk_domain=system.clk_domain
1403 conf_base=8804649402368
1404 conf_device_bits=8
1405 conf_size=16777216
1406 default_p_state=UNDEFINED
1407 eventq_index=0
1408 p_state_clk_gate_bins=20
1409 p_state_clk_gate_max=1000000000000
1410 p_state_clk_gate_min=1000
1411 pci_dma_base=0
1412 pci_mem_base=8796093022208
1413 pci_pio_base=8804615847936
1414 pio_addr=8802535473152
1415 pio_latency=100000
1416 platform=system.tsunami
1417 power_model=Null
1418 system=system
1419 tsunami=system.tsunami
1420 pio=system.iobus.master[1]
1421
1422 [system.tsunami.uart]
1423 type=Uart8250
1424 clk_domain=system.clk_domain
1425 default_p_state=UNDEFINED
1426 eventq_index=0
1427 p_state_clk_gate_bins=20
1428 p_state_clk_gate_max=1000000000000
1429 p_state_clk_gate_min=1000
1430 pio_addr=8804615848952
1431 pio_latency=100000
1432 platform=system.tsunami
1433 power_model=Null
1434 system=system
1435 terminal=system.terminal
1436 pio=system.iobus.master[23]
1437
1438 [system.voltage_domain]
1439 type=VoltageDomain
1440 eventq_index=0
1441 voltage=1.000000
1442