2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.870325 # Number of seconds simulated
4 sim_ticks 1870325497500 # Number of ticks simulated
5 final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 3609656 # Simulator instruction rate (inst/s)
8 host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 106905838632 # Simulator tick rate (ticks/s)
10 host_mem_usage 305660 # Number of bytes of host memory used
11 host_seconds 17.50 # Real time elapsed on the host
12 sim_insts 63151114 # Number of instructions simulated
13 sim_ops 63151114 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory
16 system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory
27 system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory
30 system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory
31 system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory
32 system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory
33 system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 0 # Total number of read requests seen
52 system.physmem.writeReqs 0 # Total number of write requests seen
53 system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
54 system.physmem.bytesRead 0 # Total number of bytes read from memory
55 system.physmem.bytesWritten 0 # Total number of bytes written to memory
56 system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
57 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
58 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
59 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
60 system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
74 system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
75 system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
76 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
90 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
91 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
92 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
93 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
94 system.physmem.totGap 0 # Total gap between requests
95 system.physmem.readPktSize::0 0 # Categorize read packet sizes
96 system.physmem.readPktSize::1 0 # Categorize read packet sizes
97 system.physmem.readPktSize::2 0 # Categorize read packet sizes
98 system.physmem.readPktSize::3 0 # Categorize read packet sizes
99 system.physmem.readPktSize::4 0 # Categorize read packet sizes
100 system.physmem.readPktSize::5 0 # Categorize read packet sizes
101 system.physmem.readPktSize::6 0 # Categorize read packet sizes
102 system.physmem.writePktSize::0 0 # Categorize write packet sizes
103 system.physmem.writePktSize::1 0 # Categorize write packet sizes
104 system.physmem.writePktSize::2 0 # Categorize write packet sizes
105 system.physmem.writePktSize::3 0 # Categorize write packet sizes
106 system.physmem.writePktSize::4 0 # Categorize write packet sizes
107 system.physmem.writePktSize::5 0 # Categorize write packet sizes
108 system.physmem.writePktSize::6 0 # Categorize write packet sizes
109 system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
141 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
173 system.physmem.totQLat 0 # Total cycles spent in queuing delays
174 system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
175 system.physmem.totBusLat 0 # Total cycles spent in databus access
176 system.physmem.totBankLat 0 # Total cycles spent in bank access
177 system.physmem.avgQLat nan # Average queueing delay per request
178 system.physmem.avgBankLat nan # Average bank access latency per request
179 system.physmem.avgBusLat nan # Average bus latency per request
180 system.physmem.avgMemAccLat nan # Average memory access latency
181 system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
182 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
183 system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
184 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
185 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
186 system.physmem.busUtil 0.00 # Data bus utilization in percentage
187 system.physmem.avgRdQLen 0.00 # Average read queue length over time
188 system.physmem.avgWrQLen 0.00 # Average write queue length over time
189 system.physmem.readRowHits 0 # Number of row buffer hits during reads
190 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
191 system.physmem.readRowHitRate nan # Row buffer hit rate for reads
192 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
193 system.physmem.avgGap nan # Average gap between requests
194 system.l2c.replacements 1000406 # number of replacements
195 system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use
196 system.l2c.total_refs 2465980 # Total number of references to valid blocks.
197 system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks.
198 system.l2c.avg_refs 2.314279 # Average number of references to valid blocks.
199 system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
200 system.l2c.occ_blocks::writebacks 56158.126694 # Average occupied blocks per requestor
201 system.l2c.occ_blocks::cpu0.inst 4894.240575 # Average occupied blocks per requestor
202 system.l2c.occ_blocks::cpu0.data 4135.004261 # Average occupied blocks per requestor
203 system.l2c.occ_blocks::cpu1.inst 174.436811 # Average occupied blocks per requestor
204 system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor
205 system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy
206 system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
207 system.l2c.occ_percent::cpu0.data 0.063095 # Average percentage of cache occupancy
208 system.l2c.occ_percent::cpu1.inst 0.002662 # Average percentage of cache occupancy
209 system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
210 system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy
211 system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits
212 system.l2c.ReadReq_hits::cpu0.data 763064 # number of ReadReq hits
213 system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits
214 system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits
215 system.l2c.ReadReq_hits::total 1775588 # number of ReadReq hits
216 system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits
217 system.l2c.Writeback_hits::total 816811 # number of Writeback hits
218 system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits
219 system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
220 system.l2c.UpgradeReq_hits::total 175 # number of UpgradeReq hits
221 system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits
222 system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
223 system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits
224 system.l2c.ReadExReq_hits::cpu0.data 166434 # number of ReadExReq hits
225 system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits
226 system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits
227 system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits
228 system.l2c.demand_hits::cpu0.data 929498 # number of demand (read+write) hits
229 system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits
230 system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits
231 system.l2c.demand_hits::total 1956322 # number of demand (read+write) hits
232 system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits
233 system.l2c.overall_hits::cpu0.data 929498 # number of overall hits
234 system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits
235 system.l2c.overall_hits::cpu1.data 51189 # number of overall hits
236 system.l2c.overall_hits::total 1956322 # number of overall hits
237 system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses
238 system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses
239 system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses
240 system.l2c.ReadReq_misses::cpu1.data 918 # number of ReadReq misses
241 system.l2c.ReadReq_misses::total 941314 # number of ReadReq misses
242 system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses
243 system.l2c.UpgradeReq_misses::cpu1.data 575 # number of UpgradeReq misses
244 system.l2c.UpgradeReq_misses::total 3016 # number of UpgradeReq misses
245 system.l2c.SCUpgradeReq_misses::cpu0.data 67 # number of SCUpgradeReq misses
246 system.l2c.SCUpgradeReq_misses::cpu1.data 103 # number of SCUpgradeReq misses
247 system.l2c.SCUpgradeReq_misses::total 170 # number of SCUpgradeReq misses
248 system.l2c.ReadExReq_misses::cpu0.data 115282 # number of ReadExReq misses
249 system.l2c.ReadExReq_misses::cpu1.data 9862 # number of ReadExReq misses
250 system.l2c.ReadExReq_misses::total 125144 # number of ReadExReq misses
251 system.l2c.demand_misses::cpu0.inst 11889 # number of demand (read+write) misses
252 system.l2c.demand_misses::cpu0.data 1042052 # number of demand (read+write) misses
253 system.l2c.demand_misses::cpu1.inst 1737 # number of demand (read+write) misses
254 system.l2c.demand_misses::cpu1.data 10780 # number of demand (read+write) misses
255 system.l2c.demand_misses::total 1066458 # number of demand (read+write) misses
256 system.l2c.overall_misses::cpu0.inst 11889 # number of overall misses
257 system.l2c.overall_misses::cpu0.data 1042052 # number of overall misses
258 system.l2c.overall_misses::cpu1.inst 1737 # number of overall misses
259 system.l2c.overall_misses::cpu1.data 10780 # number of overall misses
260 system.l2c.overall_misses::total 1066458 # number of overall misses
261 system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses)
262 system.l2c.ReadReq_accesses::cpu0.data 1689834 # number of ReadReq accesses(hits+misses)
263 system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses)
264 system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses)
265 system.l2c.ReadReq_accesses::total 2716902 # number of ReadReq accesses(hits+misses)
266 system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses)
267 system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses)
268 system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses)
269 system.l2c.UpgradeReq_accesses::cpu1.data 612 # number of UpgradeReq accesses(hits+misses)
270 system.l2c.UpgradeReq_accesses::total 3191 # number of UpgradeReq accesses(hits+misses)
271 system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses)
272 system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses)
273 system.l2c.SCUpgradeReq_accesses::total 193 # number of SCUpgradeReq accesses(hits+misses)
274 system.l2c.ReadExReq_accesses::cpu0.data 281716 # number of ReadExReq accesses(hits+misses)
275 system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses)
276 system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses)
277 system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses
278 system.l2c.demand_accesses::cpu0.data 1971550 # number of demand (read+write) accesses
279 system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses
280 system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses
281 system.l2c.demand_accesses::total 3022780 # number of demand (read+write) accesses
282 system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses
283 system.l2c.overall_accesses::cpu0.data 1971550 # number of overall (read+write) accesses
284 system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses
285 system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses
286 system.l2c.overall_accesses::total 3022780 # number of overall (read+write) accesses
287 system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses
288 system.l2c.ReadReq_miss_rate::cpu0.data 0.548438 # miss rate for ReadReq accesses
289 system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses
290 system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses
291 system.l2c.ReadReq_miss_rate::total 0.346466 # miss rate for ReadReq accesses
292 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses
293 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses
294 system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses
295 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses
296 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses
297 system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses
298 system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses
299 system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses
300 system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses
301 system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses
302 system.l2c.demand_miss_rate::cpu0.data 0.528545 # miss rate for demand accesses
303 system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses
304 system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses
305 system.l2c.demand_miss_rate::total 0.352807 # miss rate for demand accesses
306 system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses
307 system.l2c.overall_miss_rate::cpu0.data 0.528545 # miss rate for overall accesses
308 system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses
309 system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses
310 system.l2c.overall_miss_rate::total 0.352807 # miss rate for overall accesses
311 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
312 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
313 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
314 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
315 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
316 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
317 system.l2c.fast_writes 0 # number of fast writes performed
318 system.l2c.cache_copies 0 # number of cache copies performed
319 system.l2c.writebacks::writebacks 81175 # number of writebacks
320 system.l2c.writebacks::total 81175 # number of writebacks
321 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
322 system.iocache.replacements 41694 # number of replacements
323 system.iocache.tagsinuse 0.435353 # Cycle average of tags in use
324 system.iocache.total_refs 0 # Total number of references to valid blocks.
325 system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
326 system.iocache.avg_refs 0 # Average number of references to valid blocks.
327 system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit.
328 system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor
329 system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy
330 system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy
331 system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
332 system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
333 system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
334 system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
335 system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
336 system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
337 system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
338 system.iocache.overall_misses::total 41726 # number of overall misses
339 system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
340 system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
341 system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
342 system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
343 system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
344 system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
345 system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
346 system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
347 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
348 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
349 system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
350 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
351 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
352 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
353 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
354 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
355 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
356 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
357 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
358 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
359 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
360 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
361 system.iocache.fast_writes 0 # number of fast writes performed
362 system.iocache.cache_copies 0 # number of cache copies performed
363 system.iocache.writebacks::writebacks 41520 # number of writebacks
364 system.iocache.writebacks::total 41520 # number of writebacks
365 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
366 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
367 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
368 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
369 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
370 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
371 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
372 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
373 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
374 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
375 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
376 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
377 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
378 system.cpu0.dtb.fetch_hits 0 # ITB hits
379 system.cpu0.dtb.fetch_misses 0 # ITB misses
380 system.cpu0.dtb.fetch_acv 0 # ITB acv
381 system.cpu0.dtb.fetch_accesses 0 # ITB accesses
382 system.cpu0.dtb.read_hits 9148429 # DTB read hits
383 system.cpu0.dtb.read_misses 7079 # DTB read misses
384 system.cpu0.dtb.read_acv 152 # DTB read access violations
385 system.cpu0.dtb.read_accesses 508987 # DTB read accesses
386 system.cpu0.dtb.write_hits 5932048 # DTB write hits
387 system.cpu0.dtb.write_misses 726 # DTB write misses
388 system.cpu0.dtb.write_acv 99 # DTB write access violations
389 system.cpu0.dtb.write_accesses 189050 # DTB write accesses
390 system.cpu0.dtb.data_hits 15080477 # DTB hits
391 system.cpu0.dtb.data_misses 7805 # DTB misses
392 system.cpu0.dtb.data_acv 251 # DTB access violations
393 system.cpu0.dtb.data_accesses 698037 # DTB accesses
394 system.cpu0.itb.fetch_hits 3854196 # ITB hits
395 system.cpu0.itb.fetch_misses 3485 # ITB misses
396 system.cpu0.itb.fetch_acv 127 # ITB acv
397 system.cpu0.itb.fetch_accesses 3857681 # ITB accesses
398 system.cpu0.itb.read_hits 0 # DTB read hits
399 system.cpu0.itb.read_misses 0 # DTB read misses
400 system.cpu0.itb.read_acv 0 # DTB read access violations
401 system.cpu0.itb.read_accesses 0 # DTB read accesses
402 system.cpu0.itb.write_hits 0 # DTB write hits
403 system.cpu0.itb.write_misses 0 # DTB write misses
404 system.cpu0.itb.write_acv 0 # DTB write access violations
405 system.cpu0.itb.write_accesses 0 # DTB write accesses
406 system.cpu0.itb.data_hits 0 # DTB hits
407 system.cpu0.itb.data_misses 0 # DTB misses
408 system.cpu0.itb.data_acv 0 # DTB access violations
409 system.cpu0.itb.data_accesses 0 # DTB accesses
410 system.cpu0.numCycles 3740650883 # number of cpu cycles simulated
411 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
412 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
413 system.cpu0.committedInsts 57184467 # Number of instructions committed
414 system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed
415 system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses
416 system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses
417 system.cpu0.num_func_calls 1398025 # number of times a function call or return occured
418 system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls
419 system.cpu0.num_int_insts 53214865 # number of integer instructions
420 system.cpu0.num_fp_insts 299670 # number of float instructions
421 system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read
422 system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written
423 system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read
424 system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written
425 system.cpu0.num_mem_refs 15124548 # number of memory refs
426 system.cpu0.num_load_insts 9178366 # Number of load instructions
427 system.cpu0.num_store_insts 5946182 # Number of store instructions
428 system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles
429 system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles
430 system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
431 system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
432 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
433 system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed
434 system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed
435 system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl
436 system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
437 system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
438 system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
439 system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl
440 system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl
441 system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl
442 system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
443 system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
444 system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
445 system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl
446 system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl
447 system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl
448 system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
449 system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
450 system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
451 system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl
452 system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl
453 system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl
454 system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
455 system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
456 system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
457 system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl
458 system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl
459 system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
460 system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
461 system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
462 system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed
463 system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed
464 system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed
465 system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed
466 system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed
467 system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed
468 system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed
469 system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed
470 system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed
471 system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed
472 system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed
473 system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed
474 system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed
475 system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed
476 system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed
477 system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed
478 system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed
479 system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed
480 system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed
481 system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed
482 system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed
483 system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed
484 system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed
485 system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed
486 system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed
487 system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
488 system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
489 system.cpu0.kern.syscall::total 226 # number of syscalls executed
490 system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
491 system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed
492 system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
493 system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
494 system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
495 system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed
496 system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
497 system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
498 system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed
499 system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed
500 system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
501 system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
502 system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed
503 system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
504 system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
505 system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
506 system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
507 system.cpu0.kern.callpal::total 183136 # number of callpals executed
508 system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches
509 system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches
510 system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
511 system.cpu0.kern.mode_good::kernel 1155
512 system.cpu0.kern.mode_good::user 1156
513 system.cpu0.kern.mode_good::idle 0
514 system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches
515 system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
516 system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
517 system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches
518 system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode
519 system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode
520 system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
521 system.cpu0.kern.swap_context 3761 # number of times the context was actually changed
522 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
523 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
524 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
525 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
526 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
527 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
528 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
529 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
530 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
531 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
532 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
533 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
534 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
535 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
536 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
537 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
538 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
539 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
540 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
541 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
542 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
543 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
544 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
545 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
546 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
547 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
548 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
549 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
550 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
551 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
552 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
553 system.cpu0.icache.replacements 883989 # number of replacements
554 system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use
555 system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks.
556 system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks.
557 system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks.
558 system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
559 system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor
560 system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
561 system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy
562 system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits
563 system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits
564 system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits
565 system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits
566 system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits
567 system.cpu0.icache.overall_hits::total 56307893 # number of overall hits
568 system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses
569 system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses
570 system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses
571 system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses
572 system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses
573 system.cpu0.icache.overall_misses::total 884630 # number of overall misses
574 system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses)
575 system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses)
576 system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses
577 system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses
578 system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses
579 system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses
580 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses
581 system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses
582 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses
583 system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses
584 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses
585 system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses
586 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
587 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
588 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
589 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
590 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
591 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
592 system.cpu0.icache.fast_writes 0 # number of fast writes performed
593 system.cpu0.icache.cache_copies 0 # number of cache copies performed
594 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
595 system.cpu0.dcache.replacements 1978248 # number of replacements
596 system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use
597 system.cpu0.dcache.total_refs 13113195 # Total number of references to valid blocks.
598 system.cpu0.dcache.sampled_refs 1978760 # Sample count of references to valid blocks.
599 system.cpu0.dcache.avg_refs 6.626976 # Average number of references to valid blocks.
600 system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
601 system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor
602 system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy
603 system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy
604 system.cpu0.dcache.ReadReq_hits::cpu0.data 7292594 # number of ReadReq hits
605 system.cpu0.dcache.ReadReq_hits::total 7292594 # number of ReadReq hits
606 system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits
607 system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits
608 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits
609 system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits
610 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits
611 system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits
612 system.cpu0.dcache.demand_hits::cpu0.data 12750381 # number of demand (read+write) hits
613 system.cpu0.dcache.demand_hits::total 12750381 # number of demand (read+write) hits
614 system.cpu0.dcache.overall_hits::cpu0.data 12750381 # number of overall hits
615 system.cpu0.dcache.overall_hits::total 12750381 # number of overall hits
616 system.cpu0.dcache.ReadReq_misses::cpu0.data 1683136 # number of ReadReq misses
617 system.cpu0.dcache.ReadReq_misses::total 1683136 # number of ReadReq misses
618 system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses
619 system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses
620 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses
621 system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses
622 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses
623 system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses
624 system.cpu0.dcache.demand_misses::cpu0.data 1968934 # number of demand (read+write) misses
625 system.cpu0.dcache.demand_misses::total 1968934 # number of demand (read+write) misses
626 system.cpu0.dcache.overall_misses::cpu0.data 1968934 # number of overall misses
627 system.cpu0.dcache.overall_misses::total 1968934 # number of overall misses
628 system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses)
629 system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses)
630 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses)
631 system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses)
632 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses)
633 system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses)
634 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses)
635 system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses)
636 system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses
637 system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses
638 system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses
639 system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses
640 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187521 # miss rate for ReadReq accesses
641 system.cpu0.dcache.ReadReq_miss_rate::total 0.187521 # miss rate for ReadReq accesses
642 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses
643 system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses
644 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses
645 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses
646 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses
647 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses
648 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses
649 system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses
650 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses
651 system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses
652 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
653 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
654 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
655 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
656 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
657 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
658 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
659 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
660 system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks
661 system.cpu0.dcache.writebacks::total 775494 # number of writebacks
662 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
663 system.cpu1.dtb.fetch_hits 0 # ITB hits
664 system.cpu1.dtb.fetch_misses 0 # ITB misses
665 system.cpu1.dtb.fetch_acv 0 # ITB acv
666 system.cpu1.dtb.fetch_accesses 0 # ITB accesses
667 system.cpu1.dtb.read_hits 1169160 # DTB read hits
668 system.cpu1.dtb.read_misses 3277 # DTB read misses
669 system.cpu1.dtb.read_acv 58 # DTB read access violations
670 system.cpu1.dtb.read_accesses 220342 # DTB read accesses
671 system.cpu1.dtb.write_hits 755883 # DTB write hits
672 system.cpu1.dtb.write_misses 415 # DTB write misses
673 system.cpu1.dtb.write_acv 58 # DTB write access violations
674 system.cpu1.dtb.write_accesses 103280 # DTB write accesses
675 system.cpu1.dtb.data_hits 1925043 # DTB hits
676 system.cpu1.dtb.data_misses 3692 # DTB misses
677 system.cpu1.dtb.data_acv 116 # DTB access violations
678 system.cpu1.dtb.data_accesses 323622 # DTB accesses
679 system.cpu1.itb.fetch_hits 1469677 # ITB hits
680 system.cpu1.itb.fetch_misses 1539 # ITB misses
681 system.cpu1.itb.fetch_acv 57 # ITB acv
682 system.cpu1.itb.fetch_accesses 1471216 # ITB accesses
683 system.cpu1.itb.read_hits 0 # DTB read hits
684 system.cpu1.itb.read_misses 0 # DTB read misses
685 system.cpu1.itb.read_acv 0 # DTB read access violations
686 system.cpu1.itb.read_accesses 0 # DTB read accesses
687 system.cpu1.itb.write_hits 0 # DTB write hits
688 system.cpu1.itb.write_misses 0 # DTB write misses
689 system.cpu1.itb.write_acv 0 # DTB write access violations
690 system.cpu1.itb.write_accesses 0 # DTB write accesses
691 system.cpu1.itb.data_hits 0 # DTB hits
692 system.cpu1.itb.data_misses 0 # DTB misses
693 system.cpu1.itb.data_acv 0 # DTB access violations
694 system.cpu1.itb.data_accesses 0 # DTB accesses
695 system.cpu1.numCycles 3740237218 # number of cpu cycles simulated
696 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
697 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
698 system.cpu1.committedInsts 5966647 # Number of instructions committed
699 system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed
700 system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses
701 system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses
702 system.cpu1.num_func_calls 184190 # number of times a function call or return occured
703 system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls
704 system.cpu1.num_int_insts 5582916 # number of integer instructions
705 system.cpu1.num_fp_insts 28730 # number of float instructions
706 system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read
707 system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written
708 system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read
709 system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written
710 system.cpu1.num_mem_refs 1936419 # number of memory refs
711 system.cpu1.num_load_insts 1176619 # Number of load instructions
712 system.cpu1.num_store_insts 759800 # Number of store instructions
713 system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles
714 system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles
715 system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles
716 system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles
717 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
718 system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed
719 system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed
720 system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl
721 system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl
722 system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl
723 system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl
724 system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl
725 system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl
726 system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl
727 system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl
728 system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl
729 system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl
730 system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl
731 system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
732 system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl
733 system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl
734 system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl
735 system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl
736 system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
737 system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
738 system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl
739 system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl
740 system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
741 system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
742 system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
743 system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
744 system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
745 system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
746 system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
747 system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
748 system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
749 system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
750 system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
751 system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
752 system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
753 system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
754 system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
755 system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
756 system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
757 system.cpu1.kern.syscall::total 100 # number of syscalls executed
758 system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
759 system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
760 system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
761 system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
762 system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed
763 system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
764 system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
765 system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed
766 system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed
767 system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed
768 system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed
769 system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed
770 system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed
771 system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed
772 system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
773 system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
774 system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
775 system.cpu1.kern.callpal::total 32267 # number of callpals executed
776 system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches
777 system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
778 system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches
779 system.cpu1.kern.mode_good::kernel 613
780 system.cpu1.kern.mode_good::user 580
781 system.cpu1.kern.mode_good::idle 33
782 system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches
783 system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
784 system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches
785 system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches
786 system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode
787 system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
788 system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode
789 system.cpu1.kern.swap_context 473 # number of times the context was actually changed
790 system.cpu1.icache.replacements 104103 # number of replacements
791 system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use
792 system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks.
793 system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks.
794 system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks.
795 system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit.
796 system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor
797 system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy
798 system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy
799 system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits
800 system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits
801 system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits
802 system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits
803 system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits
804 system.cpu1.icache.overall_hits::total 5865807 # number of overall hits
805 system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses
806 system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses
807 system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses
808 system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses
809 system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses
810 system.cpu1.icache.overall_misses::total 104648 # number of overall misses
811 system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses)
812 system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses)
813 system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses
814 system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses
815 system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses
816 system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses
817 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses
818 system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses
819 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses
820 system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses
821 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses
822 system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses
823 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
824 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
825 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
826 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
827 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
828 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
829 system.cpu1.icache.fast_writes 0 # number of fast writes performed
830 system.cpu1.icache.cache_copies 0 # number of cache copies performed
831 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
832 system.cpu1.dcache.replacements 62444 # number of replacements
833 system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use
834 system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks.
835 system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks.
836 system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks.
837 system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit.
838 system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor
839 system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy
840 system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy
841 system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits
842 system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits
843 system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits
844 system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits
845 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits
846 system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits
847 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits
848 system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits
849 system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits
850 system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits
851 system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits
852 system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits
853 system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses
854 system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses
855 system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses
856 system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses
857 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses
858 system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses
859 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses
860 system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses
861 system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses
862 system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses
863 system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses
864 system.cpu1.dcache.overall_misses::total 67742 # number of overall misses
865 system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses)
866 system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses)
867 system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses)
868 system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses)
869 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses)
870 system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses)
871 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses)
872 system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses)
873 system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses
874 system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses
875 system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses
876 system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses
877 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses
878 system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses
879 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses
880 system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses
881 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses
882 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses
883 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses
884 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses
885 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses
886 system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses
887 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses
888 system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses
889 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
890 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
891 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
892 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
893 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
894 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
895 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
896 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
897 system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks
898 system.cpu1.dcache.writebacks::total 41317 # number of writebacks
899 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
901 ---------- End Simulation Statistics ----------
projects / gem5.git / blob