2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.926422 # Number of seconds simulated
4 sim_ticks 1926421638000 # Number of ticks simulated
5 final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1739419 # Simulator instruction rate (inst/s)
8 host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 59628989604 # Simulator tick rate (ticks/s)
10 host_mem_usage 334072 # Number of bytes of host memory used
11 host_seconds 32.31 # Real time elapsed on the host
12 sim_insts 56195014 # Number of instructions simulated
13 sim_ops 56195014 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory
19 system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory
21 system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory
27 system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory
30 system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory
31 system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.readReqs 401602 # Number of read requests accepted
45 system.physmem.writeReqs 115765 # Number of write requests accepted
46 system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue
47 system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue
48 system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM
49 system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
50 system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM
51 system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side
52 system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side
53 system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
54 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
55 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56 system.physmem.perBankRdBursts::0 25229 # Per bank write bursts
57 system.physmem.perBankRdBursts::1 25631 # Per bank write bursts
58 system.physmem.perBankRdBursts::2 25563 # Per bank write bursts
59 system.physmem.perBankRdBursts::3 25503 # Per bank write bursts
60 system.physmem.perBankRdBursts::4 24978 # Per bank write bursts
61 system.physmem.perBankRdBursts::5 24964 # Per bank write bursts
62 system.physmem.perBankRdBursts::6 24209 # Per bank write bursts
63 system.physmem.perBankRdBursts::7 24494 # Per bank write bursts
64 system.physmem.perBankRdBursts::8 25180 # Per bank write bursts
65 system.physmem.perBankRdBursts::9 24757 # Per bank write bursts
66 system.physmem.perBankRdBursts::10 25269 # Per bank write bursts
67 system.physmem.perBankRdBursts::11 24873 # Per bank write bursts
68 system.physmem.perBankRdBursts::12 24512 # Per bank write bursts
69 system.physmem.perBankRdBursts::13 25367 # Per bank write bursts
70 system.physmem.perBankRdBursts::14 25615 # Per bank write bursts
71 system.physmem.perBankRdBursts::15 25349 # Per bank write bursts
72 system.physmem.perBankWrBursts::0 7626 # Per bank write bursts
73 system.physmem.perBankWrBursts::1 7640 # Per bank write bursts
74 system.physmem.perBankWrBursts::2 7866 # Per bank write bursts
75 system.physmem.perBankWrBursts::3 7539 # Per bank write bursts
76 system.physmem.perBankWrBursts::4 7128 # Per bank write bursts
77 system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
78 system.physmem.perBankWrBursts::6 6324 # Per bank write bursts
79 system.physmem.perBankWrBursts::7 6321 # Per bank write bursts
80 system.physmem.perBankWrBursts::8 7317 # Per bank write bursts
81 system.physmem.perBankWrBursts::9 6511 # Per bank write bursts
82 system.physmem.perBankWrBursts::10 7117 # Per bank write bursts
83 system.physmem.perBankWrBursts::11 6900 # Per bank write bursts
84 system.physmem.perBankWrBursts::12 7101 # Per bank write bursts
85 system.physmem.perBankWrBursts::13 7827 # Per bank write bursts
86 system.physmem.perBankWrBursts::14 7864 # Per bank write bursts
87 system.physmem.perBankWrBursts::15 7687 # Per bank write bursts
88 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89 system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
90 system.physmem.totGap 1926409764500 # Total gap between requests
91 system.physmem.readPktSize::0 0 # Read request sizes (log2)
92 system.physmem.readPktSize::1 0 # Read request sizes (log2)
93 system.physmem.readPktSize::2 0 # Read request sizes (log2)
94 system.physmem.readPktSize::3 0 # Read request sizes (log2)
95 system.physmem.readPktSize::4 0 # Read request sizes (log2)
96 system.physmem.readPktSize::5 0 # Read request sizes (log2)
97 system.physmem.readPktSize::6 401602 # Read request sizes (log2)
98 system.physmem.writePktSize::0 0 # Write request sizes (log2)
99 system.physmem.writePktSize::1 0 # Write request sizes (log2)
100 system.physmem.writePktSize::2 0 # Write request sizes (log2)
101 system.physmem.writePktSize::3 0 # Write request sizes (log2)
102 system.physmem.writePktSize::4 0 # Write request sizes (log2)
103 system.physmem.writePktSize::5 0 # Write request sizes (log2)
104 system.physmem.writePktSize::6 115765 # Write request sizes (log2)
105 system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
137 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see
201 system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation
215 system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes
223 system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads
255 system.physmem.totQLat 6110922250 # Total ticks spent queuing
256 system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM
257 system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers
258 system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst
259 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
260 system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst
261 system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s
262 system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s
263 system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s
264 system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s
265 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
266 system.physmem.busUtil 0.13 # Data bus utilization in percentage
267 system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
268 system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
269 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
270 system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing
271 system.physmem.readRowHits 360225 # Number of row buffer hits during reads
272 system.physmem.writeRowHits 93542 # Number of row buffer hits during writes
273 system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads
274 system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
275 system.physmem.avgGap 3723487.90 # Average gap between requests
276 system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined
277 system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ)
278 system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ)
279 system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ)
280 system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ)
281 system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ)
282 system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ)
283 system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ)
284 system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ)
285 system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ)
286 system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ)
287 system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ)
288 system.physmem_0.averagePower 250.199922 # Core power per rank (mW)
289 system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank
290 system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states
291 system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states
292 system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states
293 system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states
294 system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states
295 system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states
296 system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ)
297 system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ)
298 system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ)
299 system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ)
300 system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ)
301 system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ)
302 system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ)
303 system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ)
304 system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ)
305 system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ)
306 system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ)
307 system.physmem_1.averagePower 250.543123 # Core power per rank (mW)
308 system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank
309 system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states
310 system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states
311 system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states
312 system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states
313 system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states
314 system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states
315 system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
316 system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
317 system.cpu_clk_domain.clock 500 # Clock period in ticks
318 system.cpu.dtb.fetch_hits 0 # ITB hits
319 system.cpu.dtb.fetch_misses 0 # ITB misses
320 system.cpu.dtb.fetch_acv 0 # ITB acv
321 system.cpu.dtb.fetch_accesses 0 # ITB accesses
322 system.cpu.dtb.read_hits 9066536 # DTB read hits
323 system.cpu.dtb.read_misses 10331 # DTB read misses
324 system.cpu.dtb.read_acv 210 # DTB read access violations
325 system.cpu.dtb.read_accesses 728865 # DTB read accesses
326 system.cpu.dtb.write_hits 6357492 # DTB write hits
327 system.cpu.dtb.write_misses 1143 # DTB write misses
328 system.cpu.dtb.write_acv 157 # DTB write access violations
329 system.cpu.dtb.write_accesses 291932 # DTB write accesses
330 system.cpu.dtb.data_hits 15424028 # DTB hits
331 system.cpu.dtb.data_misses 11474 # DTB misses
332 system.cpu.dtb.data_acv 367 # DTB access violations
333 system.cpu.dtb.data_accesses 1020797 # DTB accesses
334 system.cpu.itb.fetch_hits 4975201 # ITB hits
335 system.cpu.itb.fetch_misses 5010 # ITB misses
336 system.cpu.itb.fetch_acv 184 # ITB acv
337 system.cpu.itb.fetch_accesses 4980211 # ITB accesses
338 system.cpu.itb.read_hits 0 # DTB read hits
339 system.cpu.itb.read_misses 0 # DTB read misses
340 system.cpu.itb.read_acv 0 # DTB read access violations
341 system.cpu.itb.read_accesses 0 # DTB read accesses
342 system.cpu.itb.write_hits 0 # DTB write hits
343 system.cpu.itb.write_misses 0 # DTB write misses
344 system.cpu.itb.write_acv 0 # DTB write access violations
345 system.cpu.itb.write_accesses 0 # DTB write accesses
346 system.cpu.itb.data_hits 0 # DTB hits
347 system.cpu.itb.data_misses 0 # DTB misses
348 system.cpu.itb.data_acv 0 # DTB access violations
349 system.cpu.itb.data_accesses 0 # DTB accesses
350 system.cpu.numPwrStateTransitions 12758 # Number of power state transitions
351 system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state
352 system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state
353 system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state
354 system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
355 system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state
356 system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
357 system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
358 system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state
359 system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states
360 system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states
361 system.cpu.numCycles 3852843276 # number of cpu cycles simulated
362 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
363 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
364 system.cpu.kern.inst.arm 0 # number of arm instructions executed
365 system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
366 system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed
367 system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl
368 system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
369 system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl
370 system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl
371 system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl
372 system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl
373 system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
374 system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl
375 system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl
376 system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl
377 system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl
378 system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl
379 system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl
380 system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl
381 system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl
382 system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl
383 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
384 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
385 system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl
386 system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl
387 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
388 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
389 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
390 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
391 system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed
392 system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
393 system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
394 system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed
395 system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed
396 system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
397 system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
398 system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
399 system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
400 system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed
401 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
402 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
403 system.cpu.kern.callpal::total 192947 # number of callpals executed
404 system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches
405 system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
406 system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
407 system.cpu.kern.mode_good::kernel 1908
408 system.cpu.kern.mode_good::user 1738
409 system.cpu.kern.mode_good::idle 170
410 system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches
411 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
412 system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
413 system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches
414 system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode
415 system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode
416 system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode
417 system.cpu.kern.swap_context 4178 # number of times the context was actually changed
418 system.cpu.committedInsts 56195014 # Number of instructions committed
419 system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed
420 system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses
421 system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
422 system.cpu.num_func_calls 1483758 # number of times a function call or return occured
423 system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls
424 system.cpu.num_int_insts 52066552 # number of integer instructions
425 system.cpu.num_fp_insts 324460 # number of float instructions
426 system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read
427 system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written
428 system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
429 system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
430 system.cpu.num_mem_refs 15476659 # number of memory refs
431 system.cpu.num_load_insts 9103400 # Number of load instructions
432 system.cpu.num_store_insts 6373259 # Number of store instructions
433 system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles
434 system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles
435 system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles
436 system.cpu.idle_fraction 0.930908 # Percentage of idle cycles
437 system.cpu.Branches 8424278 # Number of branches fetched
438 system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction
439 system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction
440 system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction
441 system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction
442 system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction
443 system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction
444 system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction
445 system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction
446 system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction
447 system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction
448 system.cpu.op_class::FloatMisc 0 0.00% 70.35% # Class of executed instruction
449 system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction
450 system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction
451 system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction
452 system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction
453 system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction
454 system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction
455 system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction
456 system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction
457 system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction
458 system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction
459 system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction
460 system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction
461 system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction
462 system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction
463 system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction
464 system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction
465 system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction
466 system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction
467 system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
468 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
469 system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
470 system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction
471 system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction
472 system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction
473 system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction
474 system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction
475 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
476 system.cpu.op_class::total 56206855 # Class of executed instruction
477 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
478 system.cpu.dcache.tags.replacements 1390804 # number of replacements
479 system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use
480 system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks.
481 system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks.
482 system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks.
483 system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit.
484 system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor
485 system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy
486 system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy
487 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
488 system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
489 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
490 system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
491 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
492 system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses
493 system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses
494 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
495 system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits
496 system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits
497 system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits
498 system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits
499 system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits
500 system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits
501 system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits
502 system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits
503 system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits
504 system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits
505 system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits
506 system.cpu.dcache.overall_hits::total 13669481 # number of overall hits
507 system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses
508 system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses
509 system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses
510 system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses
511 system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses
512 system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses
513 system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses
514 system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses
515 system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses
516 system.cpu.dcache.overall_misses::total 1374056 # number of overall misses
517 system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles
518 system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles
519 system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles
520 system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles
521 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles
522 system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles
523 system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles
524 system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles
525 system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles
526 system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles
527 system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses)
528 system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses)
529 system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses)
530 system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses)
531 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses)
532 system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses)
533 system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses)
534 system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses)
535 system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses
536 system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses
537 system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses
538 system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses
539 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses
540 system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses
541 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses
542 system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses
543 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses
544 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses
545 system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses
546 system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses
547 system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses
548 system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses
549 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency
550 system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency
551 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency
552 system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency
553 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency
554 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency
555 system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency
556 system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency
557 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency
558 system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency
559 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
560 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
561 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
562 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
563 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
564 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
565 system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks
566 system.cpu.dcache.writebacks::total 835203 # number of writebacks
567 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses
568 system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses
569 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses
570 system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses
571 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses
572 system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses
573 system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses
574 system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses
575 system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses
576 system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses
577 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
578 system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
579 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable
580 system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable
581 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses
582 system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses
583 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles
584 system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles
585 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles
586 system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles
587 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles
588 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles
589 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles
590 system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles
591 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles
592 system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles
593 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles
594 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles
595 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles
596 system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles
597 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses
598 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses
599 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049420 # mshr miss rate for WriteReq accesses
600 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049420 # mshr miss rate for WriteReq accesses
601 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086269 # mshr miss rate for LoadLockedReq accesses
602 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086269 # mshr miss rate for LoadLockedReq accesses
603 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses
604 system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses
605 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses
606 system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses
607 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency
608 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency
609 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency
610 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency
611 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency
612 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency
613 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency
614 system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency
615 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency
616 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency
617 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency
618 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency
619 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency
620 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency
621 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
622 system.cpu.icache.tags.replacements 928685 # number of replacements
623 system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use
624 system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks.
625 system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks.
626 system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks.
627 system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit.
628 system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor
629 system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy
630 system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy
631 system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
632 system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
633 system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
634 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
635 system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
636 system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
637 system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses
638 system.cpu.icache.tags.data_accesses 57136212 # Number of data accesses
639 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
640 system.cpu.icache.ReadReq_hits::cpu.inst 55277500 # number of ReadReq hits
641 system.cpu.icache.ReadReq_hits::total 55277500 # number of ReadReq hits
642 system.cpu.icache.demand_hits::cpu.inst 55277500 # number of demand (read+write) hits
643 system.cpu.icache.demand_hits::total 55277500 # number of demand (read+write) hits
644 system.cpu.icache.overall_hits::cpu.inst 55277500 # number of overall hits
645 system.cpu.icache.overall_hits::total 55277500 # number of overall hits
646 system.cpu.icache.ReadReq_misses::cpu.inst 929356 # number of ReadReq misses
647 system.cpu.icache.ReadReq_misses::total 929356 # number of ReadReq misses
648 system.cpu.icache.demand_misses::cpu.inst 929356 # number of demand (read+write) misses
649 system.cpu.icache.demand_misses::total 929356 # number of demand (read+write) misses
650 system.cpu.icache.overall_misses::cpu.inst 929356 # number of overall misses
651 system.cpu.icache.overall_misses::total 929356 # number of overall misses
652 system.cpu.icache.ReadReq_miss_latency::cpu.inst 13310087000 # number of ReadReq miss cycles
653 system.cpu.icache.ReadReq_miss_latency::total 13310087000 # number of ReadReq miss cycles
654 system.cpu.icache.demand_miss_latency::cpu.inst 13310087000 # number of demand (read+write) miss cycles
655 system.cpu.icache.demand_miss_latency::total 13310087000 # number of demand (read+write) miss cycles
656 system.cpu.icache.overall_miss_latency::cpu.inst 13310087000 # number of overall miss cycles
657 system.cpu.icache.overall_miss_latency::total 13310087000 # number of overall miss cycles
658 system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses)
659 system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses)
660 system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses
661 system.cpu.icache.demand_accesses::total 56206856 # number of demand (read+write) accesses
662 system.cpu.icache.overall_accesses::cpu.inst 56206856 # number of overall (read+write) accesses
663 system.cpu.icache.overall_accesses::total 56206856 # number of overall (read+write) accesses
664 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016535 # miss rate for ReadReq accesses
665 system.cpu.icache.ReadReq_miss_rate::total 0.016535 # miss rate for ReadReq accesses
666 system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 # miss rate for demand accesses
667 system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses
668 system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses
669 system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses
670 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.838994 # average ReadReq miss latency
671 system.cpu.icache.ReadReq_avg_miss_latency::total 14321.838994 # average ReadReq miss latency
672 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency
673 system.cpu.icache.demand_avg_miss_latency::total 14321.838994 # average overall miss latency
674 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency
675 system.cpu.icache.overall_avg_miss_latency::total 14321.838994 # average overall miss latency
676 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
677 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
678 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
679 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
680 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
681 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
682 system.cpu.icache.writebacks::writebacks 928685 # number of writebacks
683 system.cpu.icache.writebacks::total 928685 # number of writebacks
684 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929356 # number of ReadReq MSHR misses
685 system.cpu.icache.ReadReq_mshr_misses::total 929356 # number of ReadReq MSHR misses
686 system.cpu.icache.demand_mshr_misses::cpu.inst 929356 # number of demand (read+write) MSHR misses
687 system.cpu.icache.demand_mshr_misses::total 929356 # number of demand (read+write) MSHR misses
688 system.cpu.icache.overall_mshr_misses::cpu.inst 929356 # number of overall MSHR misses
689 system.cpu.icache.overall_mshr_misses::total 929356 # number of overall MSHR misses
690 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380731000 # number of ReadReq MSHR miss cycles
691 system.cpu.icache.ReadReq_mshr_miss_latency::total 12380731000 # number of ReadReq MSHR miss cycles
692 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380731000 # number of demand (read+write) MSHR miss cycles
693 system.cpu.icache.demand_mshr_miss_latency::total 12380731000 # number of demand (read+write) MSHR miss cycles
694 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380731000 # number of overall MSHR miss cycles
695 system.cpu.icache.overall_mshr_miss_latency::total 12380731000 # number of overall MSHR miss cycles
696 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses
697 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses
698 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses
699 system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses
700 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses
701 system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses
702 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994 # average ReadReq mshr miss latency
703 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994 # average ReadReq mshr miss latency
704 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency
705 system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency
706 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency
707 system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency
708 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
709 system.cpu.l2cache.tags.replacements 336397 # number of replacements
710 system.cpu.l2cache.tags.tagsinuse 65387.710870 # Cycle average of tags in use
711 system.cpu.l2cache.tags.total_refs 4236311 # Total number of references to valid blocks.
712 system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks.
713 system.cpu.l2cache.tags.avg_refs 10.540211 # Average number of references to valid blocks.
714 system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit.
715 system.cpu.l2cache.tags.occ_blocks::writebacks 234.658565 # Average occupied blocks per requestor
716 system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor
717 system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor
718 system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy
719 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy
720 system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy
721 system.cpu.l2cache.tags.occ_percent::total 0.997737 # Average percentage of cache occupancy
722 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
723 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id
724 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id
725 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id
726 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id
727 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
728 system.cpu.l2cache.tags.tag_accesses 37511410 # Number of tag accesses
729 system.cpu.l2cache.tags.data_accesses 37511410 # Number of data accesses
730 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
731 system.cpu.l2cache.WritebackDirty_hits::writebacks 835203 # number of WritebackDirty hits
732 system.cpu.l2cache.WritebackDirty_hits::total 835203 # number of WritebackDirty hits
733 system.cpu.l2cache.WritebackClean_hits::writebacks 928452 # number of WritebackClean hits
734 system.cpu.l2cache.WritebackClean_hits::total 928452 # number of WritebackClean hits
735 system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits
736 system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits
737 system.cpu.l2cache.ReadExReq_hits::cpu.data 187488 # number of ReadExReq hits
738 system.cpu.l2cache.ReadExReq_hits::total 187488 # number of ReadExReq hits
739 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916138 # number of ReadCleanReq hits
740 system.cpu.l2cache.ReadCleanReq_hits::total 916138 # number of ReadCleanReq hits
741 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815038 # number of ReadSharedReq hits
742 system.cpu.l2cache.ReadSharedReq_hits::total 815038 # number of ReadSharedReq hits
743 system.cpu.l2cache.demand_hits::cpu.inst 916138 # number of demand (read+write) hits
744 system.cpu.l2cache.demand_hits::cpu.data 1002526 # number of demand (read+write) hits
745 system.cpu.l2cache.demand_hits::total 1918664 # number of demand (read+write) hits
746 system.cpu.l2cache.overall_hits::cpu.inst 916138 # number of overall hits
747 system.cpu.l2cache.overall_hits::cpu.data 1002526 # number of overall hits
748 system.cpu.l2cache.overall_hits::total 1918664 # number of overall hits
749 system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
750 system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
751 system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses
752 system.cpu.l2cache.ReadExReq_misses::total 116817 # number of ReadExReq misses
753 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13198 # number of ReadCleanReq misses
754 system.cpu.l2cache.ReadCleanReq_misses::total 13198 # number of ReadCleanReq misses
755 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses
756 system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses
757 system.cpu.l2cache.demand_misses::cpu.inst 13198 # number of demand (read+write) misses
758 system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses
759 system.cpu.l2cache.demand_misses::total 401989 # number of demand (read+write) misses
760 system.cpu.l2cache.overall_misses::cpu.inst 13198 # number of overall misses
761 system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses
762 system.cpu.l2cache.overall_misses::total 401989 # number of overall misses
763 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles
764 system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles
765 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10708900500 # number of ReadExReq miss cycles
766 system.cpu.l2cache.ReadExReq_miss_latency::total 10708900500 # number of ReadExReq miss cycles
767 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353922000 # number of ReadCleanReq miss cycles
768 system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353922000 # number of ReadCleanReq miss cycles
769 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993208500 # number of ReadSharedReq miss cycles
770 system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993208500 # number of ReadSharedReq miss cycles
771 system.cpu.l2cache.demand_miss_latency::cpu.inst 1353922000 # number of demand (read+write) miss cycles
772 system.cpu.l2cache.demand_miss_latency::cpu.data 32702109000 # number of demand (read+write) miss cycles
773 system.cpu.l2cache.demand_miss_latency::total 34056031000 # number of demand (read+write) miss cycles
774 system.cpu.l2cache.overall_miss_latency::cpu.inst 1353922000 # number of overall miss cycles
775 system.cpu.l2cache.overall_miss_latency::cpu.data 32702109000 # number of overall miss cycles
776 system.cpu.l2cache.overall_miss_latency::total 34056031000 # number of overall miss cycles
777 system.cpu.l2cache.WritebackDirty_accesses::writebacks 835203 # number of WritebackDirty accesses(hits+misses)
778 system.cpu.l2cache.WritebackDirty_accesses::total 835203 # number of WritebackDirty accesses(hits+misses)
779 system.cpu.l2cache.WritebackClean_accesses::writebacks 928452 # number of WritebackClean accesses(hits+misses)
780 system.cpu.l2cache.WritebackClean_accesses::total 928452 # number of WritebackClean accesses(hits+misses)
781 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
782 system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
783 system.cpu.l2cache.ReadExReq_accesses::cpu.data 304305 # number of ReadExReq accesses(hits+misses)
784 system.cpu.l2cache.ReadExReq_accesses::total 304305 # number of ReadExReq accesses(hits+misses)
785 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929336 # number of ReadCleanReq accesses(hits+misses)
786 system.cpu.l2cache.ReadCleanReq_accesses::total 929336 # number of ReadCleanReq accesses(hits+misses)
787 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087012 # number of ReadSharedReq accesses(hits+misses)
788 system.cpu.l2cache.ReadSharedReq_accesses::total 1087012 # number of ReadSharedReq accesses(hits+misses)
789 system.cpu.l2cache.demand_accesses::cpu.inst 929336 # number of demand (read+write) accesses
790 system.cpu.l2cache.demand_accesses::cpu.data 1391317 # number of demand (read+write) accesses
791 system.cpu.l2cache.demand_accesses::total 2320653 # number of demand (read+write) accesses
792 system.cpu.l2cache.overall_accesses::cpu.inst 929336 # number of overall (read+write) accesses
793 system.cpu.l2cache.overall_accesses::cpu.data 1391317 # number of overall (read+write) accesses
794 system.cpu.l2cache.overall_accesses::total 2320653 # number of overall (read+write) accesses
795 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses
796 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses
797 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383881 # miss rate for ReadExReq accesses
798 system.cpu.l2cache.ReadExReq_miss_rate::total 0.383881 # miss rate for ReadExReq accesses
799 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses
800 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses
801 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250203 # miss rate for ReadSharedReq accesses
802 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250203 # miss rate for ReadSharedReq accesses
803 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses
804 system.cpu.l2cache.demand_miss_rate::cpu.data 0.279441 # miss rate for demand accesses
805 system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses
806 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses
807 system.cpu.l2cache.overall_miss_rate::cpu.data 0.279441 # miss rate for overall accesses
808 system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses
809 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency
810 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency
811 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91672.449215 # average ReadExReq miss latency
812 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91672.449215 # average ReadExReq miss latency
813 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102585.391726 # average ReadCleanReq miss latency
814 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102585.391726 # average ReadCleanReq miss latency
815 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80865.113945 # average ReadSharedReq miss latency
816 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80865.113945 # average ReadSharedReq miss latency
817 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency
818 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency
819 system.cpu.l2cache.demand_avg_miss_latency::total 84718.813201 # average overall miss latency
820 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency
821 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency
822 system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201 # average overall miss latency
823 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
824 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
825 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
826 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
827 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
828 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
829 system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks
830 system.cpu.l2cache.writebacks::total 74253 # number of writebacks
831 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
832 system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
833 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116817 # number of ReadExReq MSHR misses
834 system.cpu.l2cache.ReadExReq_mshr_misses::total 116817 # number of ReadExReq MSHR misses
835 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13198 # number of ReadCleanReq MSHR misses
836 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13198 # number of ReadCleanReq MSHR misses
837 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses
838 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses
839 system.cpu.l2cache.demand_mshr_misses::cpu.inst 13198 # number of demand (read+write) MSHR misses
840 system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses
841 system.cpu.l2cache.demand_mshr_misses::total 401989 # number of demand (read+write) MSHR misses
842 system.cpu.l2cache.overall_mshr_misses::cpu.inst 13198 # number of overall MSHR misses
843 system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses
844 system.cpu.l2cache.overall_mshr_misses::total 401989 # number of overall MSHR misses
845 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
846 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
847 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable
848 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable
849 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses
850 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses
851 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles
852 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles
853 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles
854 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles
855 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles
856 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles
857 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles
858 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles
859 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles
860 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles
861 system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles
862 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles
863 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles
864 system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles
865 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles
866 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles
867 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles
868 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles
869 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses
870 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses
871 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses
872 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses
873 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses
874 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses
875 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses
876 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses
877 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses
878 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses
879 system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses
880 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses
881 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses
882 system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses
883 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency
884 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency
885 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency
886 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency
887 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency
888 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency
889 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency
890 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency
891 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency
892 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency
893 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency
894 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency
895 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency
896 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency
897 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency
898 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency
899 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency
900 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency
901 system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter.
902 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data.
903 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
904 system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter.
905 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
906 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
907 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
908 system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
909 system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution
910 system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution
911 system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution
912 system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution
913 system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution
914 system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution
915 system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
916 system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
917 system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution
918 system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution
919 system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution
920 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution
921 system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution
922 system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution
923 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes)
924 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes)
925 system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes)
926 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes)
927 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes)
928 system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes)
929 system.cpu.toL2Bus.snoops 336955 # Total snoops (count)
930 system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes)
931 system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram
932 system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram
933 system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram
934 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
935 system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram
936 system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram
937 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
938 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
939 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
940 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
941 system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram
942 system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks)
943 system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
944 system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks)
945 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
946 system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks)
947 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
948 system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks)
949 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
950 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
951 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
952 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
953 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
954 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
955 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
956 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
957 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
958 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
959 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
960 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
961 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
962 system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
963 system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
964 system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
965 system.iobus.trans_dist::WriteReq 51204 # Transaction distribution
966 system.iobus.trans_dist::WriteResp 51204 # Transaction distribution
967 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes)
968 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
969 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
970 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
971 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
972 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
973 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
974 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
975 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
976 system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes)
977 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
978 system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
979 system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes)
980 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes)
981 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
982 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
983 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
984 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
985 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
986 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
987 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
988 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
989 system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes)
990 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
991 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
992 system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes)
993 system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks)
994 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
995 system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks)
996 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
997 system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
998 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
999 system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
1000 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1001 system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks)
1002 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1003 system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks)
1004 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1005 system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks)
1006 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1007 system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks)
1008 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1009 system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1010 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1011 system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks)
1012 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1013 system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks)
1014 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1015 system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1016 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1017 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1018 system.iocache.tags.replacements 41685 # number of replacements
1019 system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use
1020 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1021 system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1022 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1023 system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit.
1024 system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor
1025 system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy
1026 system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy
1027 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1028 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1029 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1030 system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1031 system.iocache.tags.data_accesses 375525 # Number of data accesses
1032 system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1033 system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1034 system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1035 system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1036 system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1037 system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1038 system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1039 system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1040 system.iocache.overall_misses::total 41725 # number of overall misses
1041 system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles
1042 system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles
1043 system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles
1044 system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles
1045 system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles
1046 system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles
1047 system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles
1048 system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles
1049 system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1050 system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1051 system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1052 system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1053 system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
1054 system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
1055 system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
1056 system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1057 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1058 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1059 system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1060 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1061 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1062 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1063 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1064 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1065 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency
1066 system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency
1067 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency
1068 system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency
1069 system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency
1070 system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency
1071 system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency
1072 system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency
1073 system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked
1074 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1075 system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
1076 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1077 system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked
1078 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1079 system.iocache.writebacks::writebacks 41512 # number of writebacks
1080 system.iocache.writebacks::total 41512 # number of writebacks
1081 system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1082 system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1083 system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1084 system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1085 system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
1086 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
1087 system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
1088 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1089 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles
1090 system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles
1091 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles
1092 system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles
1093 system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles
1094 system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles
1095 system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles
1096 system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles
1097 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1098 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1099 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1100 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1101 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1102 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1103 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1104 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1105 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency
1106 system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency
1107 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency
1108 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency
1109 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency
1110 system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency
1111 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency
1112 system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency
1113 system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter.
1114 system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1115 system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1116 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1117 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1118 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1119 system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1120 system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1121 system.membus.trans_dist::ReadResp 292275 # Transaction distribution
1122 system.membus.trans_dist::WriteReq 9652 # Transaction distribution
1123 system.membus.trans_dist::WriteResp 9652 # Transaction distribution
1124 system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution
1125 system.membus.trans_dist::CleanEvict 261592 # Transaction distribution
1126 system.membus.trans_dist::UpgradeReq 136 # Transaction distribution
1127 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1128 system.membus.trans_dist::ReadExReq 116686 # Transaction distribution
1129 system.membus.trans_dist::ReadExResp 116686 # Transaction distribution
1130 system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution
1131 system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1132 system.membus.trans_dist::InvalidateResp 124 # Transaction distribution
1133 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes)
1134 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes)
1135 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes)
1136 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
1137 system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
1138 system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes)
1139 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes)
1140 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes)
1141 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes)
1142 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
1143 system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
1144 system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes)
1145 system.membus.snoops 555 # Total snoops (count)
1146 system.membus.snoopTraffic 27456 # Total snoop traffic (bytes)
1147 system.membus.snoop_fanout::samples 460301 # Request fanout histogram
1148 system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram
1149 system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram
1150 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1151 system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram
1152 system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram
1153 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1154 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1155 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1156 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1157 system.membus.snoop_fanout::total 460301 # Request fanout histogram
1158 system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks)
1159 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1160 system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks)
1161 system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1162 system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks)
1163 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1164 system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks)
1165 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1166 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1167 system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1168 system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1169 system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1170 system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1171 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1172 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1173 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1174 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1175 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1176 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1177 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1178 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1179 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1180 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1181 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1182 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1183 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1184 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1185 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1186 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1187 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1188 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1189 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1190 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1191 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1192 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1193 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1194 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1195 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1196 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1197 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1198 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1199 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1200 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1201 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1202 system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1203 system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1204 system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1205 system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1206 system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1207 system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1208 system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1209 system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1210 system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1211 system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1212 system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1213 system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1214 system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1215 system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1216 system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1217 system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1218 system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1219 system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1220 system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1221 system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1222 system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1223 system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1224 system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1226 ---------- End Simulation Statistics ----------
projects / gem5.git / blob