2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.915549 # Number of seconds simulated
4 sim_ticks 1915548867000 # Number of ticks simulated
5 final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1998214 # Simulator instruction rate (inst/s)
8 host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 68184353129 # Simulator tick rate (ticks/s)
10 host_mem_usage 288188 # Number of bytes of host memory used
11 host_seconds 28.09 # Real time elapsed on the host
12 sim_insts 56137087 # Number of instructions simulated
13 sim_ops 56137087 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 29663360 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 10122368 # Number of bytes written to this memory
17 system.physmem.num_reads 463490 # Number of read requests responded to by this memory
18 system.physmem.num_writes 158162 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s)
24 system.l2c.replacements 389289 # number of replacements
25 system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
26 system.l2c.total_refs 2311163 # Total number of references to valid blocks.
27 system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
28 system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
29 system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
30 system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
31 system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
32 system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
33 system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
34 system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
35 system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
36 system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
37 system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits
38 system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits
39 system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
40 system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits
41 system.l2c.Writeback_hits::total 826671 # number of Writeback hits
42 system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
43 system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
44 system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits
45 system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
46 system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits
47 system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits
48 system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
49 system.l2c.overall_hits::cpu.inst 913599 # number of overall hits
50 system.l2c.overall_hits::cpu.data 982740 # number of overall hits
51 system.l2c.overall_hits::total 1896339 # number of overall hits
52 system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses
53 system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses
54 system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
55 system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
56 system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
57 system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses
58 system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
59 system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses
60 system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses
61 system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
62 system.l2c.overall_misses::cpu.inst 14735 # number of overall misses
63 system.l2c.overall_misses::cpu.data 407697 # number of overall misses
64 system.l2c.overall_misses::total 422432 # number of overall misses
65 system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles
66 system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles
67 system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles
68 system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
69 system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
70 system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles
71 system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles
72 system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles
73 system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles
74 system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles
75 system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles
76 system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
77 system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
78 system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses)
79 system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses)
80 system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
81 system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses)
82 system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
83 system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
84 system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
85 system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
86 system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
87 system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses
88 system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses
89 system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
90 system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses
91 system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses
92 system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
93 system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses
94 system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses
95 system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses
96 system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses
97 system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses
98 system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses
99 system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses
100 system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses
101 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency
102 system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency
103 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency
104 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency
105 system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
106 system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
107 system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
108 system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
109 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
110 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
111 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
112 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
113 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
114 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
115 system.l2c.fast_writes 0 # number of fast writes performed
116 system.l2c.cache_copies 0 # number of cache copies performed
117 system.l2c.writebacks::writebacks 116650 # number of writebacks
118 system.l2c.writebacks::total 116650 # number of writebacks
119 system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses
120 system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses
121 system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses
122 system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
123 system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
124 system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses
125 system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses
126 system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses
127 system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses
128 system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses
129 system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses
130 system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses
131 system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses
132 system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles
133 system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles
134 system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles
135 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles
136 system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles
137 system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles
138 system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles
139 system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles
140 system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles
141 system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles
142 system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles
143 system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles
144 system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles
145 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles
146 system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles
147 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles
148 system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles
149 system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles
150 system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles
151 system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses
152 system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses
153 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses
154 system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses
155 system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses
156 system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses
157 system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses
158 system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses
159 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency
160 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency
161 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency
162 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency
163 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
164 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
165 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
166 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
167 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
168 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
169 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
170 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
171 system.iocache.replacements 41685 # number of replacements
172 system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
173 system.iocache.total_refs 0 # Total number of references to valid blocks.
174 system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
175 system.iocache.avg_refs 0 # Average number of references to valid blocks.
176 system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
177 system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor
178 system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy
179 system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy
180 system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
181 system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
182 system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
183 system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
184 system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
185 system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
186 system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
187 system.iocache.overall_misses::total 41725 # number of overall misses
188 system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles
189 system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles
190 system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles
191 system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles
192 system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles
193 system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles
194 system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles
195 system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles
196 system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
197 system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
198 system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
199 system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
200 system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
201 system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
202 system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
203 system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
204 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
205 system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
206 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
207 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
208 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency
209 system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency
210 system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
211 system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
212 system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
213 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
214 system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
215 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
216 system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
217 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
218 system.iocache.fast_writes 0 # number of fast writes performed
219 system.iocache.cache_copies 0 # number of cache copies performed
220 system.iocache.writebacks::writebacks 41512 # number of writebacks
221 system.iocache.writebacks::total 41512 # number of writebacks
222 system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
223 system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
224 system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
225 system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
226 system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
227 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
228 system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
229 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
230 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles
231 system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles
232 system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles
233 system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles
234 system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles
235 system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles
236 system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles
237 system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles
238 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
239 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
240 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
241 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
242 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency
243 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency
244 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
245 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
246 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
247 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
248 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
249 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
250 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
251 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
252 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
253 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
254 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
255 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
256 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
257 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
258 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
259 system.cpu.dtb.fetch_hits 0 # ITB hits
260 system.cpu.dtb.fetch_misses 0 # ITB misses
261 system.cpu.dtb.fetch_acv 0 # ITB acv
262 system.cpu.dtb.fetch_accesses 0 # ITB accesses
263 system.cpu.dtb.read_hits 9057511 # DTB read hits
264 system.cpu.dtb.read_misses 10312 # DTB read misses
265 system.cpu.dtb.read_acv 210 # DTB read access violations
266 system.cpu.dtb.read_accesses 728817 # DTB read accesses
267 system.cpu.dtb.write_hits 6352446 # DTB write hits
268 system.cpu.dtb.write_misses 1140 # DTB write misses
269 system.cpu.dtb.write_acv 157 # DTB write access violations
270 system.cpu.dtb.write_accesses 291929 # DTB write accesses
271 system.cpu.dtb.data_hits 15409957 # DTB hits
272 system.cpu.dtb.data_misses 11452 # DTB misses
273 system.cpu.dtb.data_acv 367 # DTB access violations
274 system.cpu.dtb.data_accesses 1020746 # DTB accesses
275 system.cpu.itb.fetch_hits 4973520 # ITB hits
276 system.cpu.itb.fetch_misses 4997 # ITB misses
277 system.cpu.itb.fetch_acv 184 # ITB acv
278 system.cpu.itb.fetch_accesses 4978517 # ITB accesses
279 system.cpu.itb.read_hits 0 # DTB read hits
280 system.cpu.itb.read_misses 0 # DTB read misses
281 system.cpu.itb.read_acv 0 # DTB read access violations
282 system.cpu.itb.read_accesses 0 # DTB read accesses
283 system.cpu.itb.write_hits 0 # DTB write hits
284 system.cpu.itb.write_misses 0 # DTB write misses
285 system.cpu.itb.write_acv 0 # DTB write access violations
286 system.cpu.itb.write_accesses 0 # DTB write accesses
287 system.cpu.itb.data_hits 0 # DTB hits
288 system.cpu.itb.data_misses 0 # DTB misses
289 system.cpu.itb.data_acv 0 # DTB access violations
290 system.cpu.itb.data_accesses 0 # DTB accesses
291 system.cpu.numCycles 3831097734 # number of cpu cycles simulated
292 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
293 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
294 system.cpu.committedInsts 56137087 # Number of instructions committed
295 system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed
296 system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
297 system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
298 system.cpu.num_func_calls 1482242 # number of times a function call or return occured
299 system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
300 system.cpu.num_int_insts 52011214 # number of integer instructions
301 system.cpu.num_fp_insts 324192 # number of float instructions
302 system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
303 system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
304 system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
305 system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
306 system.cpu.num_mem_refs 15462519 # number of memory refs
307 system.cpu.num_load_insts 9094324 # Number of load instructions
308 system.cpu.num_store_insts 6368195 # Number of store instructions
309 system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
310 system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
311 system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
312 system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
313 system.cpu.kern.inst.arm 0 # number of arm instructions executed
314 system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
315 system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
316 system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
317 system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
318 system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
319 system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
320 system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
321 system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
322 system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
323 system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
324 system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
325 system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
326 system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
327 system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
328 system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
329 system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
330 system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
331 system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
332 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
333 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
334 system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
335 system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
336 system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
337 system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
338 system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
339 system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
340 system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
341 system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
342 system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
343 system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
344 system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
345 system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
346 system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
347 system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
348 system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
349 system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
350 system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
351 system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
352 system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
353 system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
354 system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
355 system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
356 system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
357 system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
358 system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
359 system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
360 system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
361 system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
362 system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
363 system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
364 system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
365 system.cpu.kern.syscall::total 326 # number of syscalls executed
366 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
367 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
368 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
369 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
370 system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
371 system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
372 system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
373 system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
374 system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
375 system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
376 system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
377 system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
378 system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
379 system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
380 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
381 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
382 system.cpu.kern.callpal::total 192868 # number of callpals executed
383 system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
384 system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
385 system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
386 system.cpu.kern.mode_good::kernel 1906
387 system.cpu.kern.mode_good::user 1738
388 system.cpu.kern.mode_good::idle 168
389 system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
390 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
391 system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
392 system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches
393 system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
394 system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
395 system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
396 system.cpu.kern.swap_context 4174 # number of times the context was actually changed
397 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
398 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
399 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
400 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
401 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
402 system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
403 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
404 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
405 system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
406 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
407 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
408 system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
409 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
410 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
411 system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
412 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
413 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
414 system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
415 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
416 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
417 system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
418 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
419 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
420 system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
421 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
422 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
423 system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
424 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
425 system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
426 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
427 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
428 system.cpu.icache.replacements 927683 # number of replacements
429 system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
430 system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
431 system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
432 system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
433 system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
434 system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor
435 system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy
436 system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy
437 system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits
438 system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
439 system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits
440 system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
441 system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits
442 system.cpu.icache.overall_hits::total 55220553 # number of overall hits
443 system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses
444 system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
445 system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses
446 system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
447 system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses
448 system.cpu.icache.overall_misses::total 928354 # number of overall misses
449 system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles
450 system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles
451 system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles
452 system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles
453 system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles
454 system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles
455 system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses)
456 system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
457 system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses
458 system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
459 system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses
460 system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
461 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses
462 system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses
463 system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses
464 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency
465 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
466 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
467 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
468 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
469 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
470 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
471 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
472 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
473 system.cpu.icache.fast_writes 0 # number of fast writes performed
474 system.cpu.icache.cache_copies 0 # number of cache copies performed
475 system.cpu.icache.writebacks::writebacks 85 # number of writebacks
476 system.cpu.icache.writebacks::total 85 # number of writebacks
477 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses
478 system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses
479 system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses
480 system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses
481 system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses
482 system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses
483 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles
484 system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles
485 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles
486 system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles
487 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles
488 system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles
489 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses
490 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses
491 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses
492 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency
493 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
494 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
495 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
496 system.cpu.dcache.replacements 1390115 # number of replacements
497 system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
498 system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
499 system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
500 system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
501 system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
502 system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor
503 system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy
504 system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy
505 system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits
506 system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
507 system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits
508 system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
509 system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits
510 system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
511 system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits
512 system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
513 system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits
514 system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
515 system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits
516 system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
517 system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses
518 system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
519 system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses
520 system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
521 system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses
522 system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
523 system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses
524 system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
525 system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses
526 system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
527 system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles
528 system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles
529 system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles
530 system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles
531 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles
532 system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles
533 system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles
534 system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles
535 system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles
536 system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles
537 system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses)
538 system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
539 system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses)
540 system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
541 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses)
542 system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
543 system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses)
544 system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
545 system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses
546 system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
547 system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses
548 system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
549 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses
550 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses
551 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses
552 system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
553 system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
554 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency
555 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency
556 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency
557 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
558 system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
559 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
560 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
561 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
562 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
563 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
564 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
565 system.cpu.dcache.fast_writes 0 # number of fast writes performed
566 system.cpu.dcache.cache_copies 0 # number of cache copies performed
567 system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks
568 system.cpu.dcache.writebacks::total 826586 # number of writebacks
569 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses
570 system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses
571 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
572 system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
573 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses
574 system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses
575 system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses
576 system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses
577 system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses
578 system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses
579 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles
580 system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles
581 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles
582 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles
583 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles
584 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles
585 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles
586 system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
587 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
588 system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
589 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
590 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
591 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
592 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
593 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
594 system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
595 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
596 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
597 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
598 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
599 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
600 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
601 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
602 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
603 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
604 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
605 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
606 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
607 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
608 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
610 ---------- End Simulation Statistics ----------
projects / gem5.git / blob