2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.919439 # Number of seconds simulated
4 sim_ticks 1919439025000 # Number of ticks simulated
5 final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1426339 # Simulator instruction rate (inst/s)
8 host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 48799693433 # Simulator tick rate (ticks/s)
10 host_mem_usage 367228 # Number of bytes of host memory used
11 host_seconds 39.33 # Real time elapsed on the host
12 sim_insts 56102180 # Number of instructions simulated
13 sim_ops 56102180 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory
18 system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory
23 system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory
27 system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory
30 system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory
32 system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.readReqs 401995 # Number of read requests accepted
47 system.physmem.writeReqs 115732 # Number of write requests accepted
48 system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue
49 system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue
50 system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM
51 system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
52 system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM
53 system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side
54 system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side
55 system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
56 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
57 system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write
58 system.physmem.perBankRdBursts::0 25161 # Per bank write bursts
59 system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
60 system.physmem.perBankRdBursts::2 25618 # Per bank write bursts
61 system.physmem.perBankRdBursts::3 25536 # Per bank write bursts
62 system.physmem.perBankRdBursts::4 24982 # Per bank write bursts
63 system.physmem.perBankRdBursts::5 24977 # Per bank write bursts
64 system.physmem.perBankRdBursts::6 24228 # Per bank write bursts
65 system.physmem.perBankRdBursts::7 24506 # Per bank write bursts
66 system.physmem.perBankRdBursts::8 25158 # Per bank write bursts
67 system.physmem.perBankRdBursts::9 24823 # Per bank write bursts
68 system.physmem.perBankRdBursts::10 25363 # Per bank write bursts
69 system.physmem.perBankRdBursts::11 24839 # Per bank write bursts
70 system.physmem.perBankRdBursts::12 24418 # Per bank write bursts
71 system.physmem.perBankRdBursts::13 25388 # Per bank write bursts
72 system.physmem.perBankRdBursts::14 25795 # Per bank write bursts
73 system.physmem.perBankRdBursts::15 25481 # Per bank write bursts
74 system.physmem.perBankWrBursts::0 7550 # Per bank write bursts
75 system.physmem.perBankWrBursts::1 7529 # Per bank write bursts
76 system.physmem.perBankWrBursts::2 7880 # Per bank write bursts
77 system.physmem.perBankWrBursts::3 7553 # Per bank write bursts
78 system.physmem.perBankWrBursts::4 7115 # Per bank write bursts
79 system.physmem.perBankWrBursts::5 6983 # Per bank write bursts
80 system.physmem.perBankWrBursts::6 6321 # Per bank write bursts
81 system.physmem.perBankWrBursts::7 6315 # Per bank write bursts
82 system.physmem.perBankWrBursts::8 7293 # Per bank write bursts
83 system.physmem.perBankWrBursts::9 6555 # Per bank write bursts
84 system.physmem.perBankWrBursts::10 7205 # Per bank write bursts
85 system.physmem.perBankWrBursts::11 6861 # Per bank write bursts
86 system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
87 system.physmem.perBankWrBursts::13 7821 # Per bank write bursts
88 system.physmem.perBankWrBursts::14 7980 # Per bank write bursts
89 system.physmem.perBankWrBursts::15 7780 # Per bank write bursts
90 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
91 system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
92 system.physmem.totGap 1919427104000 # Total gap between requests
93 system.physmem.readPktSize::0 0 # Read request sizes (log2)
94 system.physmem.readPktSize::1 0 # Read request sizes (log2)
95 system.physmem.readPktSize::2 0 # Read request sizes (log2)
96 system.physmem.readPktSize::3 0 # Read request sizes (log2)
97 system.physmem.readPktSize::4 0 # Read request sizes (log2)
98 system.physmem.readPktSize::5 0 # Read request sizes (log2)
99 system.physmem.readPktSize::6 401995 # Read request sizes (log2)
100 system.physmem.writePktSize::0 0 # Write request sizes (log2)
101 system.physmem.writePktSize::1 0 # Write request sizes (log2)
102 system.physmem.writePktSize::2 0 # Write request sizes (log2)
103 system.physmem.writePktSize::3 0 # Write request sizes (log2)
104 system.physmem.writePktSize::4 0 # Write request sizes (log2)
105 system.physmem.writePktSize::5 0 # Write request sizes (log2)
106 system.physmem.writePktSize::6 115732 # Write request sizes (log2)
107 system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
139 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
203 system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation
217 system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes
225 system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads
265 system.physmem.totQLat 2129492750 # Total ticks spent queuing
266 system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM
267 system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers
268 system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst
269 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
270 system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst
271 system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s
272 system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s
273 system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s
274 system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s
275 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
276 system.physmem.busUtil 0.13 # Data bus utilization in percentage
277 system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
278 system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
279 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
280 system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
281 system.physmem.readRowHits 359991 # Number of row buffer hits during reads
282 system.physmem.writeRowHits 93535 # Number of row buffer hits during writes
283 system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads
284 system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes
285 system.physmem.avgGap 3707411.64 # Average gap between requests
286 system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined
287 system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states
288 system.physmem.memoryStateTime::REF 64094160000 # Time in different power states
289 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
290 system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states
291 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
292 system.membus.trans_dist::ReadReq 292357 # Transaction distribution
293 system.membus.trans_dist::ReadResp 292357 # Transaction distribution
294 system.membus.trans_dist::WriteReq 9649 # Transaction distribution
295 system.membus.trans_dist::WriteResp 9649 # Transaction distribution
296 system.membus.trans_dist::Writeback 74180 # Transaction distribution
297 system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
298 system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
299 system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
300 system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
301 system.membus.trans_dist::ReadExReq 116726 # Transaction distribution
302 system.membus.trans_dist::ReadExResp 116726 # Transaction distribution
303 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
304 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes)
305 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes)
306 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
307 system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
308 system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes)
309 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
310 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes)
311 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes)
312 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
313 system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
314 system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes)
315 system.membus.snoops 158 # Total snoops (count)
316 system.membus.snoop_fanout::samples 518029 # Request fanout histogram
317 system.membus.snoop_fanout::mean 1 # Request fanout histogram
318 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
319 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
320 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
321 system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram
322 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
323 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
324 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
325 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
326 system.membus.snoop_fanout::total 518029 # Request fanout histogram
327 system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks)
328 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
329 system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks)
330 system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
331 system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks)
332 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
333 system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks)
334 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
335 system.iocache.tags.replacements 41685 # number of replacements
336 system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use
337 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
338 system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
339 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
340 system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit.
341 system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor
342 system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy
343 system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy
344 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
345 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
346 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
347 system.iocache.tags.tag_accesses 375557 # Number of tag accesses
348 system.iocache.tags.data_accesses 375557 # Number of data accesses
349 system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
350 system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
351 system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
352 system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
353 system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses
354 system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses
355 system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
356 system.iocache.demand_misses::total 173 # number of demand (read+write) misses
357 system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
358 system.iocache.overall_misses::total 173 # number of overall misses
359 system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles
360 system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles
361 system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles
362 system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles
363 system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles
364 system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles
365 system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
366 system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
367 system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses)
368 system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses)
369 system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
370 system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
371 system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
372 system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
373 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
374 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
375 system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses
376 system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses
377 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
378 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
379 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
380 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
381 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency
382 system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency
383 system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
384 system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency
385 system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
386 system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency
387 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
388 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
389 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
390 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
391 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
392 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
393 system.iocache.fast_writes 41552 # number of fast writes performed
394 system.iocache.cache_copies 0 # number of cache copies performed
395 system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
396 system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
397 system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
398 system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
399 system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
400 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
401 system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
402 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
403 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles
404 system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles
405 system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles
406 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles
407 system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles
408 system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles
409 system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles
410 system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles
411 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
412 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
413 system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses
414 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses
415 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
416 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
417 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
418 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
419 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency
420 system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency
421 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency
422 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency
423 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
424 system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
425 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
426 system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
427 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
428 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
429 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
430 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
431 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
432 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
433 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
434 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
435 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
436 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
437 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
438 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
439 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
440 system.cpu_clk_domain.clock 500 # Clock period in ticks
441 system.cpu.dtb.fetch_hits 0 # ITB hits
442 system.cpu.dtb.fetch_misses 0 # ITB misses
443 system.cpu.dtb.fetch_acv 0 # ITB acv
444 system.cpu.dtb.fetch_accesses 0 # ITB accesses
445 system.cpu.dtb.read_hits 9052455 # DTB read hits
446 system.cpu.dtb.read_misses 10357 # DTB read misses
447 system.cpu.dtb.read_acv 210 # DTB read access violations
448 system.cpu.dtb.read_accesses 728916 # DTB read accesses
449 system.cpu.dtb.write_hits 6349129 # DTB write hits
450 system.cpu.dtb.write_misses 1143 # DTB write misses
451 system.cpu.dtb.write_acv 157 # DTB write access violations
452 system.cpu.dtb.write_accesses 291932 # DTB write accesses
453 system.cpu.dtb.data_hits 15401584 # DTB hits
454 system.cpu.dtb.data_misses 11500 # DTB misses
455 system.cpu.dtb.data_acv 367 # DTB access violations
456 system.cpu.dtb.data_accesses 1020848 # DTB accesses
457 system.cpu.itb.fetch_hits 4974880 # ITB hits
458 system.cpu.itb.fetch_misses 5010 # ITB misses
459 system.cpu.itb.fetch_acv 184 # ITB acv
460 system.cpu.itb.fetch_accesses 4979890 # ITB accesses
461 system.cpu.itb.read_hits 0 # DTB read hits
462 system.cpu.itb.read_misses 0 # DTB read misses
463 system.cpu.itb.read_acv 0 # DTB read access violations
464 system.cpu.itb.read_accesses 0 # DTB read accesses
465 system.cpu.itb.write_hits 0 # DTB write hits
466 system.cpu.itb.write_misses 0 # DTB write misses
467 system.cpu.itb.write_acv 0 # DTB write access violations
468 system.cpu.itb.write_accesses 0 # DTB write accesses
469 system.cpu.itb.data_hits 0 # DTB hits
470 system.cpu.itb.data_misses 0 # DTB misses
471 system.cpu.itb.data_acv 0 # DTB access violations
472 system.cpu.itb.data_accesses 0 # DTB accesses
473 system.cpu.numCycles 3838878050 # number of cpu cycles simulated
474 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
475 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
476 system.cpu.committedInsts 56102180 # Number of instructions committed
477 system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed
478 system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses
479 system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
480 system.cpu.num_func_calls 1481232 # number of times a function call or return occured
481 system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls
482 system.cpu.num_int_insts 51977296 # number of integer instructions
483 system.cpu.num_fp_insts 324326 # number of float instructions
484 system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read
485 system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written
486 system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
487 system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
488 system.cpu.num_mem_refs 15454224 # number of memory refs
489 system.cpu.num_load_insts 9089337 # Number of load instructions
490 system.cpu.num_store_insts 6364887 # Number of store instructions
491 system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles
492 system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles
493 system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles
494 system.cpu.idle_fraction 0.934448 # Percentage of idle cycles
495 system.cpu.Branches 8412776 # Number of branches fetched
496 system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction
497 system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction
498 system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction
499 system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
500 system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction
501 system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
502 system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
503 system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
504 system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction
505 system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction
506 system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction
507 system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction
508 system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction
509 system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction
510 system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction
511 system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction
512 system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction
513 system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction
514 system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction
515 system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction
516 system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction
517 system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction
518 system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction
519 system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction
520 system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction
521 system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction
522 system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction
523 system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
524 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
525 system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
526 system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction
527 system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction
528 system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction
529 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
530 system.cpu.op_class::total 56114047 # Class of executed instruction
531 system.cpu.kern.inst.arm 0 # number of arm instructions executed
532 system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
533 system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed
534 system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
535 system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
536 system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
537 system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl
538 system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl
539 system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
540 system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
541 system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
542 system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
543 system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl
544 system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl
545 system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl
546 system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl
547 system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl
548 system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl
549 system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
550 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
551 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
552 system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl
553 system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl
554 system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
555 system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
556 system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
557 system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
558 system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
559 system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
560 system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
561 system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
562 system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
563 system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
564 system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
565 system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
566 system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
567 system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
568 system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
569 system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
570 system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
571 system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
572 system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
573 system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
574 system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
575 system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
576 system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
577 system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
578 system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
579 system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
580 system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
581 system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
582 system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
583 system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
584 system.cpu.kern.syscall::total 326 # number of syscalls executed
585 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
586 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
587 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
588 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
589 system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
590 system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
591 system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
592 system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed
593 system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
594 system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
595 system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
596 system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
597 system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
598 system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
599 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
600 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
601 system.cpu.kern.callpal::total 192892 # number of callpals executed
602 system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
603 system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
604 system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
605 system.cpu.kern.mode_good::kernel 1911
606 system.cpu.kern.mode_good::user 1742
607 system.cpu.kern.mode_good::idle 169
608 system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches
609 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
610 system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
611 system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches
612 system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode
613 system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode
614 system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode
615 system.cpu.kern.swap_context 4176 # number of times the context was actually changed
616 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
617 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
618 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
619 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
620 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
621 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
622 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
623 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
624 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
625 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
626 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
627 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
628 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
629 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
630 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
631 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
632 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
633 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
634 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
635 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
636 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
637 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
638 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
639 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
640 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
641 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
642 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
643 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
644 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
645 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
646 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
647 system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
648 system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
649 system.iobus.trans_dist::WriteReq 51197 # Transaction distribution
650 system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
651 system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution
652 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
653 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
654 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
655 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
656 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
657 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
658 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
659 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
660 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
661 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
662 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
663 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
664 system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
665 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
666 system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
667 system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
668 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
669 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
670 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
671 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
672 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
673 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
674 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
675 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
676 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
677 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
678 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
679 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
680 system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
681 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
682 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
683 system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
684 system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
685 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
686 system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
687 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
688 system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
689 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
690 system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
691 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
692 system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
693 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
694 system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
695 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
696 system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
697 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
698 system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
699 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
700 system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
701 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
702 system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
703 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
704 system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
705 system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
706 system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks)
707 system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
708 system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
709 system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
710 system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks)
711 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
712 system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks)
713 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
714 system.cpu.icache.tags.replacements 927651 # number of replacements
715 system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use
716 system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks.
717 system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks.
718 system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks.
719 system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit.
720 system.cpu.icache.tags.occ_blocks::cpu.inst 508.304035 # Average occupied blocks per requestor
721 system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy
722 system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy
723 system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
724 system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
725 system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
726 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
727 system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
728 system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
729 system.cpu.icache.tags.tag_accesses 57042370 # Number of tag accesses
730 system.cpu.icache.tags.data_accesses 57042370 # Number of data accesses
731 system.cpu.icache.ReadReq_hits::cpu.inst 55185726 # number of ReadReq hits
732 system.cpu.icache.ReadReq_hits::total 55185726 # number of ReadReq hits
733 system.cpu.icache.demand_hits::cpu.inst 55185726 # number of demand (read+write) hits
734 system.cpu.icache.demand_hits::total 55185726 # number of demand (read+write) hits
735 system.cpu.icache.overall_hits::cpu.inst 55185726 # number of overall hits
736 system.cpu.icache.overall_hits::total 55185726 # number of overall hits
737 system.cpu.icache.ReadReq_misses::cpu.inst 928322 # number of ReadReq misses
738 system.cpu.icache.ReadReq_misses::total 928322 # number of ReadReq misses
739 system.cpu.icache.demand_misses::cpu.inst 928322 # number of demand (read+write) misses
740 system.cpu.icache.demand_misses::total 928322 # number of demand (read+write) misses
741 system.cpu.icache.overall_misses::cpu.inst 928322 # number of overall misses
742 system.cpu.icache.overall_misses::total 928322 # number of overall misses
743 system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909129000 # number of ReadReq miss cycles
744 system.cpu.icache.ReadReq_miss_latency::total 12909129000 # number of ReadReq miss cycles
745 system.cpu.icache.demand_miss_latency::cpu.inst 12909129000 # number of demand (read+write) miss cycles
746 system.cpu.icache.demand_miss_latency::total 12909129000 # number of demand (read+write) miss cycles
747 system.cpu.icache.overall_miss_latency::cpu.inst 12909129000 # number of overall miss cycles
748 system.cpu.icache.overall_miss_latency::total 12909129000 # number of overall miss cycles
749 system.cpu.icache.ReadReq_accesses::cpu.inst 56114048 # number of ReadReq accesses(hits+misses)
750 system.cpu.icache.ReadReq_accesses::total 56114048 # number of ReadReq accesses(hits+misses)
751 system.cpu.icache.demand_accesses::cpu.inst 56114048 # number of demand (read+write) accesses
752 system.cpu.icache.demand_accesses::total 56114048 # number of demand (read+write) accesses
753 system.cpu.icache.overall_accesses::cpu.inst 56114048 # number of overall (read+write) accesses
754 system.cpu.icache.overall_accesses::total 56114048 # number of overall (read+write) accesses
755 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses
756 system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses
757 system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses
758 system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses
759 system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses
760 system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses
761 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13905.874255 # average ReadReq miss latency
762 system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255 # average ReadReq miss latency
763 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency
764 system.cpu.icache.demand_avg_miss_latency::total 13905.874255 # average overall miss latency
765 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency
766 system.cpu.icache.overall_avg_miss_latency::total 13905.874255 # average overall miss latency
767 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
768 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
769 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
770 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
771 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
772 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
773 system.cpu.icache.fast_writes 0 # number of fast writes performed
774 system.cpu.icache.cache_copies 0 # number of cache copies performed
775 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928322 # number of ReadReq MSHR misses
776 system.cpu.icache.ReadReq_mshr_misses::total 928322 # number of ReadReq MSHR misses
777 system.cpu.icache.demand_mshr_misses::cpu.inst 928322 # number of demand (read+write) MSHR misses
778 system.cpu.icache.demand_mshr_misses::total 928322 # number of demand (read+write) MSHR misses
779 system.cpu.icache.overall_mshr_misses::cpu.inst 928322 # number of overall MSHR misses
780 system.cpu.icache.overall_mshr_misses::total 928322 # number of overall MSHR misses
781 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11047351000 # number of ReadReq MSHR miss cycles
782 system.cpu.icache.ReadReq_mshr_miss_latency::total 11047351000 # number of ReadReq MSHR miss cycles
783 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11047351000 # number of demand (read+write) MSHR miss cycles
784 system.cpu.icache.demand_mshr_miss_latency::total 11047351000 # number of demand (read+write) MSHR miss cycles
785 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11047351000 # number of overall MSHR miss cycles
786 system.cpu.icache.overall_mshr_miss_latency::total 11047351000 # number of overall MSHR miss cycles
787 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses
788 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses
789 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses
790 system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses
791 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses
792 system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses
793 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.343846 # average ReadReq mshr miss latency
794 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.343846 # average ReadReq mshr miss latency
795 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency
796 system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency
797 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency
798 system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency
799 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
800 system.cpu.l2cache.tags.replacements 336238 # number of replacements
801 system.cpu.l2cache.tags.tagsinuse 65296.035696 # Cycle average of tags in use
802 system.cpu.l2cache.tags.total_refs 2445623 # Total number of references to valid blocks.
803 system.cpu.l2cache.tags.sampled_refs 401399 # Sample count of references to valid blocks.
804 system.cpu.l2cache.tags.avg_refs 6.092748 # Average number of references to valid blocks.
805 system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit.
806 system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042 # Average occupied blocks per requestor
807 system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.074149 # Average occupied blocks per requestor
808 system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.861505 # Average occupied blocks per requestor
809 system.cpu.l2cache.tags.occ_percent::writebacks 0.847688 # Average percentage of cache occupancy
810 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy
811 system.cpu.l2cache.tags.occ_percent::cpu.data 0.075910 # Average percentage of cache occupancy
812 system.cpu.l2cache.tags.occ_percent::total 0.996338 # Average percentage of cache occupancy
813 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id
814 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
815 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id
816 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id
817 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3263 # Occupied blocks per task id
818 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55775 # Occupied blocks per task id
819 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id
820 system.cpu.l2cache.tags.tag_accesses 25932255 # Number of tag accesses
821 system.cpu.l2cache.tags.data_accesses 25932255 # Number of data accesses
822 system.cpu.l2cache.ReadReq_hits::cpu.inst 915008 # number of ReadReq hits
823 system.cpu.l2cache.ReadReq_hits::cpu.data 814389 # number of ReadReq hits
824 system.cpu.l2cache.ReadReq_hits::total 1729397 # number of ReadReq hits
825 system.cpu.l2cache.Writeback_hits::writebacks 834448 # number of Writeback hits
826 system.cpu.l2cache.Writeback_hits::total 834448 # number of Writeback hits
827 system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
828 system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
829 system.cpu.l2cache.ReadExReq_hits::cpu.data 187344 # number of ReadExReq hits
830 system.cpu.l2cache.ReadExReq_hits::total 187344 # number of ReadExReq hits
831 system.cpu.l2cache.demand_hits::cpu.inst 915008 # number of demand (read+write) hits
832 system.cpu.l2cache.demand_hits::cpu.data 1001733 # number of demand (read+write) hits
833 system.cpu.l2cache.demand_hits::total 1916741 # number of demand (read+write) hits
834 system.cpu.l2cache.overall_hits::cpu.inst 915008 # number of overall hits
835 system.cpu.l2cache.overall_hits::cpu.data 1001733 # number of overall hits
836 system.cpu.l2cache.overall_hits::total 1916741 # number of overall hits
837 system.cpu.l2cache.ReadReq_misses::cpu.inst 13294 # number of ReadReq misses
838 system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses
839 system.cpu.l2cache.ReadReq_misses::total 285254 # number of ReadReq misses
840 system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
841 system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
842 system.cpu.l2cache.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses
843 system.cpu.l2cache.ReadExReq_misses::total 116845 # number of ReadExReq misses
844 system.cpu.l2cache.demand_misses::cpu.inst 13294 # number of demand (read+write) misses
845 system.cpu.l2cache.demand_misses::cpu.data 388805 # number of demand (read+write) misses
846 system.cpu.l2cache.demand_misses::total 402099 # number of demand (read+write) misses
847 system.cpu.l2cache.overall_misses::cpu.inst 13294 # number of overall misses
848 system.cpu.l2cache.overall_misses::cpu.data 388805 # number of overall misses
849 system.cpu.l2cache.overall_misses::total 402099 # number of overall misses
850 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 968929000 # number of ReadReq miss cycles
851 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17693938000 # number of ReadReq miss cycles
852 system.cpu.l2cache.ReadReq_miss_latency::total 18662867000 # number of ReadReq miss cycles
853 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 93496 # number of UpgradeReq miss cycles
854 system.cpu.l2cache.UpgradeReq_miss_latency::total 93496 # number of UpgradeReq miss cycles
855 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8083085881 # number of ReadExReq miss cycles
856 system.cpu.l2cache.ReadExReq_miss_latency::total 8083085881 # number of ReadExReq miss cycles
857 system.cpu.l2cache.demand_miss_latency::cpu.inst 968929000 # number of demand (read+write) miss cycles
858 system.cpu.l2cache.demand_miss_latency::cpu.data 25777023881 # number of demand (read+write) miss cycles
859 system.cpu.l2cache.demand_miss_latency::total 26745952881 # number of demand (read+write) miss cycles
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861 system.cpu.l2cache.overall_miss_latency::cpu.data 25777023881 # number of overall miss cycles
862 system.cpu.l2cache.overall_miss_latency::total 26745952881 # number of overall miss cycles
863 system.cpu.l2cache.ReadReq_accesses::cpu.inst 928302 # number of ReadReq accesses(hits+misses)
864 system.cpu.l2cache.ReadReq_accesses::cpu.data 1086349 # number of ReadReq accesses(hits+misses)
865 system.cpu.l2cache.ReadReq_accesses::total 2014651 # number of ReadReq accesses(hits+misses)
866 system.cpu.l2cache.Writeback_accesses::writebacks 834448 # number of Writeback accesses(hits+misses)
867 system.cpu.l2cache.Writeback_accesses::total 834448 # number of Writeback accesses(hits+misses)
868 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
869 system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
870 system.cpu.l2cache.ReadExReq_accesses::cpu.data 304189 # number of ReadExReq accesses(hits+misses)
871 system.cpu.l2cache.ReadExReq_accesses::total 304189 # number of ReadExReq accesses(hits+misses)
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876 system.cpu.l2cache.overall_accesses::cpu.data 1390538 # number of overall (read+write) accesses
877 system.cpu.l2cache.overall_accesses::total 2318840 # number of overall (read+write) accesses
878 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014321 # miss rate for ReadReq accesses
879 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250343 # miss rate for ReadReq accesses
880 system.cpu.l2cache.ReadReq_miss_rate::total 0.141590 # miss rate for ReadReq accesses
881 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
882 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
883 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384120 # miss rate for ReadExReq accesses
884 system.cpu.l2cache.ReadExReq_miss_rate::total 0.384120 # miss rate for ReadExReq accesses
885 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014321 # miss rate for demand accesses
886 system.cpu.l2cache.demand_miss_rate::cpu.data 0.279608 # miss rate for demand accesses
887 system.cpu.l2cache.demand_miss_rate::total 0.173405 # miss rate for demand accesses
888 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014321 # miss rate for overall accesses
889 system.cpu.l2cache.overall_miss_rate::cpu.data 0.279608 # miss rate for overall accesses
890 system.cpu.l2cache.overall_miss_rate::total 0.173405 # miss rate for overall accesses
891 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72884.684820 # average ReadReq miss latency
892 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413 # average ReadReq miss latency
893 system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876 # average ReadReq miss latency
894 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7192 # average UpgradeReq miss latency
895 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7192 # average UpgradeReq miss latency
896 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69177.849981 # average ReadExReq miss latency
897 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69177.849981 # average ReadExReq miss latency
898 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency
899 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency
900 system.cpu.l2cache.demand_avg_miss_latency::total 66515.840330 # average overall miss latency
901 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency
902 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency
903 system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330 # average overall miss latency
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905 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
906 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
907 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
908 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
909 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
910 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
911 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
912 system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks
913 system.cpu.l2cache.writebacks::total 74180 # number of writebacks
914 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses
915 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses
916 system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses
917 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
918 system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
919 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses
920 system.cpu.l2cache.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses
921 system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # number of demand (read+write) MSHR misses
922 system.cpu.l2cache.demand_mshr_misses::cpu.data 388805 # number of demand (read+write) MSHR misses
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924 system.cpu.l2cache.overall_mshr_misses::cpu.inst 13294 # number of overall MSHR misses
925 system.cpu.l2cache.overall_mshr_misses::cpu.data 388805 # number of overall MSHR misses
926 system.cpu.l2cache.overall_mshr_misses::total 402099 # number of overall MSHR misses
927 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802368000 # number of ReadReq MSHR miss cycles
928 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14293948000 # number of ReadReq MSHR miss cycles
929 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15096316000 # number of ReadReq MSHR miss cycles
930 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 130013 # number of UpgradeReq MSHR miss cycles
931 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 130013 # number of UpgradeReq MSHR miss cycles
932 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6622079619 # number of ReadExReq MSHR miss cycles
933 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6622079619 # number of ReadExReq MSHR miss cycles
934 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802368000 # number of demand (read+write) MSHR miss cycles
935 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916027619 # number of demand (read+write) MSHR miss cycles
936 system.cpu.l2cache.demand_mshr_miss_latency::total 21718395619 # number of demand (read+write) MSHR miss cycles
937 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802368000 # number of overall MSHR miss cycles
938 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916027619 # number of overall MSHR miss cycles
939 system.cpu.l2cache.overall_mshr_miss_latency::total 21718395619 # number of overall MSHR miss cycles
940 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles
941 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles
942 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893390000 # number of WriteReq MSHR uncacheable cycles
943 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893390000 # number of WriteReq MSHR uncacheable cycles
944 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227573000 # number of overall MSHR uncacheable cycles
945 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227573000 # number of overall MSHR uncacheable cycles
946 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for ReadReq accesses
947 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250343 # mshr miss rate for ReadReq accesses
948 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141590 # mshr miss rate for ReadReq accesses
949 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
950 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
951 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384120 # mshr miss rate for ReadExReq accesses
952 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384120 # mshr miss rate for ReadExReq accesses
953 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for demand accesses
954 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for demand accesses
955 system.cpu.l2cache.demand_mshr_miss_rate::total 0.173405 # mshr miss rate for demand accesses
956 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for overall accesses
957 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for overall accesses
958 system.cpu.l2cache.overall_mshr_miss_rate::total 0.173405 # mshr miss rate for overall accesses
959 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165 # average ReadReq mshr miss latency
960 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678 # average ReadReq mshr miss latency
961 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928 # average ReadReq mshr miss latency
962 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
963 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
964 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112 # average ReadExReq mshr miss latency
965 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency
966 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
967 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
968 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
969 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
970 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
971 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
972 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
973 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
974 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
975 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
976 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
977 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
978 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
979 system.cpu.dcache.tags.replacements 1390025 # number of replacements
980 system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use
981 system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks.
982 system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks.
983 system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks.
984 system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
985 system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor
986 system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
987 system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
988 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
989 system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
990 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
991 system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
992 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
993 system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses
994 system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses
995 system.cpu.dcache.ReadReq_hits::cpu.data 7802461 # number of ReadReq hits
996 system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits
997 system.cpu.dcache.WriteReq_hits::cpu.data 5845351 # number of WriteReq hits
998 system.cpu.dcache.WriteReq_hits::total 5845351 # number of WriteReq hits
999 system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits
1000 system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits
1001 system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits
1002 system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits
1003 system.cpu.dcache.demand_hits::cpu.data 13647812 # number of demand (read+write) hits
1004 system.cpu.dcache.demand_hits::total 13647812 # number of demand (read+write) hits
1005 system.cpu.dcache.overall_hits::cpu.data 13647812 # number of overall hits
1006 system.cpu.dcache.overall_hits::total 13647812 # number of overall hits
1007 system.cpu.dcache.ReadReq_misses::cpu.data 1069134 # number of ReadReq misses
1008 system.cpu.dcache.ReadReq_misses::total 1069134 # number of ReadReq misses
1009 system.cpu.dcache.WriteReq_misses::cpu.data 304206 # number of WriteReq misses
1010 system.cpu.dcache.WriteReq_misses::total 304206 # number of WriteReq misses
1011 system.cpu.dcache.LoadLockedReq_misses::cpu.data 17215 # number of LoadLockedReq misses
1012 system.cpu.dcache.LoadLockedReq_misses::total 17215 # number of LoadLockedReq misses
1013 system.cpu.dcache.demand_misses::cpu.data 1373340 # number of demand (read+write) misses
1014 system.cpu.dcache.demand_misses::total 1373340 # number of demand (read+write) misses
1015 system.cpu.dcache.overall_misses::cpu.data 1373340 # number of overall misses
1016 system.cpu.dcache.overall_misses::total 1373340 # number of overall misses
1017 system.cpu.dcache.ReadReq_miss_latency::cpu.data 28994287250 # number of ReadReq miss cycles
1018 system.cpu.dcache.ReadReq_miss_latency::total 28994287250 # number of ReadReq miss cycles
1019 system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922192632 # number of WriteReq miss cycles
1020 system.cpu.dcache.WriteReq_miss_latency::total 10922192632 # number of WriteReq miss cycles
1021 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228270750 # number of LoadLockedReq miss cycles
1022 system.cpu.dcache.LoadLockedReq_miss_latency::total 228270750 # number of LoadLockedReq miss cycles
1023 system.cpu.dcache.demand_miss_latency::cpu.data 39916479882 # number of demand (read+write) miss cycles
1024 system.cpu.dcache.demand_miss_latency::total 39916479882 # number of demand (read+write) miss cycles
1025 system.cpu.dcache.overall_miss_latency::cpu.data 39916479882 # number of overall miss cycles
1026 system.cpu.dcache.overall_miss_latency::total 39916479882 # number of overall miss cycles
1027 system.cpu.dcache.ReadReq_accesses::cpu.data 8871595 # number of ReadReq accesses(hits+misses)
1028 system.cpu.dcache.ReadReq_accesses::total 8871595 # number of ReadReq accesses(hits+misses)
1029 system.cpu.dcache.WriteReq_accesses::cpu.data 6149557 # number of WriteReq accesses(hits+misses)
1030 system.cpu.dcache.WriteReq_accesses::total 6149557 # number of WriteReq accesses(hits+misses)
1031 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses)
1032 system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses)
1033 system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses)
1034 system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses)
1035 system.cpu.dcache.demand_accesses::cpu.data 15021152 # number of demand (read+write) accesses
1036 system.cpu.dcache.demand_accesses::total 15021152 # number of demand (read+write) accesses
1037 system.cpu.dcache.overall_accesses::cpu.data 15021152 # number of overall (read+write) accesses
1038 system.cpu.dcache.overall_accesses::total 15021152 # number of overall (read+write) accesses
1039 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120512 # miss rate for ReadReq accesses
1040 system.cpu.dcache.ReadReq_miss_rate::total 0.120512 # miss rate for ReadReq accesses
1041 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
1042 system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
1043 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses
1044 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses
1045 system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses
1046 system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses
1047 system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses
1048 system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses
1049 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency
1050 system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency
1051 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency
1052 system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency
1053 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency
1054 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency
1055 system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
1056 system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency
1057 system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
1058 system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency
1059 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1060 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1061 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1062 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1063 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1064 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1065 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1066 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1067 system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks
1068 system.cpu.dcache.writebacks::total 834448 # number of writebacks
1069 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses
1070 system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses
1071 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses
1072 system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses
1073 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses
1074 system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses
1075 system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses
1076 system.cpu.dcache.demand_mshr_misses::total 1373340 # number of demand (read+write) MSHR misses
1077 system.cpu.dcache.overall_mshr_misses::cpu.data 1373340 # number of overall MSHR misses
1078 system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses
1079 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles
1080 system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles
1081 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles
1082 system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles
1083 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles
1084 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles
1085 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles
1086 system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles
1087 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles
1088 system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles
1089 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles
1090 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles
1091 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles
1092 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles
1093 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles
1094 system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles
1095 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses
1096 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses
1097 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses
1098 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses
1099 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses
1100 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses
1101 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses
1102 system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses
1103 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses
1104 system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses
1105 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency
1106 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency
1107 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency
1108 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency
1109 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency
1110 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency
1111 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
1112 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
1113 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
1114 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
1115 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1116 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1117 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1118 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1119 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1120 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1121 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1122 system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution
1123 system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution
1124 system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
1125 system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
1126 system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution
1127 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution
1128 system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
1129 system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
1130 system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution
1131 system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution
1132 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes)
1133 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes)
1134 system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes)
1135 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes)
1136 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes)
1137 system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes)
1138 system.cpu.toL2Bus.snoops 41913 # Total snoops (count)
1139 system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram
1140 system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram
1141 system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram
1142 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1143 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1144 system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram
1145 system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram
1146 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1147 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1148 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1149 system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram
1150 system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks)
1151 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1152 system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
1153 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1154 system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks)
1155 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1156 system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks)
1157 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1159 ---------- End Simulation Statistics ----------
projects / gem5.git / blob