8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
14 boot_cpu_frequency=500
15 boot_osflags=root=/dev/hda1 console=ttyS0
17 clk_domain=system.clk_domain
18 console=/dist/m5/system/binaries/console
20 exit_on_work_items=false
22 kernel=/dist/m5/system/binaries/vmlinux
23 kernel_addr_check=true
24 load_addr_mask=1099511627775
27 mem_ranges=0:134217727
28 memories=system.physmem
29 mmap_using_noreserve=false
32 pal=/dist/m5/system/binaries/ts_osfpal
33 readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
37 work_begin_ckpt_count=0
38 work_begin_cpu_id_exit=-1
39 work_begin_exit_count=0
40 work_cpus_ckpt_count=0
44 system_port=system.membus.slave[0]
48 clk_domain=system.clk_domain
51 ranges=8796093022208:18446744073709551615
54 master=system.iobus.slave[0]
55 slave=system.membus.master[0]
63 voltage_domain=system.voltage_domain
67 children=dcache dtb icache interrupts isa itb tracer
70 clk_domain=system.cpu_clk_domain
72 do_checkpoint_insts=true
74 do_statistics_insts=true
78 function_trace_start=0
79 interrupts=system.cpu0.interrupts
82 max_insts_all_threads=0
83 max_insts_any_thread=0
84 max_loads_all_threads=0
85 max_loads_any_thread=0
93 tracer=system.cpu0.tracer
95 dcache_port=system.cpu0.dcache.cpu_side
96 icache_port=system.cpu0.icache.cpu_side
101 addr_ranges=0:18446744073709551615
103 clk_domain=system.cpu_clk_domain
104 clusivity=mostly_incl
105 demand_mshr_reserve=1
112 prefetch_on_access=false
115 sequential_access=false
118 tags=system.cpu0.dcache.tags
121 writeback_clean=false
122 cpu_side=system.cpu0.dcache_port
123 mem_side=system.toL2Bus.slave[1]
125 [system.cpu0.dcache.tags]
129 clk_domain=system.cpu_clk_domain
132 sequential_access=false
143 addr_ranges=0:18446744073709551615
145 clk_domain=system.cpu_clk_domain
146 clusivity=mostly_incl
147 demand_mshr_reserve=1
154 prefetch_on_access=false
157 sequential_access=false
160 tags=system.cpu0.icache.tags
164 cpu_side=system.cpu0.icache_port
165 mem_side=system.toL2Bus.slave[0]
167 [system.cpu0.icache.tags]
171 clk_domain=system.cpu_clk_domain
174 sequential_access=false
177 [system.cpu0.interrupts]
197 children=dcache dtb icache interrupts isa itb tracer
200 clk_domain=system.cpu_clk_domain
202 do_checkpoint_insts=true
204 do_statistics_insts=true
208 function_trace_start=0
209 interrupts=system.cpu1.interrupts
212 max_insts_all_threads=0
213 max_insts_any_thread=0
214 max_loads_all_threads=0
215 max_loads_any_thread=0
219 simpoint_start_insts=
223 tracer=system.cpu1.tracer
225 dcache_port=system.cpu1.dcache.cpu_side
226 icache_port=system.cpu1.icache.cpu_side
231 addr_ranges=0:18446744073709551615
233 clk_domain=system.cpu_clk_domain
234 clusivity=mostly_incl
235 demand_mshr_reserve=1
242 prefetch_on_access=false
245 sequential_access=false
248 tags=system.cpu1.dcache.tags
251 writeback_clean=false
252 cpu_side=system.cpu1.dcache_port
253 mem_side=system.toL2Bus.slave[3]
255 [system.cpu1.dcache.tags]
259 clk_domain=system.cpu_clk_domain
262 sequential_access=false
273 addr_ranges=0:18446744073709551615
275 clk_domain=system.cpu_clk_domain
276 clusivity=mostly_incl
277 demand_mshr_reserve=1
284 prefetch_on_access=false
287 sequential_access=false
290 tags=system.cpu1.icache.tags
294 cpu_side=system.cpu1.icache_port
295 mem_side=system.toL2Bus.slave[2]
297 [system.cpu1.icache.tags]
301 clk_domain=system.cpu_clk_domain
304 sequential_access=false
307 [system.cpu1.interrupts]
325 [system.cpu_clk_domain]
331 voltage_domain=system.voltage_domain
339 image=system.disk0.image
344 child=system.disk0.image.child
350 [system.disk0.image.child]
353 image_file=/dist/m5/system/disks/linux-latest.img
362 image=system.disk2.image
367 child=system.disk2.image.child
373 [system.disk2.image.child]
376 image_file=/dist/m5/system/disks/linux-bigswap2.img
379 [system.dvfs_handler]
384 sys_clk_domain=system.clk_domain
385 transition_latency=100000000
394 clk_domain=system.clk_domain
399 use_default_range=false
401 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
402 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
407 addr_ranges=0:134217727
409 clk_domain=system.clk_domain
410 clusivity=mostly_incl
411 demand_mshr_reserve=1
418 prefetch_on_access=false
421 sequential_access=false
424 tags=system.iocache.tags
427 writeback_clean=false
428 cpu_side=system.iobus.master[27]
429 mem_side=system.membus.slave[2]
431 [system.iocache.tags]
435 clk_domain=system.clk_domain
438 sequential_access=false
444 addr_ranges=0:18446744073709551615
446 clk_domain=system.cpu_clk_domain
447 clusivity=mostly_incl
448 demand_mshr_reserve=1
455 prefetch_on_access=false
458 sequential_access=false
464 writeback_clean=false
465 cpu_side=system.toL2Bus.master[0]
466 mem_side=system.membus.slave[1]
472 clk_domain=system.cpu_clk_domain
475 sequential_access=false
480 children=badaddr_responder
481 clk_domain=system.clk_domain
487 snoop_response_latency=4
489 use_default_range=false
491 default=system.membus.badaddr_responder.pio
492 master=system.bridge.slave system.physmem.port
493 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
495 [system.membus.badaddr_responder]
497 clk_domain=system.clk_domain
505 ret_data32=4294967295
506 ret_data64=18446744073709551615
511 pio=system.membus.default
540 addr_mapping=RoRaBaCoCh
541 bank_groups_per_rank=0
545 clk_domain=system.clk_domain
546 conf_table_reported=true
548 device_rowbuffer_size=1024
549 device_size=536870912
554 max_accesses_per_row=16
555 mem_sched_policy=frfcfs
556 min_writes_per_switch=16
558 page_policy=open_adaptive
562 static_backend_latency=10000
563 static_frontend_latency=10000
586 write_high_thresh_perc=85
587 write_low_thresh_perc=50
588 port=system.membus.master[1]
593 disk=system.simple_disk.disk
597 [system.simple_disk.disk]
600 image_file=/dist/m5/system/disks/linux-latest.img
606 intr_control=system.intrctrl
613 children=snoop_filter
614 clk_domain=system.cpu_clk_domain
619 snoop_filter=system.toL2Bus.snoop_filter
620 snoop_response_latency=1
622 use_default_range=false
624 master=system.l2c.cpu_side
625 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
627 [system.toL2Bus.snoop_filter]
636 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
638 intrctrl=system.intrctrl
641 [system.tsunami.backdoor]
643 clk_domain=system.clk_domain
645 disk=system.simple_disk
647 pio_addr=8804682956800
649 platform=system.tsunami
651 terminal=system.terminal
652 pio=system.iobus.master[24]
654 [system.tsunami.cchip]
656 clk_domain=system.clk_domain
658 pio_addr=8803072344064
661 tsunami=system.tsunami
662 pio=system.iobus.master[0]
664 [system.tsunami.ethernet]
704 MSICAPNextCapability=0
708 MSIXCAPNextCapability=0
718 PMCAPNextCapability=0
723 PXCAPDevCapabilities=0
730 PXCAPNextCapability=0
738 clk_domain=system.clk_domain
748 hardware_address=00:90:00:00:00:01
749 host=system.tsunami.pchip
764 dma=system.iobus.slave[2]
765 pio=system.iobus.master[26]
767 [system.tsunami.fake_OROM]
769 clk_domain=system.clk_domain
772 pio_addr=8796093677568
777 ret_data32=4294967295
778 ret_data64=18446744073709551615
783 pio=system.iobus.master[8]
785 [system.tsunami.fake_ata0]
787 clk_domain=system.clk_domain
790 pio_addr=8804615848432
795 ret_data32=4294967295
796 ret_data64=18446744073709551615
801 pio=system.iobus.master[19]
803 [system.tsunami.fake_ata1]
805 clk_domain=system.clk_domain
808 pio_addr=8804615848304
813 ret_data32=4294967295
814 ret_data64=18446744073709551615
819 pio=system.iobus.master[20]
821 [system.tsunami.fake_pnp_addr]
823 clk_domain=system.clk_domain
826 pio_addr=8804615848569
831 ret_data32=4294967295
832 ret_data64=18446744073709551615
837 pio=system.iobus.master[9]
839 [system.tsunami.fake_pnp_read0]
841 clk_domain=system.clk_domain
844 pio_addr=8804615848451
849 ret_data32=4294967295
850 ret_data64=18446744073709551615
855 pio=system.iobus.master[11]
857 [system.tsunami.fake_pnp_read1]
859 clk_domain=system.clk_domain
862 pio_addr=8804615848515
867 ret_data32=4294967295
868 ret_data64=18446744073709551615
873 pio=system.iobus.master[12]
875 [system.tsunami.fake_pnp_read2]
877 clk_domain=system.clk_domain
880 pio_addr=8804615848579
885 ret_data32=4294967295
886 ret_data64=18446744073709551615
891 pio=system.iobus.master[13]
893 [system.tsunami.fake_pnp_read3]
895 clk_domain=system.clk_domain
898 pio_addr=8804615848643
903 ret_data32=4294967295
904 ret_data64=18446744073709551615
909 pio=system.iobus.master[14]
911 [system.tsunami.fake_pnp_read4]
913 clk_domain=system.clk_domain
916 pio_addr=8804615848707
921 ret_data32=4294967295
922 ret_data64=18446744073709551615
927 pio=system.iobus.master[15]
929 [system.tsunami.fake_pnp_read5]
931 clk_domain=system.clk_domain
934 pio_addr=8804615848771
939 ret_data32=4294967295
940 ret_data64=18446744073709551615
945 pio=system.iobus.master[16]
947 [system.tsunami.fake_pnp_read6]
949 clk_domain=system.clk_domain
952 pio_addr=8804615848835
957 ret_data32=4294967295
958 ret_data64=18446744073709551615
963 pio=system.iobus.master[17]
965 [system.tsunami.fake_pnp_read7]
967 clk_domain=system.clk_domain
970 pio_addr=8804615848899
975 ret_data32=4294967295
976 ret_data64=18446744073709551615
981 pio=system.iobus.master[18]
983 [system.tsunami.fake_pnp_write]
985 clk_domain=system.clk_domain
988 pio_addr=8804615850617
993 ret_data32=4294967295
994 ret_data64=18446744073709551615
999 pio=system.iobus.master[10]
1001 [system.tsunami.fake_ppc]
1003 clk_domain=system.clk_domain
1006 pio_addr=8804615848891
1011 ret_data32=4294967295
1012 ret_data64=18446744073709551615
1017 pio=system.iobus.master[7]
1019 [system.tsunami.fake_sm_chip]
1021 clk_domain=system.clk_domain
1024 pio_addr=8804615848816
1029 ret_data32=4294967295
1030 ret_data64=18446744073709551615
1035 pio=system.iobus.master[2]
1037 [system.tsunami.fake_uart1]
1039 clk_domain=system.clk_domain
1042 pio_addr=8804615848696
1047 ret_data32=4294967295
1048 ret_data64=18446744073709551615
1053 pio=system.iobus.master[3]
1055 [system.tsunami.fake_uart2]
1057 clk_domain=system.clk_domain
1060 pio_addr=8804615848936
1065 ret_data32=4294967295
1066 ret_data64=18446744073709551615
1071 pio=system.iobus.master[4]
1073 [system.tsunami.fake_uart3]
1075 clk_domain=system.clk_domain
1078 pio_addr=8804615848680
1083 ret_data32=4294967295
1084 ret_data64=18446744073709551615
1089 pio=system.iobus.master[5]
1091 [system.tsunami.fake_uart4]
1093 clk_domain=system.clk_domain
1096 pio_addr=8804615848944
1101 ret_data32=4294967295
1102 ret_data64=18446744073709551615
1107 pio=system.iobus.master[6]
1111 clk_domain=system.clk_domain
1112 devicename=FrameBuffer
1114 pio_addr=8804615848912
1117 pio=system.iobus.master[21]
1119 [system.tsunami.ide]
1158 MSICAPMsgUpperAddr=0
1159 MSICAPNextCapability=0
1163 MSIXCAPNextCapability=0
1173 PMCAPNextCapability=0
1178 PXCAPDevCapabilities=0
1185 PXCAPNextCapability=0
1193 clk_domain=system.clk_domain
1194 config_latency=20000
1196 disks=system.disk0 system.disk2
1198 host=system.tsunami.pchip
1205 dma=system.iobus.slave[1]
1206 pio=system.iobus.master[25]
1210 clk_domain=system.clk_domain
1213 pio_addr=8804615847936
1216 time=Thu Jan 1 00:00:00 2009
1217 tsunami=system.tsunami
1219 pio=system.iobus.master[22]
1221 [system.tsunami.pchip]
1223 clk_domain=system.clk_domain
1224 conf_base=8804649402368
1229 pci_mem_base=8796093022208
1230 pci_pio_base=8804615847936
1231 pio_addr=8802535473152
1233 platform=system.tsunami
1235 tsunami=system.tsunami
1236 pio=system.iobus.master[1]
1238 [system.tsunami.uart]
1240 clk_domain=system.clk_domain
1242 pio_addr=8804615848952
1244 platform=system.tsunami
1246 terminal=system.terminal
1247 pio=system.iobus.master[23]
1249 [system.voltage_domain]