2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.966742 # Number of seconds simulated
4 sim_ticks 1966742176000 # Number of ticks simulated
5 final_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1742915 # Simulator instruction rate (inst/s)
8 host_op_rate 1742915 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 56229643103 # Simulator tick rate (ticks/s)
10 host_mem_usage 335876 # Number of bytes of host memory used
11 host_seconds 34.98 # Real time elapsed on the host
12 sim_insts 60961842 # Number of instructions simulated
13 sim_ops 60961842 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory
21 system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 26119552 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory
26 system.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory
27 system.physmem.bytes_written::total 7774400 # Number of bytes written to this memory
28 system.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory
32 system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
33 system.physmem.num_reads::total 408118 # Number of read requests responded to by this memory
34 system.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 121475 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.readReqs 408118 # Number of read requests accepted
55 system.physmem.writeReqs 121475 # Number of write requests accepted
56 system.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue
57 system.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue
58 system.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM
59 system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue
60 system.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM
61 system.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side
62 system.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side
63 system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue
64 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
65 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
66 system.physmem.perBankRdBursts::0 25299 # Per bank write bursts
67 system.physmem.perBankRdBursts::1 25599 # Per bank write bursts
68 system.physmem.perBankRdBursts::2 25910 # Per bank write bursts
69 system.physmem.perBankRdBursts::3 25657 # Per bank write bursts
70 system.physmem.perBankRdBursts::4 25586 # Per bank write bursts
71 system.physmem.perBankRdBursts::5 25177 # Per bank write bursts
72 system.physmem.perBankRdBursts::6 26012 # Per bank write bursts
73 system.physmem.perBankRdBursts::7 25110 # Per bank write bursts
74 system.physmem.perBankRdBursts::8 25002 # Per bank write bursts
75 system.physmem.perBankRdBursts::9 25326 # Per bank write bursts
76 system.physmem.perBankRdBursts::10 25349 # Per bank write bursts
77 system.physmem.perBankRdBursts::11 25350 # Per bank write bursts
78 system.physmem.perBankRdBursts::12 25737 # Per bank write bursts
79 system.physmem.perBankRdBursts::13 25386 # Per bank write bursts
80 system.physmem.perBankRdBursts::14 25673 # Per bank write bursts
81 system.physmem.perBankRdBursts::15 25833 # Per bank write bursts
82 system.physmem.perBankWrBursts::0 7888 # Per bank write bursts
83 system.physmem.perBankWrBursts::1 7973 # Per bank write bursts
84 system.physmem.perBankWrBursts::2 7891 # Per bank write bursts
85 system.physmem.perBankWrBursts::3 7697 # Per bank write bursts
86 system.physmem.perBankWrBursts::4 7528 # Per bank write bursts
87 system.physmem.perBankWrBursts::5 7375 # Per bank write bursts
88 system.physmem.perBankWrBursts::6 8079 # Per bank write bursts
89 system.physmem.perBankWrBursts::7 7030 # Per bank write bursts
90 system.physmem.perBankWrBursts::8 7056 # Per bank write bursts
91 system.physmem.perBankWrBursts::9 7058 # Per bank write bursts
92 system.physmem.perBankWrBursts::10 7244 # Per bank write bursts
93 system.physmem.perBankWrBursts::11 7671 # Per bank write bursts
94 system.physmem.perBankWrBursts::12 7657 # Per bank write bursts
95 system.physmem.perBankWrBursts::13 7545 # Per bank write bursts
96 system.physmem.perBankWrBursts::14 7813 # Per bank write bursts
97 system.physmem.perBankWrBursts::15 7943 # Per bank write bursts
98 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99 system.physmem.numWrRetry 71 # Number of times write queue was full causing retry
100 system.physmem.totGap 1966734882500 # Total gap between requests
101 system.physmem.readPktSize::0 0 # Read request sizes (log2)
102 system.physmem.readPktSize::1 0 # Read request sizes (log2)
103 system.physmem.readPktSize::2 0 # Read request sizes (log2)
104 system.physmem.readPktSize::3 0 # Read request sizes (log2)
105 system.physmem.readPktSize::4 0 # Read request sizes (log2)
106 system.physmem.readPktSize::5 0 # Read request sizes (log2)
107 system.physmem.readPktSize::6 408118 # Read request sizes (log2)
108 system.physmem.writePktSize::0 0 # Write request sizes (log2)
109 system.physmem.writePktSize::1 0 # Write request sizes (log2)
110 system.physmem.writePktSize::2 0 # Write request sizes (log2)
111 system.physmem.writePktSize::3 0 # Write request sizes (log2)
112 system.physmem.writePktSize::4 0 # Write request sizes (log2)
113 system.physmem.writePktSize::5 0 # Write request sizes (log2)
114 system.physmem.writePktSize::6 121475 # Write request sizes (log2)
115 system.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see
211 system.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation
225 system.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
231 system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
232 system.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes
233 system.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads
268 system.physmem.totQLat 6253232750 # Total ticks spent queuing
269 system.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM
270 system.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers
271 system.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst
272 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
273 system.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst
274 system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s
275 system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
276 system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s
277 system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
278 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
279 system.physmem.busUtil 0.13 # Data bus utilization in percentage
280 system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
281 system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
282 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
283 system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing
284 system.physmem.readRowHits 365871 # Number of row buffer hits during reads
285 system.physmem.writeRowHits 97586 # Number of row buffer hits during writes
286 system.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads
287 system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes
288 system.physmem.avgGap 3713672.35 # Average gap between requests
289 system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined
290 system.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ)
291 system.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ)
292 system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ)
293 system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ)
294 system.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ)
295 system.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ)
296 system.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ)
297 system.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ)
298 system.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ)
299 system.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ)
300 system.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ)
301 system.physmem_0.averagePower 250.241923 # Core power per rank (mW)
302 system.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank
303 system.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states
304 system.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states
305 system.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states
306 system.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states
307 system.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states
308 system.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states
309 system.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ)
310 system.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ)
311 system.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ)
312 system.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ)
313 system.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ)
314 system.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ)
315 system.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ)
316 system.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ)
317 system.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ)
318 system.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ)
319 system.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ)
320 system.physmem_1.averagePower 250.452256 # Core power per rank (mW)
321 system.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank
322 system.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states
323 system.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states
324 system.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states
325 system.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states
326 system.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states
327 system.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states
328 system.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
329 system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
330 system.cpu_clk_domain.clock 500 # Clock period in ticks
331 system.cpu0.dtb.fetch_hits 0 # ITB hits
332 system.cpu0.dtb.fetch_misses 0 # ITB misses
333 system.cpu0.dtb.fetch_acv 0 # ITB acv
334 system.cpu0.dtb.fetch_accesses 0 # ITB accesses
335 system.cpu0.dtb.read_hits 7479524 # DTB read hits
336 system.cpu0.dtb.read_misses 7764 # DTB read misses
337 system.cpu0.dtb.read_acv 210 # DTB read access violations
338 system.cpu0.dtb.read_accesses 524068 # DTB read accesses
339 system.cpu0.dtb.write_hits 5079926 # DTB write hits
340 system.cpu0.dtb.write_misses 909 # DTB write misses
341 system.cpu0.dtb.write_acv 133 # DTB write access violations
342 system.cpu0.dtb.write_accesses 202594 # DTB write accesses
343 system.cpu0.dtb.data_hits 12559450 # DTB hits
344 system.cpu0.dtb.data_misses 8673 # DTB misses
345 system.cpu0.dtb.data_acv 343 # DTB access violations
346 system.cpu0.dtb.data_accesses 726662 # DTB accesses
347 system.cpu0.itb.fetch_hits 3638587 # ITB hits
348 system.cpu0.itb.fetch_misses 3984 # ITB misses
349 system.cpu0.itb.fetch_acv 184 # ITB acv
350 system.cpu0.itb.fetch_accesses 3642571 # ITB accesses
351 system.cpu0.itb.read_hits 0 # DTB read hits
352 system.cpu0.itb.read_misses 0 # DTB read misses
353 system.cpu0.itb.read_acv 0 # DTB read access violations
354 system.cpu0.itb.read_accesses 0 # DTB read accesses
355 system.cpu0.itb.write_hits 0 # DTB write hits
356 system.cpu0.itb.write_misses 0 # DTB write misses
357 system.cpu0.itb.write_acv 0 # DTB write access violations
358 system.cpu0.itb.write_accesses 0 # DTB write accesses
359 system.cpu0.itb.data_hits 0 # DTB hits
360 system.cpu0.itb.data_misses 0 # DTB misses
361 system.cpu0.itb.data_acv 0 # DTB access violations
362 system.cpu0.itb.data_accesses 0 # DTB accesses
363 system.cpu0.numPwrStateTransitions 13586 # Number of power state transitions
364 system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state
365 system.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state
366 system.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state
367 system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state
368 system.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state
369 system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
370 system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state
371 system.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states
372 system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states
373 system.cpu0.numCycles 3933484352 # number of cpu cycles simulated
374 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
375 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
376 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
377 system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed
378 system.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed
379 system.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl
380 system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl
381 system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl
382 system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl
383 system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl
384 system.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl
385 system.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl
386 system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
387 system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl
388 system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl
389 system.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl
390 system.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl
391 system.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl
392 system.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl
393 system.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl
394 system.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl
395 system.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl
396 system.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl
397 system.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl
398 system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
399 system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
400 system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
401 system.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl
402 system.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl
403 system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
404 system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed
405 system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
406 system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
407 system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
408 system.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed
409 system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed
410 system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed
411 system.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed
412 system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed
413 system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed
414 system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed
415 system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed
416 system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed
417 system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed
418 system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed
419 system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
420 system.cpu0.kern.callpal::total 148123 # number of callpals executed
421 system.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches
422 system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches
423 system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
424 system.cpu0.kern.mode_good::kernel 1369
425 system.cpu0.kern.mode_good::user 1370
426 system.cpu0.kern.mode_good::idle 0
427 system.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches
428 system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
429 system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
430 system.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches
431 system.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode
432 system.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode
433 system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
434 system.cpu0.kern.swap_context 3064 # number of times the context was actually changed
435 system.cpu0.committedInsts 47693300 # Number of instructions committed
436 system.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed
437 system.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses
438 system.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses
439 system.cpu0.num_func_calls 1191022 # number of times a function call or return occured
440 system.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls
441 system.cpu0.num_int_insts 44245928 # number of integer instructions
442 system.cpu0.num_fp_insts 210005 # number of float instructions
443 system.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read
444 system.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written
445 system.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read
446 system.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written
447 system.cpu0.num_mem_refs 12600240 # number of memory refs
448 system.cpu0.num_load_insts 7507148 # Number of load instructions
449 system.cpu0.num_store_insts 5093092 # Number of store instructions
450 system.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles
451 system.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles
452 system.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles
453 system.cpu0.idle_fraction 0.940603 # Percentage of idle cycles
454 system.cpu0.Branches 7183589 # Number of branches fetched
455 system.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction
456 system.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction
457 system.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction
458 system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction
459 system.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction
460 system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction
461 system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction
462 system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction
463 system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction
464 system.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction
465 system.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction
466 system.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction
467 system.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction
468 system.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction
469 system.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction
470 system.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction
471 system.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction
472 system.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction
473 system.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction
474 system.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction
475 system.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction
476 system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction
477 system.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction
478 system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction
479 system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction
480 system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction
481 system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction
482 system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction
483 system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction
484 system.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction
485 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction
486 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction
487 system.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction
488 system.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction
489 system.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction
490 system.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction
491 system.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction
492 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
493 system.cpu0.op_class::total 47702316 # Class of executed instruction
494 system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
495 system.cpu0.dcache.tags.replacements 1183155 # number of replacements
496 system.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use
497 system.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks.
498 system.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks.
499 system.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks.
500 system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit.
501 system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor
502 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy
503 system.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy
504 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
505 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
506 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
507 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
508 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
509 system.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses
510 system.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses
511 system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
512 system.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits
513 system.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits
514 system.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits
515 system.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits
516 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits
517 system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits
518 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits
519 system.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits
520 system.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits
521 system.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits
522 system.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits
523 system.cpu0.dcache.overall_hits::total 11070637 # number of overall hits
524 system.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses
525 system.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses
526 system.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses
527 system.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses
528 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses
529 system.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses
530 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses
531 system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses
532 system.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses
533 system.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses
534 system.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses
535 system.cpu0.dcache.overall_misses::total 1193727 # number of overall misses
536 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles
537 system.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles
538 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles
539 system.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles
540 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles
541 system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles
542 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles
543 system.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles
544 system.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles
545 system.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles
546 system.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles
547 system.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles
548 system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses)
549 system.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses)
550 system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses)
551 system.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses)
552 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses)
553 system.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses)
554 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses)
555 system.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses)
556 system.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses
557 system.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses
558 system.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses
559 system.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses
560 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses
561 system.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses
562 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses
563 system.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses
564 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses
565 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses
566 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses
567 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses
568 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses
569 system.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses
570 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses
571 system.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses
572 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency
573 system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency
574 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency
575 system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency
576 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency
577 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency
578 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency
579 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency
580 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency
581 system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency
582 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency
583 system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency
584 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
585 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
586 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
587 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
588 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
589 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
590 system.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks
591 system.cpu0.dcache.writebacks::total 681263 # number of writebacks
592 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses
593 system.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses
594 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses
595 system.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses
596 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses
597 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses
598 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses
599 system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses
600 system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses
601 system.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses
602 system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses
603 system.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses
604 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable
605 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable
606 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable
607 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable
608 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses
609 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses
610 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles
611 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles
612 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles
613 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles
614 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles
615 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles
616 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles
617 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles
618 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles
619 system.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles
620 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles
621 system.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles
622 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles
623 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles
624 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles
625 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles
626 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses
627 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses
628 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses
629 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses
630 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses
631 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses
632 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses
633 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses
634 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses
635 system.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses
636 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses
637 system.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses
638 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency
639 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency
640 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency
641 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency
642 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency
643 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency
644 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency
645 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency
646 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency
647 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency
648 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency
649 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency
650 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency
651 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency
652 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency
653 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency
654 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
655 system.cpu0.icache.tags.replacements 692168 # number of replacements
656 system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use
657 system.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks.
658 system.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks.
659 system.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks.
660 system.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit.
661 system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor
662 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy
663 system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy
664 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
665 system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
666 system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
667 system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id
668 system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
669 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
670 system.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses
671 system.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses
672 system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
673 system.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits
674 system.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits
675 system.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits
676 system.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits
677 system.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits
678 system.cpu0.icache.overall_hits::total 47009511 # number of overall hits
679 system.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses
680 system.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses
681 system.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses
682 system.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses
683 system.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses
684 system.cpu0.icache.overall_misses::total 692806 # number of overall misses
685 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles
686 system.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles
687 system.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles
688 system.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles
689 system.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles
690 system.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles
691 system.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses)
692 system.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses)
693 system.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses
694 system.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses
695 system.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses
696 system.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses
697 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses
698 system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses
699 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses
700 system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses
701 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses
702 system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses
703 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency
704 system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency
705 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency
706 system.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency
707 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency
708 system.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency
709 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
710 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
711 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
712 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
713 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
714 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
715 system.cpu0.icache.writebacks::writebacks 692168 # number of writebacks
716 system.cpu0.icache.writebacks::total 692168 # number of writebacks
717 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses
718 system.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses
719 system.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses
720 system.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses
721 system.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses
722 system.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses
723 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles
724 system.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles
725 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles
726 system.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles
727 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles
728 system.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles
729 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses
730 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses
731 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses
732 system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses
733 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses
734 system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses
735 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency
736 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency
737 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency
738 system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency
739 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency
740 system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency
741 system.cpu1.dtb.fetch_hits 0 # ITB hits
742 system.cpu1.dtb.fetch_misses 0 # ITB misses
743 system.cpu1.dtb.fetch_acv 0 # ITB acv
744 system.cpu1.dtb.fetch_accesses 0 # ITB accesses
745 system.cpu1.dtb.read_hits 2442461 # DTB read hits
746 system.cpu1.dtb.read_misses 2621 # DTB read misses
747 system.cpu1.dtb.read_acv 0 # DTB read access violations
748 system.cpu1.dtb.read_accesses 205338 # DTB read accesses
749 system.cpu1.dtb.write_hits 1749247 # DTB write hits
750 system.cpu1.dtb.write_misses 236 # DTB write misses
751 system.cpu1.dtb.write_acv 24 # DTB write access violations
752 system.cpu1.dtb.write_accesses 89740 # DTB write accesses
753 system.cpu1.dtb.data_hits 4191708 # DTB hits
754 system.cpu1.dtb.data_misses 2857 # DTB misses
755 system.cpu1.dtb.data_acv 24 # DTB access violations
756 system.cpu1.dtb.data_accesses 295078 # DTB accesses
757 system.cpu1.itb.fetch_hits 1826964 # ITB hits
758 system.cpu1.itb.fetch_misses 1064 # ITB misses
759 system.cpu1.itb.fetch_acv 0 # ITB acv
760 system.cpu1.itb.fetch_accesses 1828028 # ITB accesses
761 system.cpu1.itb.read_hits 0 # DTB read hits
762 system.cpu1.itb.read_misses 0 # DTB read misses
763 system.cpu1.itb.read_acv 0 # DTB read access violations
764 system.cpu1.itb.read_accesses 0 # DTB read accesses
765 system.cpu1.itb.write_hits 0 # DTB write hits
766 system.cpu1.itb.write_misses 0 # DTB write misses
767 system.cpu1.itb.write_acv 0 # DTB write access violations
768 system.cpu1.itb.write_accesses 0 # DTB write accesses
769 system.cpu1.itb.data_hits 0 # DTB hits
770 system.cpu1.itb.data_misses 0 # DTB misses
771 system.cpu1.itb.data_acv 0 # DTB access violations
772 system.cpu1.itb.data_accesses 0 # DTB accesses
773 system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions
774 system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state
775 system.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state
776 system.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state
777 system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state
778 system.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state
779 system.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state
780 system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state
781 system.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states
782 system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states
783 system.cpu1.numCycles 3931646343 # number of cpu cycles simulated
784 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
785 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
786 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
787 system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed
788 system.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed
789 system.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl
790 system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl
791 system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl
792 system.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl
793 system.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl
794 system.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl
795 system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl
796 system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl
797 system.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl
798 system.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl
799 system.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl
800 system.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl
801 system.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl
802 system.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl
803 system.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl
804 system.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl
805 system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
806 system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
807 system.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl
808 system.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl
809 system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
810 system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed
811 system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
812 system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
813 system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed
814 system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed
815 system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed
816 system.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed
817 system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed
818 system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed
819 system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed
820 system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed
821 system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed
822 system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
823 system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
824 system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
825 system.cpu1.kern.callpal::total 73263 # number of callpals executed
826 system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches
827 system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
828 system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches
829 system.cpu1.kern.mode_good::kernel 816
830 system.cpu1.kern.mode_good::user 367
831 system.cpu1.kern.mode_good::idle 449
832 system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches
833 system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
834 system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches
835 system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches
836 system.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode
837 system.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode
838 system.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode
839 system.cpu1.kern.swap_context 2017 # number of times the context was actually changed
840 system.cpu1.committedInsts 13268542 # Number of instructions committed
841 system.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed
842 system.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses
843 system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses
844 system.cpu1.num_func_calls 423403 # number of times a function call or return occured
845 system.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls
846 system.cpu1.num_int_insts 12224320 # number of integer instructions
847 system.cpu1.num_fp_insts 175144 # number of float instructions
848 system.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read
849 system.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written
850 system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read
851 system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written
852 system.cpu1.num_mem_refs 4214775 # number of memory refs
853 system.cpu1.num_load_insts 2456291 # Number of load instructions
854 system.cpu1.num_store_insts 1758484 # Number of store instructions
855 system.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles
856 system.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles
857 system.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles
858 system.cpu1.idle_fraction 0.987229 # Percentage of idle cycles
859 system.cpu1.Branches 1898911 # Number of branches fetched
860 system.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction
861 system.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction
862 system.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction
863 system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction
864 system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction
865 system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction
866 system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction
867 system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction
868 system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction
869 system.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction
870 system.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction
871 system.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction
872 system.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction
873 system.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction
874 system.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction
875 system.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction
876 system.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction
877 system.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction
878 system.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction
879 system.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction
880 system.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction
881 system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction
882 system.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction
883 system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction
884 system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction
885 system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction
886 system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction
887 system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction
888 system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction
889 system.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction
890 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction
891 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction
892 system.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction
893 system.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction
894 system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction
895 system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction
896 system.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction
897 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
898 system.cpu1.op_class::total 13271423 # Class of executed instruction
899 system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
900 system.cpu1.dcache.tags.replacements 162127 # number of replacements
901 system.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use
902 system.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks.
903 system.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks.
904 system.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks.
905 system.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit.
906 system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor
907 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy
908 system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy
909 system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id
910 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
911 system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
912 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id
913 system.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses
914 system.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses
915 system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
916 system.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits
917 system.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits
918 system.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits
919 system.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits
920 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits
921 system.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits
922 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits
923 system.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits
924 system.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits
925 system.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits
926 system.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits
927 system.cpu1.dcache.overall_hits::total 3907923 # number of overall hits
928 system.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses
929 system.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses
930 system.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses
931 system.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses
932 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses
933 system.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses
934 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses
935 system.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses
936 system.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses
937 system.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses
938 system.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses
939 system.cpu1.dcache.overall_misses::total 177481 # number of overall misses
940 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles
941 system.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles
942 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles
943 system.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles
944 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles
945 system.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles
946 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles
947 system.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles
948 system.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles
949 system.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles
950 system.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles
951 system.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles
952 system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses)
953 system.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses)
954 system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses)
955 system.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses)
956 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses)
957 system.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses)
958 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses)
959 system.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses)
960 system.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses
961 system.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses
962 system.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses
963 system.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses
964 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses
965 system.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses
966 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses
967 system.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # miss rate for WriteReq accesses
968 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149868 # miss rate for LoadLockedReq accesses
969 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149868 # miss rate for LoadLockedReq accesses
970 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105099 # miss rate for StoreCondReq accesses
971 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105099 # miss rate for StoreCondReq accesses
972 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043443 # miss rate for demand accesses
973 system.cpu1.dcache.demand_miss_rate::total 0.043443 # miss rate for demand accesses
974 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043443 # miss rate for overall accesses
975 system.cpu1.dcache.overall_miss_rate::total 0.043443 # miss rate for overall accesses
976 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852 # average ReadReq miss latency
977 system.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852 # average ReadReq miss latency
978 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533 # average WriteReq miss latency
979 system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency
980 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency
981 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency
982 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency
983 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency
984 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency
985 system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency
986 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency
987 system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency
988 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
989 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
990 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
991 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
992 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
993 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
994 system.cpu1.dcache.writebacks::writebacks 111642 # number of writebacks
995 system.cpu1.dcache.writebacks::total 111642 # number of writebacks
996 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118690 # number of ReadReq MSHR misses
997 system.cpu1.dcache.ReadReq_mshr_misses::total 118690 # number of ReadReq MSHR misses
998 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58791 # number of WriteReq MSHR misses
999 system.cpu1.dcache.WriteReq_mshr_misses::total 58791 # number of WriteReq MSHR misses
1000 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9152 # number of LoadLockedReq MSHR misses
1001 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9152 # number of LoadLockedReq MSHR misses
1002 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6117 # number of StoreCondReq MSHR misses
1003 system.cpu1.dcache.StoreCondReq_mshr_misses::total 6117 # number of StoreCondReq MSHR misses
1004 system.cpu1.dcache.demand_mshr_misses::cpu1.data 177481 # number of demand (read+write) MSHR misses
1005 system.cpu1.dcache.demand_mshr_misses::total 177481 # number of demand (read+write) MSHR misses
1006 system.cpu1.dcache.overall_mshr_misses::cpu1.data 177481 # number of overall MSHR misses
1007 system.cpu1.dcache.overall_mshr_misses::total 177481 # number of overall MSHR misses
1008 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable
1009 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable
1010 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable
1011 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable
1012 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses
1013 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses
1014 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1348753500 # number of ReadReq MSHR miss cycles
1015 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1348753500 # number of ReadReq MSHR miss cycles
1016 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1241737500 # number of WriteReq MSHR miss cycles
1017 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1241737500 # number of WriteReq MSHR miss cycles
1018 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74910000 # number of LoadLockedReq MSHR miss cycles
1019 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles
1020 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles
1021 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles
1022 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles
1023 system.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles
1024 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles
1025 system.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles
1026 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles
1027 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles
1028 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles
1029 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles
1030 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses
1031 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses
1032 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses
1033 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses
1034 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses
1035 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses
1036 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses
1037 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses
1038 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses
1039 system.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses
1040 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses
1041 system.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses
1042 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency
1043 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency
1044 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency
1045 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency
1046 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency
1047 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency
1048 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency
1049 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency
1050 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency
1051 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency
1052 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency
1053 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency
1054 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency
1055 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency
1056 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency
1057 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency
1058 system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1059 system.cpu1.icache.tags.replacements 326560 # number of replacements
1060 system.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use
1061 system.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks.
1062 system.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks.
1063 system.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks.
1064 system.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit.
1065 system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor
1066 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy
1067 system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy
1068 system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1069 system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
1070 system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id
1071 system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
1072 system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1073 system.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses
1074 system.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses
1075 system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1076 system.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits
1077 system.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits
1078 system.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits
1079 system.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits
1080 system.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits
1081 system.cpu1.icache.overall_hits::total 12944312 # number of overall hits
1082 system.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses
1083 system.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses
1084 system.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses
1085 system.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses
1086 system.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses
1087 system.cpu1.icache.overall_misses::total 327111 # number of overall misses
1088 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles
1089 system.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles
1090 system.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles
1091 system.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles
1092 system.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles
1093 system.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles
1094 system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses)
1095 system.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses)
1096 system.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses
1097 system.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses
1098 system.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses
1099 system.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses
1100 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses
1101 system.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses
1102 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses
1103 system.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses
1104 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses
1105 system.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses
1106 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency
1107 system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency
1108 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency
1109 system.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency
1110 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency
1111 system.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency
1112 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1113 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1114 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1115 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1116 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1117 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1118 system.cpu1.icache.writebacks::writebacks 326560 # number of writebacks
1119 system.cpu1.icache.writebacks::total 326560 # number of writebacks
1120 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses
1121 system.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses
1122 system.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses
1123 system.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses
1124 system.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses
1125 system.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses
1126 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles
1127 system.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles
1128 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles
1129 system.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles
1130 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles
1131 system.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles
1132 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses
1133 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses
1134 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses
1135 system.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses
1136 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses
1137 system.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses
1138 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency
1139 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency
1140 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency
1141 system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency
1142 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency
1143 system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency
1144 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1145 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1146 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1147 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1148 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1149 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1150 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1151 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1152 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1153 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1154 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1155 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1156 system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1157 system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
1158 system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
1159 system.iobus.trans_dist::WriteReq 55675 # Transaction distribution
1160 system.iobus.trans_dist::WriteResp 55675 # Transaction distribution
1161 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes)
1162 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
1163 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1164 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1165 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1166 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1167 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1168 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1169 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1170 system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes)
1171 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
1172 system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
1173 system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes)
1174 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes)
1175 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
1176 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1177 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1178 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1179 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1180 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1181 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1182 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1183 system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes)
1184 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
1185 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
1186 system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes)
1187 system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks)
1188 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1189 system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks)
1190 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1191 system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
1192 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1193 system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
1194 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1195 system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks)
1196 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1197 system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks)
1198 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1199 system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks)
1200 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1201 system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks)
1202 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1203 system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1204 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1205 system.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks)
1206 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1207 system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks)
1208 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1209 system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks)
1210 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1211 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1212 system.iocache.tags.replacements 41698 # number of replacements
1213 system.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use
1214 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1215 system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
1216 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1217 system.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit.
1218 system.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor
1219 system.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy
1220 system.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy
1221 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1222 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1223 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1224 system.iocache.tags.tag_accesses 375570 # Number of tag accesses
1225 system.iocache.tags.data_accesses 375570 # Number of data accesses
1226 system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1227 system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
1228 system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
1229 system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1230 system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1231 system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses
1232 system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
1233 system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses
1234 system.iocache.overall_misses::total 41730 # number of overall misses
1235 system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles
1236 system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles
1237 system.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles
1238 system.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles
1239 system.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles
1240 system.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles
1241 system.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles
1242 system.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles
1243 system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
1244 system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
1245 system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1246 system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1247 system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses
1248 system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
1249 system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
1250 system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
1251 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1252 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1253 system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1254 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1255 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1256 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1257 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1258 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1259 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency
1260 system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency
1261 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency
1262 system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency
1263 system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency
1264 system.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency
1265 system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency
1266 system.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency
1267 system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked
1268 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1269 system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked
1270 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1271 system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked
1272 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1273 system.iocache.writebacks::writebacks 41520 # number of writebacks
1274 system.iocache.writebacks::total 41520 # number of writebacks
1275 system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
1276 system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
1277 system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1278 system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1279 system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses
1280 system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses
1281 system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses
1282 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses
1283 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles
1284 system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles
1285 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles
1286 system.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles
1287 system.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles
1288 system.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles
1289 system.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles
1290 system.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles
1291 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1292 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1293 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1294 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1295 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1296 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1297 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1298 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1299 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency
1300 system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency
1301 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency
1302 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency
1303 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency
1304 system.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency
1305 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency
1306 system.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency
1307 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1308 system.l2c.tags.replacements 342924 # number of replacements
1309 system.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use
1310 system.l2c.tags.total_refs 3989934 # Total number of references to valid blocks.
1311 system.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks.
1312 system.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks.
1313 system.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit.
1314 system.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor
1315 system.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor
1316 system.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor
1317 system.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor
1318 system.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor
1319 system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy
1320 system.l2c.tags.occ_percent::cpu0.inst 0.073152 # Average percentage of cache occupancy
1321 system.l2c.tags.occ_percent::cpu0.data 0.904926 # Average percentage of cache occupancy
1322 system.l2c.tags.occ_percent::cpu1.inst 0.002531 # Average percentage of cache occupancy
1323 system.l2c.tags.occ_percent::cpu1.data 0.012802 # Average percentage of cache occupancy
1324 system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy
1325 system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id
1326 system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
1327 system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id
1328 system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
1329 system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id
1330 system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id
1331 system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id
1332 system.l2c.tags.tag_accesses 35598107 # Number of tag accesses
1333 system.l2c.tags.data_accesses 35598107 # Number of data accesses
1334 system.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1335 system.l2c.WritebackDirty_hits::writebacks 792905 # number of WritebackDirty hits
1336 system.l2c.WritebackDirty_hits::total 792905 # number of WritebackDirty hits
1337 system.l2c.WritebackClean_hits::writebacks 747283 # number of WritebackClean hits
1338 system.l2c.WritebackClean_hits::total 747283 # number of WritebackClean hits
1339 system.l2c.UpgradeReq_hits::cpu0.data 3151 # number of UpgradeReq hits
1340 system.l2c.UpgradeReq_hits::cpu1.data 2387 # number of UpgradeReq hits
1341 system.l2c.UpgradeReq_hits::total 5538 # number of UpgradeReq hits
1342 system.l2c.SCUpgradeReq_hits::cpu0.data 946 # number of SCUpgradeReq hits
1343 system.l2c.SCUpgradeReq_hits::cpu1.data 957 # number of SCUpgradeReq hits
1344 system.l2c.SCUpgradeReq_hits::total 1903 # number of SCUpgradeReq hits
1345 system.l2c.ReadExReq_hits::cpu0.data 128511 # number of ReadExReq hits
1346 system.l2c.ReadExReq_hits::cpu1.data 43286 # number of ReadExReq hits
1347 system.l2c.ReadExReq_hits::total 171797 # number of ReadExReq hits
1348 system.l2c.ReadCleanReq_hits::cpu0.inst 680335 # number of ReadCleanReq hits
1349 system.l2c.ReadCleanReq_hits::cpu1.inst 326126 # number of ReadCleanReq hits
1350 system.l2c.ReadCleanReq_hits::total 1006461 # number of ReadCleanReq hits
1351 system.l2c.ReadSharedReq_hits::cpu0.data 663262 # number of ReadSharedReq hits
1352 system.l2c.ReadSharedReq_hits::cpu1.data 108452 # number of ReadSharedReq hits
1353 system.l2c.ReadSharedReq_hits::total 771714 # number of ReadSharedReq hits
1354 system.l2c.demand_hits::cpu0.inst 680335 # number of demand (read+write) hits
1355 system.l2c.demand_hits::cpu0.data 791773 # number of demand (read+write) hits
1356 system.l2c.demand_hits::cpu1.inst 326126 # number of demand (read+write) hits
1357 system.l2c.demand_hits::cpu1.data 151738 # number of demand (read+write) hits
1358 system.l2c.demand_hits::total 1949972 # number of demand (read+write) hits
1359 system.l2c.overall_hits::cpu0.inst 680335 # number of overall hits
1360 system.l2c.overall_hits::cpu0.data 791773 # number of overall hits
1361 system.l2c.overall_hits::cpu1.inst 326126 # number of overall hits
1362 system.l2c.overall_hits::cpu1.data 151738 # number of overall hits
1363 system.l2c.overall_hits::total 1949972 # number of overall hits
1364 system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses
1365 system.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses
1366 system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses
1367 system.l2c.ReadExReq_misses::cpu0.data 116816 # number of ReadExReq misses
1368 system.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses
1369 system.l2c.ReadExReq_misses::total 123235 # number of ReadExReq misses
1370 system.l2c.ReadCleanReq_misses::cpu0.inst 12450 # number of ReadCleanReq misses
1371 system.l2c.ReadCleanReq_misses::cpu1.inst 984 # number of ReadCleanReq misses
1372 system.l2c.ReadCleanReq_misses::total 13434 # number of ReadCleanReq misses
1373 system.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses
1374 system.l2c.ReadSharedReq_misses::cpu1.data 339 # number of ReadSharedReq misses
1375 system.l2c.ReadSharedReq_misses::total 271856 # number of ReadSharedReq misses
1376 system.l2c.demand_misses::cpu0.inst 12450 # number of demand (read+write) misses
1377 system.l2c.demand_misses::cpu0.data 388333 # number of demand (read+write) misses
1378 system.l2c.demand_misses::cpu1.inst 984 # number of demand (read+write) misses
1379 system.l2c.demand_misses::cpu1.data 6758 # number of demand (read+write) misses
1380 system.l2c.demand_misses::total 408525 # number of demand (read+write) misses
1381 system.l2c.overall_misses::cpu0.inst 12450 # number of overall misses
1382 system.l2c.overall_misses::cpu0.data 388333 # number of overall misses
1383 system.l2c.overall_misses::cpu1.inst 984 # number of overall misses
1384 system.l2c.overall_misses::cpu1.data 6758 # number of overall misses
1385 system.l2c.overall_misses::total 408525 # number of overall misses
1386 system.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles
1387 system.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles
1388 system.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles
1389 system.l2c.ReadExReq_miss_latency::cpu0.data 10623244500 # number of ReadExReq miss cycles
1390 system.l2c.ReadExReq_miss_latency::cpu1.data 659466000 # number of ReadExReq miss cycles
1391 system.l2c.ReadExReq_miss_latency::total 11282710500 # number of ReadExReq miss cycles
1392 system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281529500 # number of ReadCleanReq miss cycles
1393 system.l2c.ReadCleanReq_miss_latency::cpu1.inst 100368000 # number of ReadCleanReq miss cycles
1394 system.l2c.ReadCleanReq_miss_latency::total 1381897500 # number of ReadCleanReq miss cycles
1395 system.l2c.ReadSharedReq_miss_latency::cpu0.data 21945590000 # number of ReadSharedReq miss cycles
1396 system.l2c.ReadSharedReq_miss_latency::cpu1.data 41766500 # number of ReadSharedReq miss cycles
1397 system.l2c.ReadSharedReq_miss_latency::total 21987356500 # number of ReadSharedReq miss cycles
1398 system.l2c.demand_miss_latency::cpu0.inst 1281529500 # number of demand (read+write) miss cycles
1399 system.l2c.demand_miss_latency::cpu0.data 32568834500 # number of demand (read+write) miss cycles
1400 system.l2c.demand_miss_latency::cpu1.inst 100368000 # number of demand (read+write) miss cycles
1401 system.l2c.demand_miss_latency::cpu1.data 701232500 # number of demand (read+write) miss cycles
1402 system.l2c.demand_miss_latency::total 34651964500 # number of demand (read+write) miss cycles
1403 system.l2c.overall_miss_latency::cpu0.inst 1281529500 # number of overall miss cycles
1404 system.l2c.overall_miss_latency::cpu0.data 32568834500 # number of overall miss cycles
1405 system.l2c.overall_miss_latency::cpu1.inst 100368000 # number of overall miss cycles
1406 system.l2c.overall_miss_latency::cpu1.data 701232500 # number of overall miss cycles
1407 system.l2c.overall_miss_latency::total 34651964500 # number of overall miss cycles
1408 system.l2c.WritebackDirty_accesses::writebacks 792905 # number of WritebackDirty accesses(hits+misses)
1409 system.l2c.WritebackDirty_accesses::total 792905 # number of WritebackDirty accesses(hits+misses)
1410 system.l2c.WritebackClean_accesses::writebacks 747283 # number of WritebackClean accesses(hits+misses)
1411 system.l2c.WritebackClean_accesses::total 747283 # number of WritebackClean accesses(hits+misses)
1412 system.l2c.UpgradeReq_accesses::cpu0.data 3156 # number of UpgradeReq accesses(hits+misses)
1413 system.l2c.UpgradeReq_accesses::cpu1.data 2388 # number of UpgradeReq accesses(hits+misses)
1414 system.l2c.UpgradeReq_accesses::total 5544 # number of UpgradeReq accesses(hits+misses)
1415 system.l2c.SCUpgradeReq_accesses::cpu0.data 946 # number of SCUpgradeReq accesses(hits+misses)
1416 system.l2c.SCUpgradeReq_accesses::cpu1.data 957 # number of SCUpgradeReq accesses(hits+misses)
1417 system.l2c.SCUpgradeReq_accesses::total 1903 # number of SCUpgradeReq accesses(hits+misses)
1418 system.l2c.ReadExReq_accesses::cpu0.data 245327 # number of ReadExReq accesses(hits+misses)
1419 system.l2c.ReadExReq_accesses::cpu1.data 49705 # number of ReadExReq accesses(hits+misses)
1420 system.l2c.ReadExReq_accesses::total 295032 # number of ReadExReq accesses(hits+misses)
1421 system.l2c.ReadCleanReq_accesses::cpu0.inst 692785 # number of ReadCleanReq accesses(hits+misses)
1422 system.l2c.ReadCleanReq_accesses::cpu1.inst 327110 # number of ReadCleanReq accesses(hits+misses)
1423 system.l2c.ReadCleanReq_accesses::total 1019895 # number of ReadCleanReq accesses(hits+misses)
1424 system.l2c.ReadSharedReq_accesses::cpu0.data 934779 # number of ReadSharedReq accesses(hits+misses)
1425 system.l2c.ReadSharedReq_accesses::cpu1.data 108791 # number of ReadSharedReq accesses(hits+misses)
1426 system.l2c.ReadSharedReq_accesses::total 1043570 # number of ReadSharedReq accesses(hits+misses)
1427 system.l2c.demand_accesses::cpu0.inst 692785 # number of demand (read+write) accesses
1428 system.l2c.demand_accesses::cpu0.data 1180106 # number of demand (read+write) accesses
1429 system.l2c.demand_accesses::cpu1.inst 327110 # number of demand (read+write) accesses
1430 system.l2c.demand_accesses::cpu1.data 158496 # number of demand (read+write) accesses
1431 system.l2c.demand_accesses::total 2358497 # number of demand (read+write) accesses
1432 system.l2c.overall_accesses::cpu0.inst 692785 # number of overall (read+write) accesses
1433 system.l2c.overall_accesses::cpu0.data 1180106 # number of overall (read+write) accesses
1434 system.l2c.overall_accesses::cpu1.inst 327110 # number of overall (read+write) accesses
1435 system.l2c.overall_accesses::cpu1.data 158496 # number of overall (read+write) accesses
1436 system.l2c.overall_accesses::total 2358497 # number of overall (read+write) accesses
1437 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001584 # miss rate for UpgradeReq accesses
1438 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000419 # miss rate for UpgradeReq accesses
1439 system.l2c.UpgradeReq_miss_rate::total 0.001082 # miss rate for UpgradeReq accesses
1440 system.l2c.ReadExReq_miss_rate::cpu0.data 0.476164 # miss rate for ReadExReq accesses
1441 system.l2c.ReadExReq_miss_rate::cpu1.data 0.129142 # miss rate for ReadExReq accesses
1442 system.l2c.ReadExReq_miss_rate::total 0.417700 # miss rate for ReadExReq accesses
1443 system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017971 # miss rate for ReadCleanReq accesses
1444 system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003008 # miss rate for ReadCleanReq accesses
1445 system.l2c.ReadCleanReq_miss_rate::total 0.013172 # miss rate for ReadCleanReq accesses
1446 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290461 # miss rate for ReadSharedReq accesses
1447 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003116 # miss rate for ReadSharedReq accesses
1448 system.l2c.ReadSharedReq_miss_rate::total 0.260506 # miss rate for ReadSharedReq accesses
1449 system.l2c.demand_miss_rate::cpu0.inst 0.017971 # miss rate for demand accesses
1450 system.l2c.demand_miss_rate::cpu0.data 0.329066 # miss rate for demand accesses
1451 system.l2c.demand_miss_rate::cpu1.inst 0.003008 # miss rate for demand accesses
1452 system.l2c.demand_miss_rate::cpu1.data 0.042638 # miss rate for demand accesses
1453 system.l2c.demand_miss_rate::total 0.173214 # miss rate for demand accesses
1454 system.l2c.overall_miss_rate::cpu0.inst 0.017971 # miss rate for overall accesses
1455 system.l2c.overall_miss_rate::cpu0.data 0.329066 # miss rate for overall accesses
1456 system.l2c.overall_miss_rate::cpu1.inst 0.003008 # miss rate for overall accesses
1457 system.l2c.overall_miss_rate::cpu1.data 0.042638 # miss rate for overall accesses
1458 system.l2c.overall_miss_rate::total 0.173214 # miss rate for overall accesses
1459 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 60000 # average UpgradeReq miss latency
1460 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 28500 # average UpgradeReq miss latency
1461 system.l2c.UpgradeReq_avg_miss_latency::total 54750 # average UpgradeReq miss latency
1462 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90939.978256 # average ReadExReq miss latency
1463 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102736.563328 # average ReadExReq miss latency
1464 system.l2c.ReadExReq_avg_miss_latency::total 91554.432588 # average ReadExReq miss latency
1465 system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 102934.096386 # average ReadCleanReq miss latency
1466 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102000 # average ReadCleanReq miss latency
1467 system.l2c.ReadCleanReq_avg_miss_latency::total 102865.676641 # average ReadCleanReq miss latency
1468 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80825.841476 # average ReadSharedReq miss latency
1469 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123205.014749 # average ReadSharedReq miss latency
1470 system.l2c.ReadSharedReq_avg_miss_latency::total 80878.687614 # average ReadSharedReq miss latency
1471 system.l2c.demand_avg_miss_latency::cpu0.inst 102934.096386 # average overall miss latency
1472 system.l2c.demand_avg_miss_latency::cpu0.data 83868.315338 # average overall miss latency
1473 system.l2c.demand_avg_miss_latency::cpu1.inst 102000 # average overall miss latency
1474 system.l2c.demand_avg_miss_latency::cpu1.data 103763.317550 # average overall miss latency
1475 system.l2c.demand_avg_miss_latency::total 84822.139404 # average overall miss latency
1476 system.l2c.overall_avg_miss_latency::cpu0.inst 102934.096386 # average overall miss latency
1477 system.l2c.overall_avg_miss_latency::cpu0.data 83868.315338 # average overall miss latency
1478 system.l2c.overall_avg_miss_latency::cpu1.inst 102000 # average overall miss latency
1479 system.l2c.overall_avg_miss_latency::cpu1.data 103763.317550 # average overall miss latency
1480 system.l2c.overall_avg_miss_latency::total 84822.139404 # average overall miss latency
1481 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1482 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1483 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1484 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1485 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1486 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1487 system.l2c.writebacks::writebacks 79955 # number of writebacks
1488 system.l2c.writebacks::total 79955 # number of writebacks
1489 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
1490 system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1491 system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
1492 system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
1493 system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
1494 system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
1495 system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
1496 system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
1497 system.l2c.UpgradeReq_mshr_misses::cpu0.data 5 # number of UpgradeReq MSHR misses
1498 system.l2c.UpgradeReq_mshr_misses::cpu1.data 1 # number of UpgradeReq MSHR misses
1499 system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
1500 system.l2c.ReadExReq_mshr_misses::cpu0.data 116816 # number of ReadExReq MSHR misses
1501 system.l2c.ReadExReq_mshr_misses::cpu1.data 6419 # number of ReadExReq MSHR misses
1502 system.l2c.ReadExReq_mshr_misses::total 123235 # number of ReadExReq MSHR misses
1503 system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12450 # number of ReadCleanReq MSHR misses
1504 system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 973 # number of ReadCleanReq MSHR misses
1505 system.l2c.ReadCleanReq_mshr_misses::total 13423 # number of ReadCleanReq MSHR misses
1506 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271517 # number of ReadSharedReq MSHR misses
1507 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 339 # number of ReadSharedReq MSHR misses
1508 system.l2c.ReadSharedReq_mshr_misses::total 271856 # number of ReadSharedReq MSHR misses
1509 system.l2c.demand_mshr_misses::cpu0.inst 12450 # number of demand (read+write) MSHR misses
1510 system.l2c.demand_mshr_misses::cpu0.data 388333 # number of demand (read+write) MSHR misses
1511 system.l2c.demand_mshr_misses::cpu1.inst 973 # number of demand (read+write) MSHR misses
1512 system.l2c.demand_mshr_misses::cpu1.data 6758 # number of demand (read+write) MSHR misses
1513 system.l2c.demand_mshr_misses::total 408514 # number of demand (read+write) MSHR misses
1514 system.l2c.overall_mshr_misses::cpu0.inst 12450 # number of overall MSHR misses
1515 system.l2c.overall_mshr_misses::cpu0.data 388333 # number of overall MSHR misses
1516 system.l2c.overall_mshr_misses::cpu1.inst 973 # number of overall MSHR misses
1517 system.l2c.overall_mshr_misses::cpu1.data 6758 # number of overall MSHR misses
1518 system.l2c.overall_mshr_misses::total 408514 # number of overall MSHR misses
1519 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable
1520 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable
1521 system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable
1522 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable
1523 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable
1524 system.l2c.WriteReq_mshr_uncacheable::total 14123 # number of WriteReq MSHR uncacheable
1525 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses
1526 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses
1527 system.l2c.overall_mshr_uncacheable_misses::total 21321 # number of overall MSHR uncacheable misses
1528 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 250000 # number of UpgradeReq MSHR miss cycles
1529 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of UpgradeReq MSHR miss cycles
1530 system.l2c.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles
1531 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9455084500 # number of ReadExReq MSHR miss cycles
1532 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595276000 # number of ReadExReq MSHR miss cycles
1533 system.l2c.ReadExReq_mshr_miss_latency::total 10050360500 # number of ReadExReq MSHR miss cycles
1534 system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157029500 # number of ReadCleanReq MSHR miss cycles
1535 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 89768000 # number of ReadCleanReq MSHR miss cycles
1536 system.l2c.ReadCleanReq_mshr_miss_latency::total 1246797500 # number of ReadCleanReq MSHR miss cycles
1537 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19230420000 # number of ReadSharedReq MSHR miss cycles
1538 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38376500 # number of ReadSharedReq MSHR miss cycles
1539 system.l2c.ReadSharedReq_mshr_miss_latency::total 19268796500 # number of ReadSharedReq MSHR miss cycles
1540 system.l2c.demand_mshr_miss_latency::cpu0.inst 1157029500 # number of demand (read+write) MSHR miss cycles
1541 system.l2c.demand_mshr_miss_latency::cpu0.data 28685504500 # number of demand (read+write) MSHR miss cycles
1542 system.l2c.demand_mshr_miss_latency::cpu1.inst 89768000 # number of demand (read+write) MSHR miss cycles
1543 system.l2c.demand_mshr_miss_latency::cpu1.data 633652500 # number of demand (read+write) MSHR miss cycles
1544 system.l2c.demand_mshr_miss_latency::total 30565954500 # number of demand (read+write) MSHR miss cycles
1545 system.l2c.overall_mshr_miss_latency::cpu0.inst 1157029500 # number of overall MSHR miss cycles
1546 system.l2c.overall_mshr_miss_latency::cpu0.data 28685504500 # number of overall MSHR miss cycles
1547 system.l2c.overall_mshr_miss_latency::cpu1.inst 89768000 # number of overall MSHR miss cycles
1548 system.l2c.overall_mshr_miss_latency::cpu1.data 633652500 # number of overall MSHR miss cycles
1549 system.l2c.overall_mshr_miss_latency::total 30565954500 # number of overall MSHR miss cycles
1550 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles
1551 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles
1552 system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles
1553 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles
1554 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles
1555 system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles
1556 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1557 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1558 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001584 # mshr miss rate for UpgradeReq accesses
1559 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000419 # mshr miss rate for UpgradeReq accesses
1560 system.l2c.UpgradeReq_mshr_miss_rate::total 0.001082 # mshr miss rate for UpgradeReq accesses
1561 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476164 # mshr miss rate for ReadExReq accesses
1562 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129142 # mshr miss rate for ReadExReq accesses
1563 system.l2c.ReadExReq_mshr_miss_rate::total 0.417700 # mshr miss rate for ReadExReq accesses
1564 system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for ReadCleanReq accesses
1565 system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for ReadCleanReq accesses
1566 system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013161 # mshr miss rate for ReadCleanReq accesses
1567 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290461 # mshr miss rate for ReadSharedReq accesses
1568 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003116 # mshr miss rate for ReadSharedReq accesses
1569 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260506 # mshr miss rate for ReadSharedReq accesses
1570 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for demand accesses
1571 system.l2c.demand_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for demand accesses
1572 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for demand accesses
1573 system.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses
1574 system.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses
1575 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses
1576 system.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses
1577 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses
1578 system.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses
1579 system.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses
1580 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency
1581 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency
1582 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency
1583 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency
1584 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency
1585 system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency
1586 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency
1587 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency
1588 system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency
1589 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency
1590 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency
1591 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency
1592 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency
1593 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency
1594 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency
1595 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency
1596 system.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency
1597 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency
1598 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency
1599 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency
1600 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency
1601 system.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency
1602 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency
1603 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency
1604 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency
1605 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency
1606 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency
1607 system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency
1608 system.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter.
1609 system.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1610 system.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1611 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1612 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1613 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1614 system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1615 system.membus.trans_dist::ReadReq 7198 # Transaction distribution
1616 system.membus.trans_dist::ReadResp 292655 # Transaction distribution
1617 system.membus.trans_dist::WriteReq 14123 # Transaction distribution
1618 system.membus.trans_dist::WriteResp 14123 # Transaction distribution
1619 system.membus.trans_dist::WritebackDirty 121475 # Transaction distribution
1620 system.membus.trans_dist::CleanEvict 262336 # Transaction distribution
1621 system.membus.trans_dist::UpgradeReq 11690 # Transaction distribution
1622 system.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution
1623 system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
1624 system.membus.trans_dist::ReadExReq 123955 # Transaction distribution
1625 system.membus.trans_dist::ReadExResp 123087 # Transaction distribution
1626 system.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution
1627 system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1628 system.membus.trans_dist::InvalidateResp 148 # Transaction distribution
1629 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes)
1630 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes)
1631 system.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes)
1632 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes)
1633 system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes)
1634 system.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes)
1635 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes)
1636 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes)
1637 system.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes)
1638 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
1639 system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
1640 system.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes)
1641 system.membus.snoops 22923 # Total snoops (count)
1642 system.membus.snoopTraffic 27264 # Total snoop traffic (bytes)
1643 system.membus.snoop_fanout::samples 493917 # Request fanout histogram
1644 system.membus.snoop_fanout::mean 0.001373 # Request fanout histogram
1645 system.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram
1646 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1647 system.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram
1648 system.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram
1649 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1650 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1651 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1652 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1653 system.membus.snoop_fanout::total 493917 # Request fanout histogram
1654 system.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks)
1655 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1656 system.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks)
1657 system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1658 system.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks)
1659 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1660 system.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks)
1661 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1662 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1663 system.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter.
1664 system.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1665 system.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1666 system.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter.
1667 system.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1668 system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1669 system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1670 system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution
1671 system.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution
1672 system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution
1673 system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution
1674 system.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution
1675 system.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution
1676 system.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution
1677 system.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution
1678 system.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution
1679 system.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution
1680 system.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution
1681 system.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution
1682 system.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution
1683 system.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution
1684 system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution
1685 system.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution
1686 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes)
1687 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes)
1688 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes)
1689 system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes)
1690 system.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes)
1691 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes)
1692 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes)
1693 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes)
1694 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes)
1695 system.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes)
1696 system.toL2Bus.snoops 403271 # Total snoops (count)
1697 system.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes)
1698 system.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram
1699 system.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram
1700 system.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram
1701 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1702 system.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram
1703 system.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram
1704 system.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram
1705 system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram
1706 system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1707 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1708 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1709 system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
1710 system.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram
1711 system.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks)
1712 system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1713 system.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks)
1714 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1715 system.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks)
1716 system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1717 system.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks)
1718 system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1719 system.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks)
1720 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1721 system.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks)
1722 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1723 system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1724 system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1725 system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1726 system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1727 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1728 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1729 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1730 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1731 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1732 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1733 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1734 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1735 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1736 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1737 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1738 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1739 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1740 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1741 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1742 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1743 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1744 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1745 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1746 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1747 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1748 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1749 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1750 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1751 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1752 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1753 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1754 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1755 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1756 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1757 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1758 system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1759 system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1760 system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1761 system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1762 system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1763 system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1764 system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1765 system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1766 system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1767 system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1768 system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1769 system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1770 system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1771 system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1772 system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1773 system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1774 system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1775 system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1776 system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1777 system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1778 system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1779 system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1780 system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1782 ---------- End Simulation Statistics ----------
projects / gem5.git / blob