2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.958647 # Number of seconds simulated
4 sim_ticks 1958647095000 # Number of ticks simulated
5 final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 669282 # Simulator instruction rate (inst/s)
8 host_op_rate 669282 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 22085281308 # Simulator tick rate (ticks/s)
10 host_mem_usage 295084 # Number of bytes of host memory used
11 host_seconds 88.69 # Real time elapsed on the host
12 sim_insts 59355643 # Number of instructions simulated
13 sim_ops 59355643 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 30050624 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 10333120 # Number of bytes written to this memory
17 system.physmem.num_reads 469541 # Number of read requests responded to by this memory
18 system.physmem.num_writes 161455 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s)
24 system.l2c.replacements 393576 # number of replacements
25 system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use
26 system.l2c.total_refs 2371449 # Total number of references to valid blocks.
27 system.l2c.sampled_refs 427769 # Sample count of references to valid blocks.
28 system.l2c.avg_refs 5.543761 # Average number of references to valid blocks.
29 system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit.
30 system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor
31 system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor
32 system.l2c.occ_blocks::cpu0.data 7139.593108 # Average occupied blocks per requestor
33 system.l2c.occ_blocks::cpu1.inst 100.838318 # Average occupied blocks per requestor
34 system.l2c.occ_blocks::cpu1.data 99.145617 # Average occupied blocks per requestor
35 system.l2c.occ_percent::writebacks 0.357359 # Average percentage of cache occupancy
36 system.l2c.occ_percent::cpu0.inst 0.056890 # Average percentage of cache occupancy
37 system.l2c.occ_percent::cpu0.data 0.108942 # Average percentage of cache occupancy
38 system.l2c.occ_percent::cpu1.inst 0.001539 # Average percentage of cache occupancy
39 system.l2c.occ_percent::cpu1.data 0.001513 # Average percentage of cache occupancy
40 system.l2c.occ_percent::total 0.526242 # Average percentage of cache occupancy
41 system.l2c.ReadReq_hits::cpu0.inst 901389 # number of ReadReq hits
42 system.l2c.ReadReq_hits::cpu0.data 758006 # number of ReadReq hits
43 system.l2c.ReadReq_hits::cpu1.inst 86187 # number of ReadReq hits
44 system.l2c.ReadReq_hits::cpu1.data 33004 # number of ReadReq hits
45 system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits
46 system.l2c.Writeback_hits::writebacks 816294 # number of Writeback hits
47 system.l2c.Writeback_hits::total 816294 # number of Writeback hits
48 system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits
49 system.l2c.UpgradeReq_hits::cpu1.data 53 # number of UpgradeReq hits
50 system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits
51 system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits
52 system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits
53 system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits
54 system.l2c.ReadExReq_hits::cpu0.data 170288 # number of ReadExReq hits
55 system.l2c.ReadExReq_hits::cpu1.data 12569 # number of ReadExReq hits
56 system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits
57 system.l2c.demand_hits::cpu0.inst 901389 # number of demand (read+write) hits
58 system.l2c.demand_hits::cpu0.data 928294 # number of demand (read+write) hits
59 system.l2c.demand_hits::cpu1.inst 86187 # number of demand (read+write) hits
60 system.l2c.demand_hits::cpu1.data 45573 # number of demand (read+write) hits
61 system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits
62 system.l2c.overall_hits::cpu0.inst 901389 # number of overall hits
63 system.l2c.overall_hits::cpu0.data 928294 # number of overall hits
64 system.l2c.overall_hits::cpu1.inst 86187 # number of overall hits
65 system.l2c.overall_hits::cpu1.data 45573 # number of overall hits
66 system.l2c.overall_hits::total 1961443 # number of overall hits
67 system.l2c.ReadReq_misses::cpu0.inst 14371 # number of ReadReq misses
68 system.l2c.ReadReq_misses::cpu0.data 288456 # number of ReadReq misses
69 system.l2c.ReadReq_misses::cpu1.inst 815 # number of ReadReq misses
70 system.l2c.ReadReq_misses::cpu1.data 1138 # number of ReadReq misses
71 system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses
72 system.l2c.UpgradeReq_misses::cpu0.data 2453 # number of UpgradeReq misses
73 system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses
74 system.l2c.UpgradeReq_misses::total 2948 # number of UpgradeReq misses
75 system.l2c.SCUpgradeReq_misses::cpu0.data 15 # number of SCUpgradeReq misses
76 system.l2c.SCUpgradeReq_misses::cpu1.data 74 # number of SCUpgradeReq misses
77 system.l2c.SCUpgradeReq_misses::total 89 # number of SCUpgradeReq misses
78 system.l2c.ReadExReq_misses::cpu0.data 117546 # number of ReadExReq misses
79 system.l2c.ReadExReq_misses::cpu1.data 6196 # number of ReadExReq misses
80 system.l2c.ReadExReq_misses::total 123742 # number of ReadExReq misses
81 system.l2c.demand_misses::cpu0.inst 14371 # number of demand (read+write) misses
82 system.l2c.demand_misses::cpu0.data 406002 # number of demand (read+write) misses
83 system.l2c.demand_misses::cpu1.inst 815 # number of demand (read+write) misses
84 system.l2c.demand_misses::cpu1.data 7334 # number of demand (read+write) misses
85 system.l2c.demand_misses::total 428522 # number of demand (read+write) misses
86 system.l2c.overall_misses::cpu0.inst 14371 # number of overall misses
87 system.l2c.overall_misses::cpu0.data 406002 # number of overall misses
88 system.l2c.overall_misses::cpu1.inst 815 # number of overall misses
89 system.l2c.overall_misses::cpu1.data 7334 # number of overall misses
90 system.l2c.overall_misses::total 428522 # number of overall misses
91 system.l2c.ReadReq_miss_latency::cpu0.inst 747344500 # number of ReadReq miss cycles
92 system.l2c.ReadReq_miss_latency::cpu0.data 15004707000 # number of ReadReq miss cycles
93 system.l2c.ReadReq_miss_latency::cpu1.inst 42364500 # number of ReadReq miss cycles
94 system.l2c.ReadReq_miss_latency::cpu1.data 59224000 # number of ReadReq miss cycles
95 system.l2c.ReadReq_miss_latency::total 15853640000 # number of ReadReq miss cycles
96 system.l2c.UpgradeReq_miss_latency::cpu0.data 2244000 # number of UpgradeReq miss cycles
97 system.l2c.UpgradeReq_miss_latency::cpu1.data 780000 # number of UpgradeReq miss cycles
98 system.l2c.UpgradeReq_miss_latency::total 3024000 # number of UpgradeReq miss cycles
99 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 104000 # number of SCUpgradeReq miss cycles
100 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 312000 # number of SCUpgradeReq miss cycles
101 system.l2c.SCUpgradeReq_miss_latency::total 416000 # number of SCUpgradeReq miss cycles
102 system.l2c.ReadExReq_miss_latency::cpu0.data 6112681000 # number of ReadExReq miss cycles
103 system.l2c.ReadExReq_miss_latency::cpu1.data 322197000 # number of ReadExReq miss cycles
104 system.l2c.ReadExReq_miss_latency::total 6434878000 # number of ReadExReq miss cycles
105 system.l2c.demand_miss_latency::cpu0.inst 747344500 # number of demand (read+write) miss cycles
106 system.l2c.demand_miss_latency::cpu0.data 21117388000 # number of demand (read+write) miss cycles
107 system.l2c.demand_miss_latency::cpu1.inst 42364500 # number of demand (read+write) miss cycles
108 system.l2c.demand_miss_latency::cpu1.data 381421000 # number of demand (read+write) miss cycles
109 system.l2c.demand_miss_latency::total 22288518000 # number of demand (read+write) miss cycles
110 system.l2c.overall_miss_latency::cpu0.inst 747344500 # number of overall miss cycles
111 system.l2c.overall_miss_latency::cpu0.data 21117388000 # number of overall miss cycles
112 system.l2c.overall_miss_latency::cpu1.inst 42364500 # number of overall miss cycles
113 system.l2c.overall_miss_latency::cpu1.data 381421000 # number of overall miss cycles
114 system.l2c.overall_miss_latency::total 22288518000 # number of overall miss cycles
115 system.l2c.ReadReq_accesses::cpu0.inst 915760 # number of ReadReq accesses(hits+misses)
116 system.l2c.ReadReq_accesses::cpu0.data 1046462 # number of ReadReq accesses(hits+misses)
117 system.l2c.ReadReq_accesses::cpu1.inst 87002 # number of ReadReq accesses(hits+misses)
118 system.l2c.ReadReq_accesses::cpu1.data 34142 # number of ReadReq accesses(hits+misses)
119 system.l2c.ReadReq_accesses::total 2083366 # number of ReadReq accesses(hits+misses)
120 system.l2c.Writeback_accesses::writebacks 816294 # number of Writeback accesses(hits+misses)
121 system.l2c.Writeback_accesses::total 816294 # number of Writeback accesses(hits+misses)
122 system.l2c.UpgradeReq_accesses::cpu0.data 2625 # number of UpgradeReq accesses(hits+misses)
123 system.l2c.UpgradeReq_accesses::cpu1.data 548 # number of UpgradeReq accesses(hits+misses)
124 system.l2c.UpgradeReq_accesses::total 3173 # number of UpgradeReq accesses(hits+misses)
125 system.l2c.SCUpgradeReq_accesses::cpu0.data 33 # number of SCUpgradeReq accesses(hits+misses)
126 system.l2c.SCUpgradeReq_accesses::cpu1.data 93 # number of SCUpgradeReq accesses(hits+misses)
127 system.l2c.SCUpgradeReq_accesses::total 126 # number of SCUpgradeReq accesses(hits+misses)
128 system.l2c.ReadExReq_accesses::cpu0.data 287834 # number of ReadExReq accesses(hits+misses)
129 system.l2c.ReadExReq_accesses::cpu1.data 18765 # number of ReadExReq accesses(hits+misses)
130 system.l2c.ReadExReq_accesses::total 306599 # number of ReadExReq accesses(hits+misses)
131 system.l2c.demand_accesses::cpu0.inst 915760 # number of demand (read+write) accesses
132 system.l2c.demand_accesses::cpu0.data 1334296 # number of demand (read+write) accesses
133 system.l2c.demand_accesses::cpu1.inst 87002 # number of demand (read+write) accesses
134 system.l2c.demand_accesses::cpu1.data 52907 # number of demand (read+write) accesses
135 system.l2c.demand_accesses::total 2389965 # number of demand (read+write) accesses
136 system.l2c.overall_accesses::cpu0.inst 915760 # number of overall (read+write) accesses
137 system.l2c.overall_accesses::cpu0.data 1334296 # number of overall (read+write) accesses
138 system.l2c.overall_accesses::cpu1.inst 87002 # number of overall (read+write) accesses
139 system.l2c.overall_accesses::cpu1.data 52907 # number of overall (read+write) accesses
140 system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses
141 system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # miss rate for ReadReq accesses
142 system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses
143 system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses
144 system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses
145 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses
146 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses
147 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses
148 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses
149 system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses
150 system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses
151 system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses
152 system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses
153 system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses
154 system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses
155 system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses
156 system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses
157 system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses
158 system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses
159 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency
160 system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency
161 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency
162 system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency
163 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency
164 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency
165 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency
166 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency
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168 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency
169 system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency
170 system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency
171 system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency
172 system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency
173 system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency
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176 system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency
177 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
178 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
179 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
180 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
181 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
182 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
183 system.l2c.fast_writes 0 # number of fast writes performed
184 system.l2c.cache_copies 0 # number of cache copies performed
185 system.l2c.writebacks::writebacks 119935 # number of writebacks
186 system.l2c.writebacks::total 119935 # number of writebacks
187 system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits
188 system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
189 system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
190 system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
191 system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
192 system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
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196 system.l2c.ReadReq_mshr_misses::cpu1.data 1138 # number of ReadReq MSHR misses
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199 system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses
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202 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 74 # number of SCUpgradeReq MSHR misses
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216 system.l2c.overall_mshr_misses::total 428511 # number of overall MSHR misses
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220 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45568000 # number of ReadReq MSHR miss cycles
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223 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19800000 # number of UpgradeReq MSHR miss cycles
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226 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2960000 # number of SCUpgradeReq MSHR miss cycles
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233 system.l2c.demand_mshr_miss_latency::cpu1.inst 32164000 # number of demand (read+write) MSHR miss cycles
234 system.l2c.demand_mshr_miss_latency::cpu1.data 293413000 # number of demand (read+write) MSHR miss cycles
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236 system.l2c.overall_mshr_miss_latency::cpu0.inst 574888000 # number of overall MSHR miss cycles
237 system.l2c.overall_mshr_miss_latency::cpu0.data 16245364000 # number of overall MSHR miss cycles
238 system.l2c.overall_mshr_miss_latency::cpu1.inst 32164000 # number of overall MSHR miss cycles
239 system.l2c.overall_mshr_miss_latency::cpu1.data 293413000 # number of overall MSHR miss cycles
240 system.l2c.overall_mshr_miss_latency::total 17145829000 # number of overall MSHR miss cycles
241 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 792100000 # number of ReadReq MSHR uncacheable cycles
242 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 10214500 # number of ReadReq MSHR uncacheable cycles
243 system.l2c.ReadReq_mshr_uncacheable_latency::total 802314500 # number of ReadReq MSHR uncacheable cycles
244 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1122200000 # number of WriteReq MSHR uncacheable cycles
245 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 269211500 # number of WriteReq MSHR uncacheable cycles
246 system.l2c.WriteReq_mshr_uncacheable_latency::total 1391411500 # number of WriteReq MSHR uncacheable cycles
247 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914300000 # number of overall MSHR uncacheable cycles
248 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279426000 # number of overall MSHR uncacheable cycles
249 system.l2c.overall_mshr_uncacheable_latency::total 2193726000 # number of overall MSHR uncacheable cycles
250 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for ReadReq accesses
251 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses
252 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses
253 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses
254 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses
255 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses
256 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses
257 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses
258 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses
259 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses
260 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses
261 system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses
262 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses
263 system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses
264 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses
265 system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses
266 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses
267 system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses
268 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency
269 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency
270 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency
271 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency
272 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency
273 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
274 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency
275 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency
276 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency
277 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency
278 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency
279 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency
280 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency
281 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency
282 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency
283 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency
284 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency
285 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency
286 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
287 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
288 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
289 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
290 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
291 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
292 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
293 system.iocache.replacements 41694 # number of replacements
294 system.iocache.tagsinuse 0.563721 # Cycle average of tags in use
295 system.iocache.total_refs 0 # Total number of references to valid blocks.
296 system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
297 system.iocache.avg_refs 0 # Average number of references to valid blocks.
298 system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit.
299 system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor
300 system.iocache.occ_percent::tsunami.ide 0.035233 # Average percentage of cache occupancy
301 system.iocache.occ_percent::total 0.035233 # Average percentage of cache occupancy
302 system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
303 system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
304 system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
305 system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
306 system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
307 system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
308 system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
309 system.iocache.overall_misses::total 41726 # number of overall misses
310 system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles
311 system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles
312 system.iocache.WriteReq_miss_latency::tsunami.ide 5721783806 # number of WriteReq miss cycles
313 system.iocache.WriteReq_miss_latency::total 5721783806 # number of WriteReq miss cycles
314 system.iocache.demand_miss_latency::tsunami.ide 5741836804 # number of demand (read+write) miss cycles
315 system.iocache.demand_miss_latency::total 5741836804 # number of demand (read+write) miss cycles
316 system.iocache.overall_miss_latency::tsunami.ide 5741836804 # number of overall miss cycles
317 system.iocache.overall_miss_latency::total 5741836804 # number of overall miss cycles
318 system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
319 system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
320 system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
321 system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
322 system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
323 system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
324 system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
325 system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
326 system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
327 system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
328 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
329 system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
330 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency
331 system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency
332 system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency
333 system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency
334 system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked
335 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
336 system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked
337 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
338 system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked
339 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
340 system.iocache.fast_writes 0 # number of fast writes performed
341 system.iocache.cache_copies 0 # number of cache copies performed
342 system.iocache.writebacks::writebacks 41520 # number of writebacks
343 system.iocache.writebacks::total 41520 # number of writebacks
344 system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
345 system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
346 system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
347 system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
348 system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
349 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
350 system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
351 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
352 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles
353 system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles
354 system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles
355 system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles
356 system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles
357 system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles
358 system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles
359 system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles
360 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
361 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
362 system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
363 system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
364 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency
365 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency
366 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency
367 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency
368 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
369 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
370 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
371 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
372 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
373 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
374 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
375 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
376 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
377 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
378 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
379 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
380 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
381 system.cpu0.dtb.fetch_hits 0 # ITB hits
382 system.cpu0.dtb.fetch_misses 0 # ITB misses
383 system.cpu0.dtb.fetch_acv 0 # ITB acv
384 system.cpu0.dtb.fetch_accesses 0 # ITB accesses
385 system.cpu0.dtb.read_hits 8633623 # DTB read hits
386 system.cpu0.dtb.read_misses 7443 # DTB read misses
387 system.cpu0.dtb.read_acv 210 # DTB read access violations
388 system.cpu0.dtb.read_accesses 490673 # DTB read accesses
389 system.cpu0.dtb.write_hits 6044743 # DTB write hits
390 system.cpu0.dtb.write_misses 813 # DTB write misses
391 system.cpu0.dtb.write_acv 134 # DTB write access violations
392 system.cpu0.dtb.write_accesses 187452 # DTB write accesses
393 system.cpu0.dtb.data_hits 14678366 # DTB hits
394 system.cpu0.dtb.data_misses 8256 # DTB misses
395 system.cpu0.dtb.data_acv 344 # DTB access violations
396 system.cpu0.dtb.data_accesses 678125 # DTB accesses
397 system.cpu0.itb.fetch_hits 3853057 # ITB hits
398 system.cpu0.itb.fetch_misses 3871 # ITB misses
399 system.cpu0.itb.fetch_acv 184 # ITB acv
400 system.cpu0.itb.fetch_accesses 3856928 # ITB accesses
401 system.cpu0.itb.read_hits 0 # DTB read hits
402 system.cpu0.itb.read_misses 0 # DTB read misses
403 system.cpu0.itb.read_acv 0 # DTB read access violations
404 system.cpu0.itb.read_accesses 0 # DTB read accesses
405 system.cpu0.itb.write_hits 0 # DTB write hits
406 system.cpu0.itb.write_misses 0 # DTB write misses
407 system.cpu0.itb.write_acv 0 # DTB write access violations
408 system.cpu0.itb.write_accesses 0 # DTB write accesses
409 system.cpu0.itb.data_hits 0 # DTB hits
410 system.cpu0.itb.data_misses 0 # DTB misses
411 system.cpu0.itb.data_acv 0 # DTB access violations
412 system.cpu0.itb.data_accesses 0 # DTB accesses
413 system.cpu0.numCycles 3916023774 # number of cpu cycles simulated
414 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
415 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
416 system.cpu0.committedInsts 54072652 # Number of instructions committed
417 system.cpu0.committedOps 54072652 # Number of ops (including micro ops) committed
418 system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses
419 system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses
420 system.cpu0.num_func_calls 1426863 # number of times a function call or return occured
421 system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls
422 system.cpu0.num_int_insts 50043234 # number of integer instructions
423 system.cpu0.num_fp_insts 293967 # number of float instructions
424 system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read
425 system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written
426 system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read
427 system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written
428 system.cpu0.num_mem_refs 14724357 # number of memory refs
429 system.cpu0.num_load_insts 8664914 # Number of load instructions
430 system.cpu0.num_store_insts 6059443 # Number of store instructions
431 system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles
432 system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles
433 system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles
434 system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles
435 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
436 system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed
437 system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed
438 system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl
439 system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
440 system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
441 system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
442 system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl
443 system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl
444 system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl
445 system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
446 system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
447 system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
448 system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl
449 system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl
450 system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl
451 system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl
452 system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl
453 system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl
454 system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl
455 system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl
456 system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl
457 system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
458 system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
459 system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
460 system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl
461 system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
462 system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
463 system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
464 system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
465 system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
466 system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
467 system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
468 system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
469 system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
470 system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
471 system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
472 system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
473 system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
474 system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
475 system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
476 system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
477 system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
478 system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
479 system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
480 system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
481 system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
482 system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
483 system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
484 system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
485 system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
486 system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
487 system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
488 system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
489 system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
490 system.cpu0.kern.syscall::total 222 # number of syscalls executed
491 system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
492 system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
493 system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
494 system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
495 system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
496 system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed
497 system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
498 system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
499 system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed
500 system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed
501 system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
502 system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed
503 system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
504 system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
505 system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
506 system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
507 system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
508 system.cpu0.kern.callpal::total 188203 # number of callpals executed
509 system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches
510 system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
511 system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
512 system.cpu0.kern.mode_good::kernel 1283
513 system.cpu0.kern.mode_good::user 1283
514 system.cpu0.kern.mode_good::idle 0
515 system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches
516 system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
517 system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
518 system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches
519 system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode
520 system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode
521 system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
522 system.cpu0.kern.swap_context 3895 # number of times the context was actually changed
523 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
524 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
525 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
526 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
527 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
528 system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
529 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
530 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
531 system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
532 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
533 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
534 system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
535 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
536 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
537 system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
538 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
539 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
540 system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
541 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
542 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
543 system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
544 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
545 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
546 system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
547 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
548 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
549 system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
550 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
551 system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
552 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
553 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
554 system.cpu0.icache.replacements 915147 # number of replacements
555 system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use
556 system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks.
557 system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks.
558 system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks.
559 system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit.
560 system.cpu0.icache.occ_blocks::cpu0.inst 508.800486 # Average occupied blocks per requestor
561 system.cpu0.icache.occ_percent::cpu0.inst 0.993751 # Average percentage of cache occupancy
562 system.cpu0.icache.occ_percent::total 0.993751 # Average percentage of cache occupancy
563 system.cpu0.icache.ReadReq_hits::cpu0.inst 53165471 # number of ReadReq hits
564 system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits
565 system.cpu0.icache.demand_hits::cpu0.inst 53165471 # number of demand (read+write) hits
566 system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits
567 system.cpu0.icache.overall_hits::cpu0.inst 53165471 # number of overall hits
568 system.cpu0.icache.overall_hits::total 53165471 # number of overall hits
569 system.cpu0.icache.ReadReq_misses::cpu0.inst 915781 # number of ReadReq misses
570 system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses
571 system.cpu0.icache.demand_misses::cpu0.inst 915781 # number of demand (read+write) misses
572 system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses
573 system.cpu0.icache.overall_misses::cpu0.inst 915781 # number of overall misses
574 system.cpu0.icache.overall_misses::total 915781 # number of overall misses
575 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13429132500 # number of ReadReq miss cycles
576 system.cpu0.icache.ReadReq_miss_latency::total 13429132500 # number of ReadReq miss cycles
577 system.cpu0.icache.demand_miss_latency::cpu0.inst 13429132500 # number of demand (read+write) miss cycles
578 system.cpu0.icache.demand_miss_latency::total 13429132500 # number of demand (read+write) miss cycles
579 system.cpu0.icache.overall_miss_latency::cpu0.inst 13429132500 # number of overall miss cycles
580 system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles
581 system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses)
582 system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses)
583 system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses
584 system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses
585 system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses
586 system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses
587 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses
588 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses
589 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses
590 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency
591 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency
592 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency
593 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
594 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
595 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
596 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
597 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
598 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
599 system.cpu0.icache.fast_writes 0 # number of fast writes performed
600 system.cpu0.icache.cache_copies 0 # number of cache copies performed
601 system.cpu0.icache.writebacks::writebacks 55 # number of writebacks
602 system.cpu0.icache.writebacks::total 55 # number of writebacks
603 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses
604 system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses
605 system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses
606 system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses
607 system.cpu0.icache.overall_mshr_misses::cpu0.inst 915781 # number of overall MSHR misses
608 system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses
609 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles
610 system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles
611 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles
612 system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles
613 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles
614 system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles
615 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses
616 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses
617 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses
618 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency
619 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency
620 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency
621 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
622 system.cpu0.dcache.replacements 1338438 # number of replacements
623 system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use
624 system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks.
625 system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks.
626 system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks.
627 system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit.
628 system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor
629 system.cpu0.dcache.occ_percent::cpu0.data 0.983447 # Average percentage of cache occupancy
630 system.cpu0.dcache.occ_percent::total 0.983447 # Average percentage of cache occupancy
631 system.cpu0.dcache.ReadReq_hits::cpu0.data 7421006 # number of ReadReq hits
632 system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits
633 system.cpu0.dcache.WriteReq_hits::cpu0.data 5560133 # number of WriteReq hits
634 system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits
635 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176505 # number of LoadLockedReq hits
636 system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits
637 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191674 # number of StoreCondReq hits
638 system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits
639 system.cpu0.dcache.demand_hits::cpu0.data 12981139 # number of demand (read+write) hits
640 system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits
641 system.cpu0.dcache.overall_hits::cpu0.data 12981139 # number of overall hits
642 system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits
643 system.cpu0.dcache.ReadReq_misses::cpu0.data 1036101 # number of ReadReq misses
644 system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses
645 system.cpu0.dcache.WriteReq_misses::cpu0.data 291536 # number of WriteReq misses
646 system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses
647 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16544 # number of LoadLockedReq misses
648 system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses
649 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 410 # number of StoreCondReq misses
650 system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses
651 system.cpu0.dcache.demand_misses::cpu0.data 1327637 # number of demand (read+write) misses
652 system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses
653 system.cpu0.dcache.overall_misses::cpu0.data 1327637 # number of overall misses
654 system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses
655 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26570279500 # number of ReadReq miss cycles
656 system.cpu0.dcache.ReadReq_miss_latency::total 26570279500 # number of ReadReq miss cycles
657 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9109954000 # number of WriteReq miss cycles
658 system.cpu0.dcache.WriteReq_miss_latency::total 9109954000 # number of WriteReq miss cycles
659 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234949000 # number of LoadLockedReq miss cycles
660 system.cpu0.dcache.LoadLockedReq_miss_latency::total 234949000 # number of LoadLockedReq miss cycles
661 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2973000 # number of StoreCondReq miss cycles
662 system.cpu0.dcache.StoreCondReq_miss_latency::total 2973000 # number of StoreCondReq miss cycles
663 system.cpu0.dcache.demand_miss_latency::cpu0.data 35680233500 # number of demand (read+write) miss cycles
664 system.cpu0.dcache.demand_miss_latency::total 35680233500 # number of demand (read+write) miss cycles
665 system.cpu0.dcache.overall_miss_latency::cpu0.data 35680233500 # number of overall miss cycles
666 system.cpu0.dcache.overall_miss_latency::total 35680233500 # number of overall miss cycles
667 system.cpu0.dcache.ReadReq_accesses::cpu0.data 8457107 # number of ReadReq accesses(hits+misses)
668 system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses)
669 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851669 # number of WriteReq accesses(hits+misses)
670 system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses)
671 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193049 # number of LoadLockedReq accesses(hits+misses)
672 system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses)
673 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses)
674 system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses)
675 system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses
676 system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses
677 system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses
678 system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses
679 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses
680 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses
681 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses
682 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses
683 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses
684 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses
685 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency
686 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency
687 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency
688 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency
689 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency
690 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency
691 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
698 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
699 system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks
700 system.cpu0.dcache.writebacks::total 786441 # number of writebacks
701 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses
702 system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses
703 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses
704 system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses
705 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16544 # number of LoadLockedReq MSHR misses
706 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16544 # number of LoadLockedReq MSHR misses
707 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 410 # number of StoreCondReq MSHR misses
708 system.cpu0.dcache.StoreCondReq_mshr_misses::total 410 # number of StoreCondReq MSHR misses
709 system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327637 # number of demand (read+write) MSHR misses
710 system.cpu0.dcache.demand_mshr_misses::total 1327637 # number of demand (read+write) MSHR misses
711 system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327637 # number of overall MSHR misses
712 system.cpu0.dcache.overall_mshr_misses::total 1327637 # number of overall MSHR misses
713 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23461938500 # number of ReadReq MSHR miss cycles
714 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23461938500 # number of ReadReq MSHR miss cycles
715 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8235346000 # number of WriteReq MSHR miss cycles
716 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8235346000 # number of WriteReq MSHR miss cycles
717 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185317000 # number of LoadLockedReq MSHR miss cycles
718 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185317000 # number of LoadLockedReq MSHR miss cycles
719 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1743000 # number of StoreCondReq MSHR miss cycles
720 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1743000 # number of StoreCondReq MSHR miss cycles
721 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31697284500 # number of demand (read+write) MSHR miss cycles
722 system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles
723 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31697284500 # number of overall MSHR miss cycles
724 system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles
725 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles
726 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles
727 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles
728 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles
729 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles
730 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles
731 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses
732 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses
733 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses
734 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses
735 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses
736 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses
737 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency
738 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency
739 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency
740 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency
741 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency
742 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency
743 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
744 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
745 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
746 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
747 system.cpu1.dtb.fetch_hits 0 # ITB hits
748 system.cpu1.dtb.fetch_misses 0 # ITB misses
749 system.cpu1.dtb.fetch_acv 0 # ITB acv
750 system.cpu1.dtb.fetch_accesses 0 # ITB accesses
751 system.cpu1.dtb.read_hits 1050117 # DTB read hits
752 system.cpu1.dtb.read_misses 2992 # DTB read misses
753 system.cpu1.dtb.read_acv 0 # DTB read access violations
754 system.cpu1.dtb.read_accesses 239363 # DTB read accesses
755 system.cpu1.dtb.write_hits 651208 # DTB write hits
756 system.cpu1.dtb.write_misses 341 # DTB write misses
757 system.cpu1.dtb.write_acv 29 # DTB write access violations
758 system.cpu1.dtb.write_accesses 105247 # DTB write accesses
759 system.cpu1.dtb.data_hits 1701325 # DTB hits
760 system.cpu1.dtb.data_misses 3333 # DTB misses
761 system.cpu1.dtb.data_acv 29 # DTB access violations
762 system.cpu1.dtb.data_accesses 344610 # DTB accesses
763 system.cpu1.itb.fetch_hits 1493438 # ITB hits
764 system.cpu1.itb.fetch_misses 1216 # ITB misses
765 system.cpu1.itb.fetch_acv 0 # ITB acv
766 system.cpu1.itb.fetch_accesses 1494654 # ITB accesses
767 system.cpu1.itb.read_hits 0 # DTB read hits
768 system.cpu1.itb.read_misses 0 # DTB read misses
769 system.cpu1.itb.read_acv 0 # DTB read access violations
770 system.cpu1.itb.read_accesses 0 # DTB read accesses
771 system.cpu1.itb.write_hits 0 # DTB write hits
772 system.cpu1.itb.write_misses 0 # DTB write misses
773 system.cpu1.itb.write_acv 0 # DTB write access violations
774 system.cpu1.itb.write_accesses 0 # DTB write accesses
775 system.cpu1.itb.data_hits 0 # DTB hits
776 system.cpu1.itb.data_misses 0 # DTB misses
777 system.cpu1.itb.data_acv 0 # DTB access violations
778 system.cpu1.itb.data_accesses 0 # DTB accesses
779 system.cpu1.numCycles 3917294190 # number of cpu cycles simulated
780 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
781 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
782 system.cpu1.committedInsts 5282991 # Number of instructions committed
783 system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed
784 system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses
785 system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
786 system.cpu1.num_func_calls 158031 # number of times a function call or return occured
787 system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls
788 system.cpu1.num_int_insts 4948310 # number of integer instructions
789 system.cpu1.num_fp_insts 34031 # number of float instructions
790 system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read
791 system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written
792 system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
793 system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
794 system.cpu1.num_mem_refs 1710778 # number of memory refs
795 system.cpu1.num_load_insts 1056124 # Number of load instructions
796 system.cpu1.num_store_insts 654654 # Number of store instructions
797 system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles
798 system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles
799 system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles
800 system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles
801 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
802 system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed
803 system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed
804 system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl
805 system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl
806 system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl
807 system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl
808 system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl
809 system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl
810 system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl
811 system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl
812 system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl
813 system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl
814 system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl
815 system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl
816 system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl
817 system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl
818 system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl
819 system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl
820 system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
821 system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
822 system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl
823 system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
824 system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
825 system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
826 system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
827 system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
828 system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
829 system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
830 system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
831 system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
832 system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
833 system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
834 system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
835 system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
836 system.cpu1.kern.syscall::total 104 # number of syscalls executed
837 system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
838 system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
839 system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
840 system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
841 system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed
842 system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed
843 system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed
844 system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed
845 system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed
846 system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed
847 system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed
848 system.cpu1.kern.callpal::whami 3 0.01% 90.83% # number of callpals executed
849 system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # number of callpals executed
850 system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed
851 system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
852 system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
853 system.cpu1.kern.callpal::total 29554 # number of callpals executed
854 system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches
855 system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
856 system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches
857 system.cpu1.kern.mode_good::kernel 477
858 system.cpu1.kern.mode_good::user 464
859 system.cpu1.kern.mode_good::idle 13
860 system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches
861 system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
862 system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches
863 system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches
864 system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode
865 system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode
866 system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode
867 system.cpu1.kern.swap_context 338 # number of times the context was actually changed
868 system.cpu1.icache.replacements 86457 # number of replacements
869 system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use
870 system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks.
871 system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks.
872 system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks.
873 system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit.
874 system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor
875 system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy
876 system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy
877 system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits
878 system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits
879 system.cpu1.icache.demand_hits::cpu1.inst 5199349 # number of demand (read+write) hits
880 system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits
881 system.cpu1.icache.overall_hits::cpu1.inst 5199349 # number of overall hits
882 system.cpu1.icache.overall_hits::total 5199349 # number of overall hits
883 system.cpu1.icache.ReadReq_misses::cpu1.inst 87005 # number of ReadReq misses
884 system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses
885 system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses
886 system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses
887 system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses
888 system.cpu1.icache.overall_misses::total 87005 # number of overall misses
889 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1260607500 # number of ReadReq miss cycles
890 system.cpu1.icache.ReadReq_miss_latency::total 1260607500 # number of ReadReq miss cycles
891 system.cpu1.icache.demand_miss_latency::cpu1.inst 1260607500 # number of demand (read+write) miss cycles
892 system.cpu1.icache.demand_miss_latency::total 1260607500 # number of demand (read+write) miss cycles
893 system.cpu1.icache.overall_miss_latency::cpu1.inst 1260607500 # number of overall miss cycles
894 system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles
895 system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses)
896 system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses)
897 system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses
898 system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses
899 system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses
900 system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses
901 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses
902 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses
903 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses
904 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency
905 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency
906 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency
907 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
908 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
909 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
910 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
911 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
912 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
913 system.cpu1.icache.fast_writes 0 # number of fast writes performed
914 system.cpu1.icache.cache_copies 0 # number of cache copies performed
915 system.cpu1.icache.writebacks::writebacks 14 # number of writebacks
916 system.cpu1.icache.writebacks::total 14 # number of writebacks
917 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses
918 system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses
919 system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses
920 system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses
921 system.cpu1.icache.overall_mshr_misses::cpu1.inst 87005 # number of overall MSHR misses
922 system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses
923 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles
924 system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles
925 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles
926 system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles
927 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles
928 system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles
929 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses
930 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses
931 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses
932 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency
933 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency
934 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency
935 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
936 system.cpu1.dcache.replacements 52960 # number of replacements
937 system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use
938 system.cpu1.dcache.total_refs 1644934 # Total number of references to valid blocks.
939 system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks.
940 system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks.
941 system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit.
942 system.cpu1.dcache.occ_blocks::cpu1.data 389.521271 # Average occupied blocks per requestor
943 system.cpu1.dcache.occ_percent::cpu1.data 0.760784 # Average percentage of cache occupancy
944 system.cpu1.dcache.occ_percent::total 0.760784 # Average percentage of cache occupancy
945 system.cpu1.dcache.ReadReq_hits::cpu1.data 1003161 # number of ReadReq hits
946 system.cpu1.dcache.ReadReq_hits::total 1003161 # number of ReadReq hits
947 system.cpu1.dcache.WriteReq_hits::cpu1.data 616899 # number of WriteReq hits
948 system.cpu1.dcache.WriteReq_hits::total 616899 # number of WriteReq hits
949 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11784 # number of LoadLockedReq hits
950 system.cpu1.dcache.LoadLockedReq_hits::total 11784 # number of LoadLockedReq hits
951 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11526 # number of StoreCondReq hits
952 system.cpu1.dcache.StoreCondReq_hits::total 11526 # number of StoreCondReq hits
953 system.cpu1.dcache.demand_hits::cpu1.data 1620060 # number of demand (read+write) hits
954 system.cpu1.dcache.demand_hits::total 1620060 # number of demand (read+write) hits
955 system.cpu1.dcache.overall_hits::cpu1.data 1620060 # number of overall hits
956 system.cpu1.dcache.overall_hits::total 1620060 # number of overall hits
957 system.cpu1.dcache.ReadReq_misses::cpu1.data 37113 # number of ReadReq misses
958 system.cpu1.dcache.ReadReq_misses::total 37113 # number of ReadReq misses
959 system.cpu1.dcache.WriteReq_misses::cpu1.data 20421 # number of WriteReq misses
960 system.cpu1.dcache.WriteReq_misses::total 20421 # number of WriteReq misses
961 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 982 # number of LoadLockedReq misses
962 system.cpu1.dcache.LoadLockedReq_misses::total 982 # number of LoadLockedReq misses
963 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 505 # number of StoreCondReq misses
964 system.cpu1.dcache.StoreCondReq_misses::total 505 # number of StoreCondReq misses
965 system.cpu1.dcache.demand_misses::cpu1.data 57534 # number of demand (read+write) misses
966 system.cpu1.dcache.demand_misses::total 57534 # number of demand (read+write) misses
967 system.cpu1.dcache.overall_misses::cpu1.data 57534 # number of overall misses
968 system.cpu1.dcache.overall_misses::total 57534 # number of overall misses
969 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 533263000 # number of ReadReq miss cycles
970 system.cpu1.dcache.ReadReq_miss_latency::total 533263000 # number of ReadReq miss cycles
971 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 556796000 # number of WriteReq miss cycles
972 system.cpu1.dcache.WriteReq_miss_latency::total 556796000 # number of WriteReq miss cycles
973 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13079000 # number of LoadLockedReq miss cycles
974 system.cpu1.dcache.LoadLockedReq_miss_latency::total 13079000 # number of LoadLockedReq miss cycles
975 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6416000 # number of StoreCondReq miss cycles
976 system.cpu1.dcache.StoreCondReq_miss_latency::total 6416000 # number of StoreCondReq miss cycles
977 system.cpu1.dcache.demand_miss_latency::cpu1.data 1090059000 # number of demand (read+write) miss cycles
978 system.cpu1.dcache.demand_miss_latency::total 1090059000 # number of demand (read+write) miss cycles
979 system.cpu1.dcache.overall_miss_latency::cpu1.data 1090059000 # number of overall miss cycles
980 system.cpu1.dcache.overall_miss_latency::total 1090059000 # number of overall miss cycles
981 system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040274 # number of ReadReq accesses(hits+misses)
982 system.cpu1.dcache.ReadReq_accesses::total 1040274 # number of ReadReq accesses(hits+misses)
983 system.cpu1.dcache.WriteReq_accesses::cpu1.data 637320 # number of WriteReq accesses(hits+misses)
984 system.cpu1.dcache.WriteReq_accesses::total 637320 # number of WriteReq accesses(hits+misses)
985 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12766 # number of LoadLockedReq accesses(hits+misses)
986 system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses)
987 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12031 # number of StoreCondReq accesses(hits+misses)
988 system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses)
989 system.cpu1.dcache.demand_accesses::cpu1.data 1677594 # number of demand (read+write) accesses
990 system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses
991 system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses
992 system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses
993 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses
994 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses
995 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses
996 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses
997 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses
998 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses
999 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency
1000 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency
1001 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency
1002 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency
1003 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency
1004 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency
1005 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1006 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1007 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1008 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1009 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1010 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1011 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1012 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1013 system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks
1014 system.cpu1.dcache.writebacks::total 29784 # number of writebacks
1015 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses
1016 system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses
1017 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses
1018 system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses
1019 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # number of LoadLockedReq MSHR misses
1020 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 982 # number of LoadLockedReq MSHR misses
1021 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 505 # number of StoreCondReq MSHR misses
1022 system.cpu1.dcache.StoreCondReq_mshr_misses::total 505 # number of StoreCondReq MSHR misses
1023 system.cpu1.dcache.demand_mshr_misses::cpu1.data 57534 # number of demand (read+write) MSHR misses
1024 system.cpu1.dcache.demand_mshr_misses::total 57534 # number of demand (read+write) MSHR misses
1025 system.cpu1.dcache.overall_mshr_misses::cpu1.data 57534 # number of overall MSHR misses
1026 system.cpu1.dcache.overall_mshr_misses::total 57534 # number of overall MSHR misses
1027 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 421922000 # number of ReadReq MSHR miss cycles
1028 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 421922000 # number of ReadReq MSHR miss cycles
1029 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 495533000 # number of WriteReq MSHR miss cycles
1030 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 495533000 # number of WriteReq MSHR miss cycles
1031 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 10133000 # number of LoadLockedReq MSHR miss cycles
1032 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 10133000 # number of LoadLockedReq MSHR miss cycles
1033 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4901000 # number of StoreCondReq MSHR miss cycles
1034 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4901000 # number of StoreCondReq MSHR miss cycles
1035 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 917455000 # number of demand (read+write) MSHR miss cycles
1036 system.cpu1.dcache.demand_mshr_miss_latency::total 917455000 # number of demand (read+write) MSHR miss cycles
1037 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 917455000 # number of overall MSHR miss cycles
1038 system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles
1039 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles
1040 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles
1041 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles
1042 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles
1043 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles
1044 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles
1045 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses
1046 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses
1047 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses
1048 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses
1049 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses
1050 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses
1051 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency
1052 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency
1053 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency
1054 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency
1055 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency
1056 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency
1057 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1058 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1059 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1060 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1062 ---------- End Simulation Statistics ----------
projects / gem5.git / blob