2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.783855 # Number of seconds simulated
4 sim_ticks 2783854535000 # Number of ticks simulated
5 final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1211130 # Simulator instruction rate (inst/s)
8 host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 23615387886 # Simulator tick rate (ticks/s)
10 host_mem_usage 581436 # Number of bytes of host memory used
11 host_seconds 117.88 # Real time elapsed on the host
12 sim_insts 142771651 # Number of instructions simulated
13 sim_ops 173801592 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory
20 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
27 system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory
31 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
34 system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s)
54 system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
55 system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
56 system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
57 system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
58 system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
59 system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
60 system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
61 system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
62 system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
63 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
64 system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
65 system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
66 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
67 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
68 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
69 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
70 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
71 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
72 system.cpu_clk_domain.clock 500 # Clock period in ticks
73 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
74 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
75 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
76 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
77 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
78 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
79 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
80 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
81 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
82 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
83 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
84 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
85 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
86 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
87 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
88 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
89 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
90 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
91 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
92 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
93 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
94 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
95 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
96 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
97 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
98 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
99 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
100 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
101 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
102 system.cpu.dtb.walker.walks 10028 # Table walker walks requested
103 system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
104 system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
105 system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
106 system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
107 system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
108 system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
109 system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
110 system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated
111 system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
112 system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated
113 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst
114 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
115 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
116 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
117 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
118 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
119 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
120 system.cpu.dtb.inst_hits 0 # ITB inst hits
121 system.cpu.dtb.inst_misses 0 # ITB inst misses
122 system.cpu.dtb.read_hits 31525949 # DTB read hits
123 system.cpu.dtb.read_misses 8580 # DTB read misses
124 system.cpu.dtb.write_hits 23124104 # DTB write hits
125 system.cpu.dtb.write_misses 1448 # DTB write misses
126 system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
127 system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
128 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
129 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
130 system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
131 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
132 system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
133 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
134 system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
135 system.cpu.dtb.read_accesses 31534529 # DTB read accesses
136 system.cpu.dtb.write_accesses 23125552 # DTB write accesses
137 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
138 system.cpu.dtb.hits 54650053 # DTB hits
139 system.cpu.dtb.misses 10028 # DTB misses
140 system.cpu.dtb.accesses 54660081 # DTB accesses
141 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
142 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
143 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
144 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
145 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
146 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
147 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
148 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
149 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
150 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
151 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
152 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
153 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
154 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
155 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
156 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
157 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
158 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
159 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
160 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
161 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
162 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
163 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
164 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
165 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
166 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
167 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
168 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
169 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
170 system.cpu.itb.walker.walks 4762 # Table walker walks requested
171 system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
172 system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
173 system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
174 system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
175 system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
176 system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
177 system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
178 system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
179 system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
180 system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
181 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
182 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
183 system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
184 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
185 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
186 system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
187 system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
188 system.cpu.itb.inst_hits 147038166 # ITB inst hits
189 system.cpu.itb.inst_misses 4762 # ITB inst misses
190 system.cpu.itb.read_hits 0 # DTB read hits
191 system.cpu.itb.read_misses 0 # DTB read misses
192 system.cpu.itb.write_hits 0 # DTB write hits
193 system.cpu.itb.write_misses 0 # DTB write misses
194 system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
195 system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
196 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
197 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
198 system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
199 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
200 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
201 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
202 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
203 system.cpu.itb.read_accesses 0 # DTB read accesses
204 system.cpu.itb.write_accesses 0 # DTB write accesses
205 system.cpu.itb.inst_accesses 147042928 # ITB inst accesses
206 system.cpu.itb.hits 147038166 # DTB hits
207 system.cpu.itb.misses 4762 # DTB misses
208 system.cpu.itb.accesses 147042928 # DTB accesses
209 system.cpu.numCycles 5567712151 # number of cpu cycles simulated
210 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
211 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
212 system.cpu.kern.inst.arm 0 # number of arm instructions executed
213 system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
214 system.cpu.committedInsts 142771651 # Number of instructions committed
215 system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed
216 system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses
217 system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
218 system.cpu.num_func_calls 16873962 # number of times a function call or return occured
219 system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls
220 system.cpu.num_int_insts 153161279 # number of integer instructions
221 system.cpu.num_fp_insts 11484 # number of float instructions
222 system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read
223 system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written
224 system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
225 system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
226 system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read
227 system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written
228 system.cpu.num_mem_refs 55938616 # number of memory refs
229 system.cpu.num_load_insts 31855585 # Number of load instructions
230 system.cpu.num_store_insts 24083031 # Number of store instructions
231 system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles
232 system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles
233 system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
234 system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
235 system.cpu.Branches 36396978 # Number of branches fetched
236 system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
237 system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction
238 system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
239 system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
240 system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
241 system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
242 system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
243 system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
244 system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction
245 system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction
246 system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction
247 system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction
248 system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction
249 system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction
250 system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction
251 system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction
252 system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction
253 system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction
254 system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction
255 system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction
256 system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction
257 system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction
258 system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
259 system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
260 system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
261 system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
262 system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
263 system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
264 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
265 system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
266 system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction
267 system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction
268 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
269 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
270 system.cpu.op_class::total 177218432 # Class of executed instruction
271 system.cpu.dcache.tags.replacements 819392 # number of replacements
272 system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
273 system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks.
274 system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
275 system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks.
276 system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
277 system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
278 system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
279 system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
280 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
281 system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
282 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
283 system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
284 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
285 system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses
286 system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses
287 system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits
288 system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits
289 system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits
290 system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits
291 system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
292 system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
293 system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
294 system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
295 system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
296 system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
297 system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits
298 system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits
299 system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits
300 system.cpu.dcache.overall_hits::total 52863656 # number of overall hits
301 system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses
302 system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses
303 system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
304 system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
305 system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
306 system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
307 system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
308 system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
309 system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
310 system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
311 system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
312 system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
313 system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
314 system.cpu.dcache.overall_misses::total 814065 # number of overall misses
315 system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses)
316 system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses)
317 system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses)
318 system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses)
319 system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
320 system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
321 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
322 system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
323 system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
324 system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
325 system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses
326 system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses
327 system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses
328 system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses
329 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
330 system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
331 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
332 system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
333 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
334 system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
335 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
336 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
337 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
338 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
339 system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
340 system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
341 system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
342 system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
343 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
344 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
345 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
346 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
347 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
348 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
349 system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
350 system.cpu.dcache.writebacks::total 682017 # number of writebacks
351 system.cpu.icache.tags.replacements 1698998 # number of replacements
352 system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
353 system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
354 system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks.
355 system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks.
356 system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
357 system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
358 system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
359 system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
360 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
361 system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
362 system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
363 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
364 system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
365 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
366 system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses
367 system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses
368 system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits
369 system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits
370 system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits
371 system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits
372 system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits
373 system.cpu.icache.overall_hits::total 145341757 # number of overall hits
374 system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses
375 system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses
376 system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses
377 system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses
378 system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses
379 system.cpu.icache.overall_misses::total 1699516 # number of overall misses
380 system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses)
381 system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses)
382 system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses
383 system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses
384 system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses
385 system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses
386 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
387 system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
388 system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
389 system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
390 system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
391 system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
392 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
393 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
394 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
395 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
396 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
397 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
398 system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
399 system.cpu.icache.writebacks::total 1698998 # number of writebacks
400 system.cpu.l2cache.tags.replacements 109913 # number of replacements
401 system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
402 system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
403 system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks.
404 system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks.
405 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
406 system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor
407 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
408 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
409 system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor
410 system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor
411 system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy
412 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
413 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
414 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy
415 system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy
416 system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
417 system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
418 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
419 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
420 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
421 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
422 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
423 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
424 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
425 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
426 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
427 system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses
428 system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses
429 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
430 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
431 system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
432 system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
433 system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
434 system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits
435 system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits
436 system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
437 system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
438 system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits
439 system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits
440 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits
441 system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits
442 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits
443 system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits
444 system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
445 system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
446 system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits
447 system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits
448 system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits
449 system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
450 system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
451 system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits
452 system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits
453 system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits
454 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
455 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
456 system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
457 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
458 system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
459 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
460 system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
461 system.cpu.l2cache.ReadExReq_misses::cpu.data 147776 # number of ReadExReq misses
462 system.cpu.l2cache.ReadExReq_misses::total 147776 # number of ReadExReq misses
463 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
464 system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
465 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses
466 system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses
467 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
468 system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
469 system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses
470 system.cpu.l2cache.demand_misses::cpu.data 163344 # number of demand (read+write) misses
471 system.cpu.l2cache.demand_misses::total 181651 # number of demand (read+write) misses
472 system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
473 system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
474 system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
475 system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses
476 system.cpu.l2cache.overall_misses::total 181651 # number of overall misses
477 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
478 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
479 system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
480 system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
481 system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
482 system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses)
483 system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses)
484 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
485 system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
486 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
487 system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
488 system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
489 system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
490 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses)
491 system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses)
492 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses)
493 system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses)
494 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
495 system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
496 system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses
497 system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
498 system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses
499 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
500 system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
501 system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses
502 system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
503 system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses
504 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
505 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
506 system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
507 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
508 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
509 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
510 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
511 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses
512 system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses
513 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
514 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
515 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
516 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
517 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
518 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
519 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
520 system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses
521 system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses
522 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
523 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
524 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
525 system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses
526 system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses
527 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
528 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
529 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
530 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
531 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
532 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
533 system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
534 system.cpu.l2cache.writebacks::total 101950 # number of writebacks
535 system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter.
536 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data.
537 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
538 system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
539 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
540 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
541 system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
542 system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution
543 system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
544 system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
545 system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
546 system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution
547 system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution
548 system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
549 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
550 system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
551 system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
552 system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
553 system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution
554 system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution
555 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes)
556 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes)
557 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
558 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
559 system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes)
560 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes)
561 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes)
562 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
563 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
564 system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes)
565 system.cpu.toL2Bus.snoops 182975 # Total snoops (count)
566 system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram
567 system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram
568 system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram
569 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
570 system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram
571 system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram
572 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
573 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
574 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
575 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
576 system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram
577 system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
578 system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
579 system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
580 system.iobus.trans_dist::WriteResp 59002 # Transaction distribution
581 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
582 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
583 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
584 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
585 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
586 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
587 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
588 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
589 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
590 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
591 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
592 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
593 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
594 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
595 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
596 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
597 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
598 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
599 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
600 system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
601 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
602 system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
603 system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
604 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
605 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
606 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
607 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
608 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
609 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
610 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
611 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
612 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
613 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
614 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
615 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
616 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
617 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
618 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
619 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
620 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
621 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
622 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
623 system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
624 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
625 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
626 system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
627 system.iocache.tags.replacements 36430 # number of replacements
628 system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
629 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
630 system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
631 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
632 system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
633 system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
634 system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
635 system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
636 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
637 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
638 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
639 system.iocache.tags.tag_accesses 328176 # Number of tag accesses
640 system.iocache.tags.data_accesses 328176 # Number of data accesses
641 system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
642 system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
643 system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
644 system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
645 system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
646 system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
647 system.iocache.overall_misses::realview.ide 36464 # number of overall misses
648 system.iocache.overall_misses::total 36464 # number of overall misses
649 system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
650 system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
651 system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
652 system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
653 system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
654 system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
655 system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
656 system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
657 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
658 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
659 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
660 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
661 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
662 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
663 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
664 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
665 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
666 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
667 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
668 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
669 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
670 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
671 system.iocache.writebacks::writebacks 36190 # number of writebacks
672 system.iocache.writebacks::total 36190 # number of writebacks
673 system.membus.trans_dist::ReadReq 40087 # Transaction distribution
674 system.membus.trans_dist::ReadResp 74202 # Transaction distribution
675 system.membus.trans_dist::WriteReq 27546 # Transaction distribution
676 system.membus.trans_dist::WriteResp 27546 # Transaction distribution
677 system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
678 system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
679 system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
680 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
681 system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
682 system.membus.trans_dist::ReadExReq 145997 # Transaction distribution
683 system.membus.trans_dist::ReadExResp 145997 # Transaction distribution
684 system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
685 system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
686 system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
687 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
688 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
689 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
690 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes)
691 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes)
692 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
693 system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
694 system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes)
695 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
696 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
697 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
698 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes)
699 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes)
700 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
701 system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
702 system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes)
703 system.membus.snoops 0 # Total snoops (count)
704 system.membus.snoop_fanout::samples 434821 # Request fanout histogram
705 system.membus.snoop_fanout::mean 1 # Request fanout histogram
706 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
707 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
708 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
709 system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram
710 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
711 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
712 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
713 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
714 system.membus.snoop_fanout::total 434821 # Request fanout histogram
715 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
716 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
717 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
718 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
719 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
720 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
721 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
722 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
723 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
724 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
725 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
726 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
727 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
728 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
729 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
730 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
731 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
732 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
733 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
734 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
735 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
736 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
737 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
738 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
739 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
740 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
741 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
742 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
743 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
744 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
745 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
746 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
747 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
748 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
749 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
750 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
751 system.realview.ethernet.droppedPackets 0 # number of packets dropped
752 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
753 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
754 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
755 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
757 ---------- End Simulation Statistics ----------
projects / gem5.git / blob