8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/dist/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17 boot_release_addr=65528
19 clk_domain=system.clk_domain
20 dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
21 early_kernel_symbols=false
22 enable_context_switch_stats_dump=false
25 gic_cpu_addr=738205696
26 have_generic_timer=false
27 have_large_asid_64=false
30 have_virtualization=false
31 highest_el_is_64=false
33 kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34 kernel_addr_check=true
35 load_addr_mask=268435455
36 load_offset=2147483648
37 machine_type=VExpress_EMM
39 mem_ranges=2147483648:2415919103
40 memories=system.realview.nvmem system.physmem system.realview.vram
46 readfile=/work/gem5.latest/tests/halt.sh
49 work_begin_ckpt_count=0
50 work_begin_cpu_id_exit=-1
51 work_begin_exit_count=0
52 work_cpus_ckpt_count=0
56 system_port=system.membus.slave[1]
60 clk_domain=system.clk_domain
63 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
66 master=system.iobus.slave[0]
67 slave=system.membus.master[0]
75 image=system.cf0.image
80 child=system.cf0.image.child
86 [system.cf0.image.child]
89 image_file=/dist/disks/linux-aarch32-ael.img
98 voltage_domain=system.voltage_domain
102 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
105 clk_domain=system.cpu_clk_domain
107 do_checkpoint_insts=true
109 do_statistics_insts=true
110 dstage2_mmu=system.cpu0.dstage2_mmu
115 function_trace_start=0
116 interrupts=system.cpu0.interrupts
118 istage2_mmu=system.cpu0.istage2_mmu
120 max_insts_all_threads=0
121 max_insts_any_thread=0
122 max_loads_all_threads=0
123 max_loads_any_thread=0
127 simpoint_start_insts=
128 simulate_data_stalls=false
129 simulate_inst_stalls=false
133 tracer=system.cpu0.tracer
136 dcache_port=system.cpu0.dcache.cpu_side
137 icache_port=system.cpu0.icache.cpu_side
142 addr_ranges=0:18446744073709551615
144 clk_domain=system.cpu_clk_domain
151 prefetch_on_access=false
154 sequential_access=false
157 tags=system.cpu0.dcache.tags
161 cpu_side=system.cpu0.dcache_port
162 mem_side=system.cpu0.toL2Bus.slave[1]
164 [system.cpu0.dcache.tags]
168 clk_domain=system.cpu_clk_domain
171 sequential_access=false
174 [system.cpu0.dstage2_mmu]
178 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
181 [system.cpu0.dstage2_mmu.stage2_tlb]
187 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
189 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
191 clk_domain=system.cpu_clk_domain
194 num_squash_per_cycle=2
196 port=system.cpu0.toL2Bus.slave[5]
204 walker=system.cpu0.dtb.walker
206 [system.cpu0.dtb.walker]
208 clk_domain=system.cpu_clk_domain
211 num_squash_per_cycle=2
213 port=system.cpu0.toL2Bus.slave[3]
218 addr_ranges=0:18446744073709551615
220 clk_domain=system.cpu_clk_domain
227 prefetch_on_access=false
230 sequential_access=false
233 tags=system.cpu0.icache.tags
237 cpu_side=system.cpu0.icache_port
238 mem_side=system.cpu0.toL2Bus.slave[0]
240 [system.cpu0.icache.tags]
244 clk_domain=system.cpu_clk_domain
247 sequential_access=false
250 [system.cpu0.interrupts]
260 id_aa64dfr0_el1=1052678
264 id_aa64mmfr0_el1=15728642
284 [system.cpu0.istage2_mmu]
288 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
291 [system.cpu0.istage2_mmu.stage2_tlb]
297 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
299 [system.cpu0.istage2_mmu.stage2_tlb.walker]
301 clk_domain=system.cpu_clk_domain
304 num_squash_per_cycle=2
306 port=system.cpu0.toL2Bus.slave[4]
314 walker=system.cpu0.itb.walker
316 [system.cpu0.itb.walker]
318 clk_domain=system.cpu_clk_domain
321 num_squash_per_cycle=2
323 port=system.cpu0.toL2Bus.slave[2]
325 [system.cpu0.l2cache]
327 children=prefetcher tags
328 addr_ranges=0:18446744073709551615
330 clk_domain=system.cpu_clk_domain
337 prefetch_on_access=true
338 prefetcher=system.cpu0.l2cache.prefetcher
340 sequential_access=false
343 tags=system.cpu0.l2cache.tags
347 cpu_side=system.cpu0.toL2Bus.master[0]
348 mem_side=system.toL2Bus.slave[0]
350 [system.cpu0.l2cache.prefetcher]
351 type=StridePrefetcher
352 clk_domain=system.cpu_clk_domain
354 data_accesses_only=false
367 [system.cpu0.l2cache.tags]
371 clk_domain=system.cpu_clk_domain
374 sequential_access=false
377 [system.cpu0.toL2Bus]
379 clk_domain=system.cpu_clk_domain
384 use_default_range=false
386 master=system.cpu0.l2cache.cpu_side
387 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
395 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
398 clk_domain=system.cpu_clk_domain
400 do_checkpoint_insts=true
402 do_statistics_insts=true
403 dstage2_mmu=system.cpu1.dstage2_mmu
408 function_trace_start=0
409 interrupts=system.cpu1.interrupts
411 istage2_mmu=system.cpu1.istage2_mmu
413 max_insts_all_threads=0
414 max_insts_any_thread=0
415 max_loads_all_threads=0
416 max_loads_any_thread=0
420 simpoint_start_insts=
421 simulate_data_stalls=false
422 simulate_inst_stalls=false
426 tracer=system.cpu1.tracer
429 dcache_port=system.cpu1.dcache.cpu_side
430 icache_port=system.cpu1.icache.cpu_side
435 addr_ranges=0:18446744073709551615
437 clk_domain=system.cpu_clk_domain
444 prefetch_on_access=false
447 sequential_access=false
450 tags=system.cpu1.dcache.tags
454 cpu_side=system.cpu1.dcache_port
455 mem_side=system.cpu1.toL2Bus.slave[1]
457 [system.cpu1.dcache.tags]
461 clk_domain=system.cpu_clk_domain
464 sequential_access=false
467 [system.cpu1.dstage2_mmu]
471 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
474 [system.cpu1.dstage2_mmu.stage2_tlb]
480 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
482 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
484 clk_domain=system.cpu_clk_domain
487 num_squash_per_cycle=2
489 port=system.cpu1.toL2Bus.slave[5]
497 walker=system.cpu1.dtb.walker
499 [system.cpu1.dtb.walker]
501 clk_domain=system.cpu_clk_domain
504 num_squash_per_cycle=2
506 port=system.cpu1.toL2Bus.slave[3]
511 addr_ranges=0:18446744073709551615
513 clk_domain=system.cpu_clk_domain
520 prefetch_on_access=false
523 sequential_access=false
526 tags=system.cpu1.icache.tags
530 cpu_side=system.cpu1.icache_port
531 mem_side=system.cpu1.toL2Bus.slave[0]
533 [system.cpu1.icache.tags]
537 clk_domain=system.cpu_clk_domain
540 sequential_access=false
543 [system.cpu1.interrupts]
553 id_aa64dfr0_el1=1052678
557 id_aa64mmfr0_el1=15728642
577 [system.cpu1.istage2_mmu]
581 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
584 [system.cpu1.istage2_mmu.stage2_tlb]
590 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
592 [system.cpu1.istage2_mmu.stage2_tlb.walker]
594 clk_domain=system.cpu_clk_domain
597 num_squash_per_cycle=2
599 port=system.cpu1.toL2Bus.slave[4]
607 walker=system.cpu1.itb.walker
609 [system.cpu1.itb.walker]
611 clk_domain=system.cpu_clk_domain
614 num_squash_per_cycle=2
616 port=system.cpu1.toL2Bus.slave[2]
618 [system.cpu1.l2cache]
620 children=prefetcher tags
621 addr_ranges=0:18446744073709551615
623 clk_domain=system.cpu_clk_domain
630 prefetch_on_access=true
631 prefetcher=system.cpu1.l2cache.prefetcher
633 sequential_access=false
636 tags=system.cpu1.l2cache.tags
640 cpu_side=system.cpu1.toL2Bus.master[0]
641 mem_side=system.toL2Bus.slave[1]
643 [system.cpu1.l2cache.prefetcher]
644 type=StridePrefetcher
645 clk_domain=system.cpu_clk_domain
647 data_accesses_only=false
660 [system.cpu1.l2cache.tags]
664 clk_domain=system.cpu_clk_domain
667 sequential_access=false
670 [system.cpu1.toL2Bus]
672 clk_domain=system.cpu_clk_domain
677 use_default_range=false
679 master=system.cpu1.l2cache.cpu_side
680 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
686 [system.cpu_clk_domain]
692 voltage_domain=system.voltage_domain
694 [system.dvfs_handler]
699 sys_clk_domain=system.clk_domain
700 transition_latency=100000000
709 clk_domain=system.clk_domain
712 use_default_range=true
714 default=system.realview.pciconfig.pio
715 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
716 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
721 addr_ranges=2147483648:2415919103
723 clk_domain=system.clk_domain
730 prefetch_on_access=false
733 sequential_access=false
736 tags=system.iocache.tags
740 cpu_side=system.iobus.master[27]
741 mem_side=system.membus.slave[3]
743 [system.iocache.tags]
747 clk_domain=system.clk_domain
750 sequential_access=false
756 addr_ranges=0:18446744073709551615
758 clk_domain=system.cpu_clk_domain
765 prefetch_on_access=false
768 sequential_access=false
775 cpu_side=system.toL2Bus.master[0]
776 mem_side=system.membus.slave[2]
782 clk_domain=system.cpu_clk_domain
785 sequential_access=false
790 children=badaddr_responder
791 clk_domain=system.clk_domain
796 use_default_range=false
798 default=system.membus.badaddr_responder.pio
799 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
800 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
802 [system.membus.badaddr_responder]
804 clk_domain=system.clk_domain
812 ret_data32=4294967295
813 ret_data64=18446744073709551615
818 pio=system.membus.default
823 clk_domain=system.clk_domain
824 conf_table_reported=true
830 range=2147483648:2415919103
831 port=system.membus.master[5]
835 children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
837 intrctrl=system.intrctrl
838 pci_cfg_base=805306368
839 pci_cfg_gen_offsets=false
843 [system.realview.aaci_fake]
846 clk_domain=system.clk_domain
852 pio=system.iobus.master[18]
854 [system.realview.cf_ctrl]
894 MSICAPNextCapability=0
898 MSIXCAPNextCapability=0
908 PMCAPNextCapability=0
913 PXCAPDevCapabilities=0
920 PXCAPNextCapability=0
928 clk_domain=system.clk_domain
938 platform=system.realview
940 config=system.iobus.master[9]
941 dma=system.iobus.slave[2]
942 pio=system.iobus.master[8]
944 [system.realview.clcd]
947 clk_domain=system.clk_domain
950 gic=system.realview.gic
957 dma=system.iobus.slave[1]
958 pio=system.iobus.master[4]
960 [system.realview.energy_ctrl]
962 clk_domain=system.clk_domain
963 dvfs_handler=system.dvfs_handler
968 pio=system.iobus.master[22]
970 [system.realview.ethernet]
1009 MSICAPMsgUpperAddr=0
1010 MSICAPNextCapability=0
1014 MSIXCAPNextCapability=0
1024 PMCAPNextCapability=0
1029 PXCAPDevCapabilities=0
1036 PXCAPNextCapability=0
1042 SubsystemVendorID=32902
1044 clk_domain=system.clk_domain
1045 config_latency=20000
1047 fetch_comp_delay=10000
1049 hardware_address=00:90:00:00:00:01
1056 platform=system.realview
1057 rx_desc_cache_size=64
1061 tx_desc_cache_size=64
1066 config=system.iobus.master[26]
1067 dma=system.iobus.slave[4]
1068 pio=system.iobus.master[25]
1070 [system.realview.generic_timer]
1073 gic=system.realview.gic
1077 [system.realview.gic]
1079 clk_domain=system.clk_domain
1083 dist_pio_delay=10000
1088 platform=system.realview
1090 pio=system.membus.master[2]
1092 [system.realview.hdlcd]
1095 clk_domain=system.clk_domain
1098 gic=system.realview.gic
1104 vnc=system.vncserver
1105 dma=system.membus.slave[0]
1106 pio=system.iobus.master[5]
1108 [system.realview.ide]
1147 MSICAPMsgUpperAddr=0
1148 MSICAPNextCapability=0
1152 MSIXCAPNextCapability=0
1162 PMCAPNextCapability=0
1167 PXCAPDevCapabilities=0
1174 PXCAPNextCapability=0
1182 clk_domain=system.clk_domain
1183 config_latency=20000
1192 platform=system.realview
1194 config=system.iobus.master[24]
1195 dma=system.iobus.slave[3]
1196 pio=system.iobus.master[23]
1198 [system.realview.kmi0]
1201 clk_domain=system.clk_domain
1203 gic=system.realview.gic
1210 vnc=system.vncserver
1211 pio=system.iobus.master[6]
1213 [system.realview.kmi1]
1216 clk_domain=system.clk_domain
1218 gic=system.realview.gic
1225 vnc=system.vncserver
1226 pio=system.iobus.master[7]
1228 [system.realview.l2x0_fake]
1230 clk_domain=system.clk_domain
1238 ret_data32=4294967295
1239 ret_data64=18446744073709551615
1244 pio=system.iobus.master[12]
1246 [system.realview.lan_fake]
1248 clk_domain=system.clk_domain
1256 ret_data32=4294967295
1257 ret_data64=18446744073709551615
1262 pio=system.iobus.master[19]
1264 [system.realview.local_cpu_timer]
1266 clk_domain=system.clk_domain
1268 gic=system.realview.gic
1274 pio=system.membus.master[3]
1276 [system.realview.mmc_fake]
1279 clk_domain=system.clk_domain
1285 pio=system.iobus.master[21]
1287 [system.realview.nvmem]
1290 clk_domain=system.clk_domain
1291 conf_table_reported=false
1298 port=system.membus.master[1]
1300 [system.realview.pciconfig]
1303 clk_domain=system.clk_domain
1307 platform=system.realview
1310 pio=system.iobus.default
1312 [system.realview.realview_io]
1314 clk_domain=system.clk_domain
1322 pio=system.iobus.master[1]
1324 [system.realview.rtc]
1327 clk_domain=system.clk_domain
1329 gic=system.realview.gic
1335 time=Thu Jan 1 00:00:00 2009
1336 pio=system.iobus.master[10]
1338 [system.realview.sp810_fake]
1341 clk_domain=system.clk_domain
1347 pio=system.iobus.master[16]
1349 [system.realview.timer0]
1352 clk_domain=system.clk_domain
1356 gic=system.realview.gic
1362 pio=system.iobus.master[2]
1364 [system.realview.timer1]
1367 clk_domain=system.clk_domain
1371 gic=system.realview.gic
1377 pio=system.iobus.master[3]
1379 [system.realview.uart]
1381 clk_domain=system.clk_domain
1384 gic=system.realview.gic
1389 platform=system.realview
1391 terminal=system.terminal
1392 pio=system.iobus.master[0]
1394 [system.realview.uart1_fake]
1397 clk_domain=system.clk_domain
1403 pio=system.iobus.master[13]
1405 [system.realview.uart2_fake]
1408 clk_domain=system.clk_domain
1414 pio=system.iobus.master[14]
1416 [system.realview.uart3_fake]
1419 clk_domain=system.clk_domain
1425 pio=system.iobus.master[15]
1427 [system.realview.usb_fake]
1429 clk_domain=system.clk_domain
1437 ret_data32=4294967295
1438 ret_data64=18446744073709551615
1443 pio=system.iobus.master[20]
1445 [system.realview.vgic]
1447 clk_domain=system.clk_domain
1449 gic=system.realview.gic
1452 platform=system.realview
1456 pio=system.membus.master[4]
1458 [system.realview.vram]
1461 clk_domain=system.clk_domain
1462 conf_table_reported=false
1468 range=402653184:436207615
1469 port=system.iobus.master[11]
1471 [system.realview.watchdog_fake]
1474 clk_domain=system.clk_domain
1480 pio=system.iobus.master[17]
1485 intr_control=system.intrctrl
1492 clk_domain=system.cpu_clk_domain
1497 use_default_range=false
1499 master=system.l2c.cpu_side
1500 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1509 [system.voltage_domain]