2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.411694 # Number of seconds simulated
4 sim_ticks 2411694099500 # Number of ticks simulated
5 final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 2039542 # Simulator instruction rate (inst/s)
8 host_tick_rate 61821688958 # Simulator tick rate (ticks/s)
9 host_mem_usage 378872 # Number of bytes of host memory used
10 host_seconds 39.01 # Real time elapsed on the host
11 sim_insts 79563488 # Number of instructions simulated
12 system.nvmem.bytes_read 68 # Number of bytes read from this memory
13 system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
14 system.nvmem.bytes_written 0 # Number of bytes written to this memory
15 system.nvmem.num_reads 17 # Number of read requests responded to by this memory
16 system.nvmem.num_writes 0 # Number of write requests responded to by this memory
17 system.nvmem.num_other 0 # Number of other requests responded to by this memory
18 system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s)
19 system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s)
20 system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s)
21 system.physmem.bytes_read 123270308 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written 10185232 # Number of bytes written to this memory
24 system.physmem.num_reads 14146769 # Number of read requests responded to by this memory
25 system.physmem.num_writes 869038 # Number of write requests responded to by this memory
26 system.physmem.num_other 0 # Number of other requests responded to by this memory
27 system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s)
30 system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s)
31 system.l2c.replacements 127720 # number of replacements
32 system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
33 system.l2c.total_refs 1498989 # Total number of references to valid blocks.
34 system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
35 system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
36 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
37 system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context
38 system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context
39 system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context
40 system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy
41 system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy
42 system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy
43 system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits
44 system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits
45 system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits
46 system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
47 system.l2c.Writeback_hits::0 580461 # number of Writeback hits
48 system.l2c.Writeback_hits::total 580461 # number of Writeback hits
49 system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits
50 system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits
51 system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
52 system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits
53 system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits
54 system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits
55 system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits
56 system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits
57 system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits
58 system.l2c.demand_hits::0 771021 # number of demand (read+write) hits
59 system.l2c.demand_hits::1 537612 # number of demand (read+write) hits
60 system.l2c.demand_hits::2 12920 # number of demand (read+write) hits
61 system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
62 system.l2c.overall_hits::0 771021 # number of overall hits
63 system.l2c.overall_hits::1 537612 # number of overall hits
64 system.l2c.overall_hits::2 12920 # number of overall hits
65 system.l2c.overall_hits::total 1321553 # number of overall hits
66 system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses
67 system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses
68 system.l2c.ReadReq_misses::2 52 # number of ReadReq misses
69 system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses
70 system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses
71 system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses
72 system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses
73 system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses
74 system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses
75 system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses
76 system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses
77 system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses
78 system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses
79 system.l2c.demand_misses::0 118723 # number of demand (read+write) misses
80 system.l2c.demand_misses::1 64009 # number of demand (read+write) misses
81 system.l2c.demand_misses::2 52 # number of demand (read+write) misses
82 system.l2c.demand_misses::total 182784 # number of demand (read+write) misses
83 system.l2c.overall_misses::0 118723 # number of overall misses
84 system.l2c.overall_misses::1 64009 # number of overall misses
85 system.l2c.overall_misses::2 52 # number of overall misses
86 system.l2c.overall_misses::total 182784 # number of overall misses
87 system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
88 system.l2c.overall_miss_latency 0 # number of overall miss cycles
89 system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses)
90 system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses)
91 system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses)
92 system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
93 system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses)
94 system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
95 system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses)
96 system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses)
97 system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
98 system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses)
99 system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses)
100 system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses)
101 system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses)
102 system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses)
103 system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses)
104 system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses
105 system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses
106 system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses
107 system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
108 system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses
109 system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses
110 system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses
111 system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
112 system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses
113 system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses
114 system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses
115 system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses
116 system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses
117 system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses
118 system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses
119 system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses
120 system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses
121 system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses
122 system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses
123 system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses
124 system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses
125 system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses
126 system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses
127 system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses
128 system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses
129 system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses
130 system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
131 system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
132 system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
133 system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
134 system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
135 system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
136 system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
137 system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
138 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
139 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
140 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
141 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
142 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
143 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
144 system.l2c.fast_writes 0 # number of fast writes performed
145 system.l2c.cache_copies 0 # number of cache copies performed
146 system.l2c.writebacks 111818 # number of writebacks
147 system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
148 system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
149 system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
150 system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
151 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
152 system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
153 system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
154 system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
155 system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
156 system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
157 system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
158 system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
159 system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
160 system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
161 system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
162 system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
163 system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
164 system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
165 system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
166 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
167 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
168 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
169 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
170 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
171 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
172 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
173 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
174 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
175 system.cpu0.dtb.inst_hits 0 # ITB inst hits
176 system.cpu0.dtb.inst_misses 0 # ITB inst misses
177 system.cpu0.dtb.read_hits 9339288 # DTB read hits
178 system.cpu0.dtb.read_misses 5153 # DTB read misses
179 system.cpu0.dtb.write_hits 6907876 # DTB write hits
180 system.cpu0.dtb.write_misses 1048 # DTB write misses
181 system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
182 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
183 system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
184 system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
185 system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
186 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
187 system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
188 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
189 system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
190 system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
191 system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
192 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
193 system.cpu0.dtb.hits 16247164 # DTB hits
194 system.cpu0.dtb.misses 6201 # DTB misses
195 system.cpu0.dtb.accesses 16253365 # DTB accesses
196 system.cpu0.itb.inst_hits 34822552 # ITB inst hits
197 system.cpu0.itb.inst_misses 2978 # ITB inst misses
198 system.cpu0.itb.read_hits 0 # DTB read hits
199 system.cpu0.itb.read_misses 0 # DTB read misses
200 system.cpu0.itb.write_hits 0 # DTB write hits
201 system.cpu0.itb.write_misses 0 # DTB write misses
202 system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
203 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
204 system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
205 system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
206 system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
207 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
208 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
209 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
210 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
211 system.cpu0.itb.read_accesses 0 # DTB read accesses
212 system.cpu0.itb.write_accesses 0 # DTB write accesses
213 system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
214 system.cpu0.itb.hits 34822552 # DTB hits
215 system.cpu0.itb.misses 2978 # DTB misses
216 system.cpu0.itb.accesses 34825530 # DTB accesses
217 system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
218 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
219 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
220 system.cpu0.num_insts 44975797 # Number of instructions executed
221 system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
222 system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
223 system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
224 system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls
225 system.cpu0.num_int_insts 39858123 # number of integer instructions
226 system.cpu0.num_fp_insts 4945 # number of float instructions
227 system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read
228 system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written
229 system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
230 system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
231 system.cpu0.num_mem_refs 17030946 # number of memory refs
232 system.cpu0.num_load_insts 9786549 # Number of load instructions
233 system.cpu0.num_store_insts 7244397 # Number of store instructions
234 system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles
235 system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles
236 system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
237 system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
238 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
239 system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
240 system.cpu0.icache.replacements 504460 # number of replacements
241 system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
242 system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks.
243 system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
244 system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks.
245 system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
246 system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context
247 system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy
248 system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits
249 system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits
250 system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits
251 system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
252 system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits
253 system.cpu0.icache.overall_hits::0 34319155 # number of overall hits
254 system.cpu0.icache.overall_hits::1 0 # number of overall hits
255 system.cpu0.icache.overall_hits::total 34319155 # number of overall hits
256 system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses
257 system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
258 system.cpu0.icache.demand_misses::0 504973 # number of demand (read+write) misses
259 system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
260 system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses
261 system.cpu0.icache.overall_misses::0 504973 # number of overall misses
262 system.cpu0.icache.overall_misses::1 0 # number of overall misses
263 system.cpu0.icache.overall_misses::total 504973 # number of overall misses
264 system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
265 system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
266 system.cpu0.icache.ReadReq_accesses::0 34824128 # number of ReadReq accesses(hits+misses)
267 system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses)
268 system.cpu0.icache.demand_accesses::0 34824128 # number of demand (read+write) accesses
269 system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
270 system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses
271 system.cpu0.icache.overall_accesses::0 34824128 # number of overall (read+write) accesses
272 system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
273 system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses
274 system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses
275 system.cpu0.icache.demand_miss_rate::0 0.014501 # miss rate for demand accesses
276 system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
277 system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
278 system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses
279 system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
280 system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
281 system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency
282 system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
283 system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency
284 system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency
285 system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
286 system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency
287 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
288 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
289 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
290 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
291 system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
292 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
293 system.cpu0.icache.fast_writes 0 # number of fast writes performed
294 system.cpu0.icache.cache_copies 0 # number of cache copies performed
295 system.cpu0.icache.writebacks 24728 # number of writebacks
296 system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
297 system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
298 system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
299 system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
300 system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
301 system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
302 system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
303 system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
304 system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
305 system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
306 system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
307 system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
308 system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
309 system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
310 system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
311 system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
312 system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
313 system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
314 system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
315 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
316 system.cpu0.dcache.replacements 380107 # number of replacements
317 system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use
318 system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks.
319 system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks.
320 system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks.
321 system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
322 system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context
323 system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy
324 system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits
325 system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits
326 system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits
327 system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits
328 system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits
329 system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
330 system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits
331 system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits
332 system.cpu0.dcache.demand_hits::0 14337355 # number of demand (read+write) hits
333 system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
334 system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits
335 system.cpu0.dcache.overall_hits::0 14337355 # number of overall hits
336 system.cpu0.dcache.overall_hits::1 0 # number of overall hits
337 system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits
338 system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses
339 system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses
340 system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses
341 system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses
342 system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses
343 system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses
344 system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses
345 system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses
346 system.cpu0.dcache.demand_misses::0 420930 # number of demand (read+write) misses
347 system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
348 system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses
349 system.cpu0.dcache.overall_misses::0 420930 # number of overall misses
350 system.cpu0.dcache.overall_misses::1 0 # number of overall misses
351 system.cpu0.dcache.overall_misses::total 420930 # number of overall misses
352 system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
353 system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
354 system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses)
355 system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses)
356 system.cpu0.dcache.WriteReq_accesses::0 6717639 # number of WriteReq accesses(hits+misses)
357 system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses)
358 system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses)
359 system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
360 system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses)
361 system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
362 system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses
363 system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
364 system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses
365 system.cpu0.dcache.overall_accesses::0 14758285 # number of overall (read+write) accesses
366 system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
367 system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses
368 system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses
369 system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses
370 system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses
371 system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses
372 system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses
373 system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
374 system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
375 system.cpu0.dcache.overall_miss_rate::0 0.028522 # miss rate for overall accesses
376 system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
377 system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
378 system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
379 system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
380 system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
381 system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
382 system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
383 system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
384 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
385 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
386 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
387 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
388 system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
389 system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
390 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
391 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
392 system.cpu0.dcache.writebacks 339627 # number of writebacks
393 system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
394 system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
395 system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
396 system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
397 system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
398 system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
399 system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
400 system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
401 system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
402 system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
403 system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
404 system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
405 system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
406 system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
407 system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
408 system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
409 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
410 system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
411 system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
412 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
413 system.cpu1.dtb.inst_hits 0 # ITB inst hits
414 system.cpu1.dtb.inst_misses 0 # ITB inst misses
415 system.cpu1.dtb.read_hits 6258230 # DTB read hits
416 system.cpu1.dtb.read_misses 2159 # DTB read misses
417 system.cpu1.dtb.write_hits 4713962 # DTB write hits
418 system.cpu1.dtb.write_misses 1181 # DTB write misses
419 system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
420 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
421 system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
422 system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
423 system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB
424 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
425 system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
426 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
427 system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
428 system.cpu1.dtb.read_accesses 6260389 # DTB read accesses
429 system.cpu1.dtb.write_accesses 4715143 # DTB write accesses
430 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
431 system.cpu1.dtb.hits 10972192 # DTB hits
432 system.cpu1.dtb.misses 3340 # DTB misses
433 system.cpu1.dtb.accesses 10975532 # DTB accesses
434 system.cpu1.itb.inst_hits 27739434 # ITB inst hits
435 system.cpu1.itb.inst_misses 1388 # ITB inst misses
436 system.cpu1.itb.read_hits 0 # DTB read hits
437 system.cpu1.itb.read_misses 0 # DTB read misses
438 system.cpu1.itb.write_hits 0 # DTB write hits
439 system.cpu1.itb.write_misses 0 # DTB write misses
440 system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
441 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
442 system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
443 system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
444 system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB
445 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
446 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
447 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
448 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
449 system.cpu1.itb.read_accesses 0 # DTB read accesses
450 system.cpu1.itb.write_accesses 0 # DTB write accesses
451 system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses
452 system.cpu1.itb.hits 27739434 # DTB hits
453 system.cpu1.itb.misses 1388 # DTB misses
454 system.cpu1.itb.accesses 27740822 # DTB accesses
455 system.cpu1.numCycles 4822838236 # number of cpu cycles simulated
456 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
457 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
458 system.cpu1.num_insts 34587691 # Number of instructions executed
459 system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses
460 system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses
461 system.cpu1.num_func_calls 758024 # number of times a function call or return occured
462 system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls
463 system.cpu1.num_int_insts 30998246 # number of integer instructions
464 system.cpu1.num_fp_insts 5772 # number of float instructions
465 system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read
466 system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written
467 system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read
468 system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written
469 system.cpu1.num_mem_refs 11415835 # number of memory refs
470 system.cpu1.num_load_insts 6478994 # Number of load instructions
471 system.cpu1.num_store_insts 4936841 # Number of store instructions
472 system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles
473 system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles
474 system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles
475 system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles
476 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
477 system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed
478 system.cpu1.icache.replacements 374406 # number of replacements
479 system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use
480 system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks.
481 system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks.
482 system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks.
483 system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit.
484 system.cpu1.icache.occ_blocks::0 498.143079 # Average occupied blocks per context
485 system.cpu1.icache.occ_percent::0 0.972936 # Average percentage of cache occupancy
486 system.cpu1.icache.ReadReq_hits::0 27365572 # number of ReadReq hits
487 system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits
488 system.cpu1.icache.demand_hits::0 27365572 # number of demand (read+write) hits
489 system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
490 system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits
491 system.cpu1.icache.overall_hits::0 27365572 # number of overall hits
492 system.cpu1.icache.overall_hits::1 0 # number of overall hits
493 system.cpu1.icache.overall_hits::total 27365572 # number of overall hits
494 system.cpu1.icache.ReadReq_misses::0 374920 # number of ReadReq misses
495 system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses
496 system.cpu1.icache.demand_misses::0 374920 # number of demand (read+write) misses
497 system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
498 system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses
499 system.cpu1.icache.overall_misses::0 374920 # number of overall misses
500 system.cpu1.icache.overall_misses::1 0 # number of overall misses
501 system.cpu1.icache.overall_misses::total 374920 # number of overall misses
502 system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
503 system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
504 system.cpu1.icache.ReadReq_accesses::0 27740492 # number of ReadReq accesses(hits+misses)
505 system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses)
506 system.cpu1.icache.demand_accesses::0 27740492 # number of demand (read+write) accesses
507 system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
508 system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses
509 system.cpu1.icache.overall_accesses::0 27740492 # number of overall (read+write) accesses
510 system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
511 system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses
512 system.cpu1.icache.ReadReq_miss_rate::0 0.013515 # miss rate for ReadReq accesses
513 system.cpu1.icache.demand_miss_rate::0 0.013515 # miss rate for demand accesses
514 system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
515 system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
516 system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses
517 system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
518 system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
519 system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency
520 system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
521 system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency
522 system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency
523 system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
524 system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency
525 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
526 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
527 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
528 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
529 system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
530 system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
531 system.cpu1.icache.fast_writes 0 # number of fast writes performed
532 system.cpu1.icache.cache_copies 0 # number of cache copies performed
533 system.cpu1.icache.writebacks 13905 # number of writebacks
534 system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
535 system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
536 system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
537 system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
538 system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
539 system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
540 system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
541 system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
542 system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
543 system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
544 system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
545 system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
546 system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
547 system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
548 system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
549 system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
550 system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
551 system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
552 system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
553 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
554 system.cpu1.dcache.replacements 247434 # number of replacements
555 system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use
556 system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks.
557 system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks.
558 system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks.
559 system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit.
560 system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context
561 system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy
562 system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits
563 system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits
564 system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits
565 system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits
566 system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits
567 system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
568 system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits
569 system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits
570 system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits
571 system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
572 system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits
573 system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits
574 system.cpu1.dcache.overall_hits::1 0 # number of overall hits
575 system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits
576 system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses
577 system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses
578 system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses
579 system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
580 system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses
581 system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
582 system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses
583 system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses
584 system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses
585 system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
586 system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses
587 system.cpu1.dcache.overall_misses::0 277266 # number of overall misses
588 system.cpu1.dcache.overall_misses::1 0 # number of overall misses
589 system.cpu1.dcache.overall_misses::total 277266 # number of overall misses
590 system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
591 system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
592 system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses)
593 system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses)
594 system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses)
595 system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses)
596 system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses)
597 system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
598 system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses)
599 system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses)
600 system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses
601 system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
602 system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses
603 system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses
604 system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
605 system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses
606 system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses
607 system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses
608 system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses
609 system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses
610 system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses
611 system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
612 system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
613 system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses
614 system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
615 system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
616 system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
617 system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
618 system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
619 system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
620 system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
621 system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
622 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
623 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
624 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
625 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
626 system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
627 system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
628 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
629 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
630 system.cpu1.dcache.writebacks 202201 # number of writebacks
631 system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
632 system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
633 system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
634 system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
635 system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
636 system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
637 system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
638 system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
639 system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
640 system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
641 system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
642 system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
643 system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
644 system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
645 system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
646 system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
647 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
648 system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
649 system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
650 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
651 system.iocache.replacements 0 # number of replacements
652 system.iocache.tagsinuse 0 # Cycle average of tags in use
653 system.iocache.total_refs 0 # Total number of references to valid blocks.
654 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
655 system.iocache.avg_refs no_value # Average number of references to valid blocks.
656 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
657 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
658 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
659 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
660 system.iocache.overall_hits::0 0 # number of overall hits
661 system.iocache.overall_hits::1 0 # number of overall hits
662 system.iocache.overall_hits::total 0 # number of overall hits
663 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
664 system.iocache.demand_misses::1 0 # number of demand (read+write) misses
665 system.iocache.demand_misses::total 0 # number of demand (read+write) misses
666 system.iocache.overall_misses::0 0 # number of overall misses
667 system.iocache.overall_misses::1 0 # number of overall misses
668 system.iocache.overall_misses::total 0 # number of overall misses
669 system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
670 system.iocache.overall_miss_latency 0 # number of overall miss cycles
671 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
672 system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
673 system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
674 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
675 system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
676 system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
677 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
678 system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
679 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
680 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
681 system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
682 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
683 system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
684 system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
685 system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
686 system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
687 system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
688 system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
689 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
690 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
691 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
692 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
693 system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
694 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
695 system.iocache.fast_writes 0 # number of fast writes performed
696 system.iocache.cache_copies 0 # number of cache copies performed
697 system.iocache.writebacks 0 # number of writebacks
698 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
699 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
700 system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
701 system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
702 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
703 system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
704 system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
705 system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
706 system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
707 system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
708 system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
709 system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
710 system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
711 system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
712 system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
713 system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
714 system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
715 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
716 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
717 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
719 ---------- End Simulation Statistics ----------
projects / gem5.git / blob