2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.912097 # Number of seconds simulated
4 sim_ticks 912096763500 # Number of ticks simulated
5 final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1640213 # Simulator instruction rate (inst/s)
8 host_op_rate 2111770 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 24275992963 # Simulator tick rate (ticks/s)
10 host_mem_usage 394600 # Number of bytes of host memory used
11 host_seconds 37.57 # Real time elapsed on the host
12 sim_insts 61625970 # Number of instructions simulated
13 sim_ops 79343340 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
26 system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory
27 system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
28 system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
29 system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory
30 system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory
38 system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory
39 system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
40 system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
41 system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
42 system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory
43 system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s)
53 system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s)
54 system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s)
55 system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s)
56 system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
57 system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s)
58 system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s)
59 system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
62 system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
63 system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s)
64 system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
66 system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
67 system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
69 system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
70 system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
71 system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
72 system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
73 system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
74 system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
75 system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
76 system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
77 system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
78 system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
79 system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
80 system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
81 system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
82 system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
83 system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
84 system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
85 system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
86 system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
87 system.membus.throughput 64986577 # Throughput (bytes/s)
88 system.membus.data_through_bus 59274047 # Total data (bytes)
89 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
90 system.l2c.tags.replacements 70658 # number of replacements
91 system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use
92 system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks.
93 system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks.
94 system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks.
95 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
96 system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
97 system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
98 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
99 system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
100 system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
101 system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
102 system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
103 system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
104 system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
105 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
106 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
107 system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
108 system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
109 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
110 system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
111 system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
112 system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy
113 system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
114 system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
115 system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
116 system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits
117 system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits
118 system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits
119 system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits
120 system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits
121 system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits
122 system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits
123 system.l2c.Writeback_hits::total 567807 # number of Writeback hits
124 system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
125 system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits
126 system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits
127 system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
128 system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
129 system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
130 system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits
131 system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits
132 system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits
133 system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
134 system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
135 system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
136 system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits
137 system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
138 system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
139 system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
140 system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
141 system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits
142 system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
143 system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
144 system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
145 system.l2c.overall_hits::cpu0.data 233336 # number of overall hits
146 system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
147 system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
148 system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
149 system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
150 system.l2c.overall_hits::total 1317466 # number of overall hits
151 system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
152 system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
153 system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
154 system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses
155 system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
156 system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses
157 system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses
158 system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses
159 system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses
160 system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses
161 system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses
162 system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
163 system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
164 system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
165 system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses
166 system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses
167 system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses
168 system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
169 system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
170 system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
171 system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses
172 system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
173 system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
174 system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses
175 system.l2c.demand_misses::total 163290 # number of demand (read+write) misses
176 system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
177 system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
178 system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
179 system.l2c.overall_misses::cpu0.data 98856 # number of overall misses
180 system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
181 system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
182 system.l2c.overall_misses::cpu1.data 53648 # number of overall misses
183 system.l2c.overall_misses::total 163290 # number of overall misses
184 system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
185 system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
186 system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
187 system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses)
188 system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses)
189 system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses)
190 system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses)
191 system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses)
192 system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses)
193 system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses)
194 system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses)
195 system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses)
196 system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses)
197 system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses)
198 system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
199 system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
200 system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
201 system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses)
202 system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses)
203 system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses)
204 system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses
205 system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses
206 system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses
207 system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses
208 system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses
209 system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses
210 system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses
211 system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses
212 system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses
213 system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses
214 system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses
215 system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses
216 system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses
217 system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses
218 system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses
219 system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses
220 system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses
221 system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses
222 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses
223 system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses
224 system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses
225 system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses
226 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses
227 system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses
228 system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses
229 system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses
230 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses
231 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses
232 system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses
233 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
234 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
235 system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
236 system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses
237 system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
238 system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses
239 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
240 system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
241 system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
242 system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses
243 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
244 system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
245 system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses
246 system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses
247 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
248 system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
249 system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
250 system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses
251 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
252 system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
253 system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses
254 system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses
255 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
256 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
257 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
258 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
259 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
260 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
261 system.l2c.fast_writes 0 # number of fast writes performed
262 system.l2c.cache_copies 0 # number of cache copies performed
263 system.l2c.writebacks::writebacks 65559 # number of writebacks
264 system.l2c.writebacks::total 65559 # number of writebacks
265 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
266 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
267 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
268 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
269 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
270 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
271 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
272 system.toL2Bus.throughput 154009014 # Throughput (bytes/s)
273 system.toL2Bus.data_through_bus 140471123 # Total data (bytes)
274 system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
275 system.iobus.throughput 45730949 # Throughput (bytes/s)
276 system.iobus.data_through_bus 41711051 # Total data (bytes)
277 system.cpu0.dtb.inst_hits 0 # ITB inst hits
278 system.cpu0.dtb.inst_misses 0 # ITB inst misses
279 system.cpu0.dtb.read_hits 7975768 # DTB read hits
280 system.cpu0.dtb.read_misses 3611 # DTB read misses
281 system.cpu0.dtb.write_hits 5966574 # DTB write hits
282 system.cpu0.dtb.write_misses 672 # DTB write misses
283 system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
284 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
285 system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
286 system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
287 system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
288 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
289 system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
290 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
291 system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
292 system.cpu0.dtb.read_accesses 7979379 # DTB read accesses
293 system.cpu0.dtb.write_accesses 5967246 # DTB write accesses
294 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
295 system.cpu0.dtb.hits 13942342 # DTB hits
296 system.cpu0.dtb.misses 4283 # DTB misses
297 system.cpu0.dtb.accesses 13946625 # DTB accesses
298 system.cpu0.itb.inst_hits 30238804 # ITB inst hits
299 system.cpu0.itb.inst_misses 2175 # ITB inst misses
300 system.cpu0.itb.read_hits 0 # DTB read hits
301 system.cpu0.itb.read_misses 0 # DTB read misses
302 system.cpu0.itb.write_hits 0 # DTB write hits
303 system.cpu0.itb.write_misses 0 # DTB write misses
304 system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
305 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
306 system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
307 system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
308 system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB
309 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
310 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
311 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
312 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
313 system.cpu0.itb.read_accesses 0 # DTB read accesses
314 system.cpu0.itb.write_accesses 0 # DTB write accesses
315 system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses
316 system.cpu0.itb.hits 30238804 # DTB hits
317 system.cpu0.itb.misses 2175 # DTB misses
318 system.cpu0.itb.accesses 30240979 # DTB accesses
319 system.cpu0.numCycles 1823633059 # number of cpu cycles simulated
320 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
321 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
322 system.cpu0.committedInsts 29750005 # Number of instructions committed
323 system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed
324 system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses
325 system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
326 system.cpu0.num_func_calls 1241903 # number of times a function call or return occured
327 system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls
328 system.cpu0.num_int_insts 34471201 # number of integer instructions
329 system.cpu0.num_fp_insts 5449 # number of float instructions
330 system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read
331 system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written
332 system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
333 system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
334 system.cpu0.num_mem_refs 14626951 # number of memory refs
335 system.cpu0.num_load_insts 8357226 # Number of load instructions
336 system.cpu0.num_store_insts 6269725 # Number of store instructions
337 system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles
338 system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles
339 system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles
340 system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
341 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
342 system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
343 system.cpu0.icache.tags.replacements 428546 # number of replacements
344 system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use
345 system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks.
346 system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
347 system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks.
348 system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
349 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
350 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
351 system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy
352 system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
353 system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
354 system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits
355 system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits
356 system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits
357 system.cpu0.icache.overall_hits::total 29811115 # number of overall hits
358 system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
359 system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
360 system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
361 system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
362 system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
363 system.cpu0.icache.overall_misses::total 429059 # number of overall misses
364 system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses)
365 system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses)
366 system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses
367 system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses
368 system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses
369 system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses
370 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses
371 system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses
372 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses
373 system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses
374 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses
375 system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses
376 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
380 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
381 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
382 system.cpu0.icache.fast_writes 0 # number of fast writes performed
383 system.cpu0.icache.cache_copies 0 # number of cache copies performed
384 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
385 system.cpu0.dcache.tags.replacements 323609 # number of replacements
386 system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use
387 system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks.
388 system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks.
389 system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks.
390 system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
391 system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor
392 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
393 system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
394 system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits
395 system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits
396 system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits
397 system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits
398 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits
399 system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits
400 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
401 system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
402 system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits
403 system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits
404 system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits
405 system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits
406 system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
407 system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
408 system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses
409 system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses
410 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses
411 system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses
412 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses
413 system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses
414 system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses
415 system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses
416 system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses
417 system.cpu0.dcache.overall_misses::total 364509 # number of overall misses
418 system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses)
419 system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses)
420 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses)
421 system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses)
422 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses)
423 system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses)
424 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses)
425 system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses)
426 system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses
427 system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses
428 system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses
429 system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses
430 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses
431 system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses
432 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses
433 system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses
434 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses
435 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses
436 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses
437 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses
438 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses
439 system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses
440 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses
441 system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses
442 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
443 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
444 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
445 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
446 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
447 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
448 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
449 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
450 system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks
451 system.cpu0.dcache.writebacks::total 300958 # number of writebacks
452 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
453 system.cpu1.dtb.inst_hits 0 # ITB inst hits
454 system.cpu1.dtb.inst_misses 0 # ITB inst misses
455 system.cpu1.dtb.read_hits 7364781 # DTB read hits
456 system.cpu1.dtb.read_misses 3705 # DTB read misses
457 system.cpu1.dtb.write_hits 5489656 # DTB write hits
458 system.cpu1.dtb.write_misses 1595 # DTB write misses
459 system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
460 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
461 system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
462 system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
463 system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB
464 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
465 system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
466 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
467 system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
468 system.cpu1.dtb.read_accesses 7368486 # DTB read accesses
469 system.cpu1.dtb.write_accesses 5491251 # DTB write accesses
470 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
471 system.cpu1.dtb.hits 12854437 # DTB hits
472 system.cpu1.dtb.misses 5300 # DTB misses
473 system.cpu1.dtb.accesses 12859737 # DTB accesses
474 system.cpu1.itb.inst_hits 32412306 # ITB inst hits
475 system.cpu1.itb.inst_misses 2200 # ITB inst misses
476 system.cpu1.itb.read_hits 0 # DTB read hits
477 system.cpu1.itb.read_misses 0 # DTB read misses
478 system.cpu1.itb.write_hits 0 # DTB write hits
479 system.cpu1.itb.write_misses 0 # DTB write misses
480 system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
481 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
482 system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
483 system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
484 system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
485 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
486 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
487 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
488 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
489 system.cpu1.itb.read_accesses 0 # DTB read accesses
490 system.cpu1.itb.write_accesses 0 # DTB write accesses
491 system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses
492 system.cpu1.itb.hits 32412306 # DTB hits
493 system.cpu1.itb.misses 2200 # DTB misses
494 system.cpu1.itb.accesses 32414506 # DTB accesses
495 system.cpu1.numCycles 1824154149 # number of cpu cycles simulated
496 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
497 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
498 system.cpu1.committedInsts 31875965 # Number of instructions committed
499 system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed
500 system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses
501 system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
502 system.cpu1.num_func_calls 955227 # number of times a function call or return occured
503 system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls
504 system.cpu1.num_int_insts 35797832 # number of integer instructions
505 system.cpu1.num_fp_insts 4436 # number of float instructions
506 system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read
507 system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written
508 system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
509 system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
510 system.cpu1.num_mem_refs 13370713 # number of memory refs
511 system.cpu1.num_load_insts 7642673 # Number of load instructions
512 system.cpu1.num_store_insts 5728040 # Number of store instructions
513 system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles
514 system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles
515 system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles
516 system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles
517 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
518 system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed
519 system.cpu1.icache.tags.replacements 433942 # number of replacements
520 system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use
521 system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks.
522 system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
523 system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks.
524 system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit.
525 system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor
526 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy
527 system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy
528 system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits
529 system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits
530 system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits
531 system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits
532 system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits
533 system.cpu1.icache.overall_hits::total 31979125 # number of overall hits
534 system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses
535 system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses
536 system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses
537 system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses
538 system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses
539 system.cpu1.icache.overall_misses::total 434454 # number of overall misses
540 system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses)
541 system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses)
542 system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses
543 system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses
544 system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses
545 system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses
546 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses
547 system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses
548 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses
549 system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses
550 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses
551 system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses
552 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
553 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
554 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
555 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
556 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
557 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
558 system.cpu1.icache.fast_writes 0 # number of fast writes performed
559 system.cpu1.icache.cache_copies 0 # number of cache copies performed
560 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
561 system.cpu1.dcache.tags.replacements 294289 # number of replacements
562 system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use
563 system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks.
564 system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
565 system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks.
566 system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit.
567 system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor
568 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy
569 system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy
570 system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits
571 system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits
572 system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits
573 system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits
574 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits
575 system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits
576 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
577 system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
578 system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits
579 system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits
580 system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits
581 system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits
582 system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses
583 system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses
584 system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses
585 system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses
586 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses
587 system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses
588 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses
589 system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses
590 system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses
591 system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses
592 system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses
593 system.cpu1.dcache.overall_misses::total 324195 # number of overall misses
594 system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses)
595 system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses)
596 system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses)
597 system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses)
598 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses)
599 system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses)
600 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses)
601 system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses)
602 system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses
603 system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses
604 system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses
605 system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses
606 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses
607 system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses
608 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses
609 system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses
610 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses
611 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses
612 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses
613 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses
614 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses
615 system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses
616 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses
617 system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses
618 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
619 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
620 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
621 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
622 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
623 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
624 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
625 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
626 system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks
627 system.cpu1.dcache.writebacks::total 266849 # number of writebacks
628 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
629 system.iocache.tags.replacements 0 # number of replacements
630 system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
631 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
632 system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
633 system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
634 system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
635 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
636 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
637 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
638 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
639 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
640 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
641 system.iocache.fast_writes 0 # number of fast writes performed
642 system.iocache.cache_copies 0 # number of cache copies performed
643 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
645 ---------- End Simulation Statistics ----------
projects / gem5.git / blob