2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.616536 # Number of seconds simulated
4 sim_ticks 2616536483000 # Number of ticks simulated
5 final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 343075 # Simulator instruction rate (inst/s)
8 host_op_rate 436578 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 14912044248 # Simulator tick rate (ticks/s)
10 host_mem_usage 444348 # Number of bytes of host memory used
11 host_seconds 175.46 # Real time elapsed on the host
12 sim_insts 60197580 # Number of instructions simulated
13 sim_ops 76603973 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory
23 system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory
25 system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory
30 system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory
31 system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory
32 system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory
34 system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.readReqs 15494693 # Number of read requests accepted
53 system.physmem.writeReqs 811927 # Number of write requests accepted
54 system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue
55 system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue
56 system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM
57 system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue
58 system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM
59 system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side
60 system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side
61 system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue
62 system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one
63 system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write
64 system.physmem.perBankRdBursts::0 967983 # Per bank write bursts
65 system.physmem.perBankRdBursts::1 967714 # Per bank write bursts
66 system.physmem.perBankRdBursts::2 967672 # Per bank write bursts
67 system.physmem.perBankRdBursts::3 967769 # Per bank write bursts
68 system.physmem.perBankRdBursts::4 974609 # Per bank write bursts
69 system.physmem.perBankRdBursts::5 968229 # Per bank write bursts
70 system.physmem.perBankRdBursts::6 967807 # Per bank write bursts
71 system.physmem.perBankRdBursts::7 967736 # Per bank write bursts
72 system.physmem.perBankRdBursts::8 968546 # Per bank write bursts
73 system.physmem.perBankRdBursts::9 968137 # Per bank write bursts
74 system.physmem.perBankRdBursts::10 967949 # Per bank write bursts
75 system.physmem.perBankRdBursts::11 967746 # Per bank write bursts
76 system.physmem.perBankRdBursts::12 967851 # Per bank write bursts
77 system.physmem.perBankRdBursts::13 967741 # Per bank write bursts
78 system.physmem.perBankRdBursts::14 967766 # Per bank write bursts
79 system.physmem.perBankRdBursts::15 967796 # Per bank write bursts
80 system.physmem.perBankWrBursts::0 6610 # Per bank write bursts
81 system.physmem.perBankWrBursts::1 6410 # Per bank write bursts
82 system.physmem.perBankWrBursts::2 6422 # Per bank write bursts
83 system.physmem.perBankWrBursts::3 6344 # Per bank write bursts
84 system.physmem.perBankWrBursts::4 6906 # Per bank write bursts
85 system.physmem.perBankWrBursts::5 7096 # Per bank write bursts
86 system.physmem.perBankWrBursts::6 6901 # Per bank write bursts
87 system.physmem.perBankWrBursts::7 6892 # Per bank write bursts
88 system.physmem.perBankWrBursts::8 7193 # Per bank write bursts
89 system.physmem.perBankWrBursts::9 6845 # Per bank write bursts
90 system.physmem.perBankWrBursts::10 6667 # Per bank write bursts
91 system.physmem.perBankWrBursts::11 6550 # Per bank write bursts
92 system.physmem.perBankWrBursts::12 6596 # Per bank write bursts
93 system.physmem.perBankWrBursts::13 6392 # Per bank write bursts
94 system.physmem.perBankWrBursts::14 6532 # Per bank write bursts
95 system.physmem.perBankWrBursts::15 6576 # Per bank write bursts
96 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
97 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
98 system.physmem.totGap 2616532122000 # Total gap between requests
99 system.physmem.readPktSize::0 0 # Read request sizes (log2)
100 system.physmem.readPktSize::1 0 # Read request sizes (log2)
101 system.physmem.readPktSize::2 6652 # Read request sizes (log2)
102 system.physmem.readPktSize::3 15335424 # Read request sizes (log2)
103 system.physmem.readPktSize::4 0 # Read request sizes (log2)
104 system.physmem.readPktSize::5 0 # Read request sizes (log2)
105 system.physmem.readPktSize::6 152617 # Read request sizes (log2)
106 system.physmem.writePktSize::0 0 # Write request sizes (log2)
107 system.physmem.writePktSize::1 0 # Write request sizes (log2)
108 system.physmem.writePktSize::2 754018 # Write request sizes (log2)
109 system.physmem.writePktSize::3 0 # Write request sizes (log2)
110 system.physmem.writePktSize::4 0 # Write request sizes (log2)
111 system.physmem.writePktSize::5 0 # Write request sizes (log2)
112 system.physmem.writePktSize::6 57909 # Write request sizes (log2)
113 system.physmem.rdQLenPdf::0 1246989 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::9 20800 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::10 20766 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::11 20672 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::12 20426 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::13 20356 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::14 20289 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::15 20260 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::16 161 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
145 system.physmem.wrQLenPdf::0 4861 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::1 4863 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::2 4862 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::4 4863 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::5 4861 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::6 4862 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::7 4861 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::8 4861 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::9 4861 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::10 4861 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::11 4861 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::13 4861 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::14 4862 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::15 4861 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::16 4861 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::17 4861 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::18 4861 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::19 4861 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::21 4861 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
177 system.physmem.bytesPerActivate::samples 89677 # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::mean 11133.273058 # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::gmean 1028.792401 # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::stdev 16712.114180 # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::64-71 23203 25.87% 25.87% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::128-135 14561 16.24% 42.11% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::192-199 2861 3.19% 45.30% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::256-263 2042 2.28% 47.58% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::320-327 1356 1.51% 49.09% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::384-391 1217 1.36% 50.45% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::448-455 956 1.07% 51.51% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::512-519 1130 1.26% 52.77% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::576-583 649 0.72% 53.50% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::640-647 589 0.66% 54.15% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::704-711 514 0.57% 54.73% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::768-775 694 0.77% 55.50% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::832-839 336 0.37% 55.88% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::896-903 266 0.30% 56.17% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::960-967 214 0.24% 56.41% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.22% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::1088-1095 152 0.17% 57.39% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::1216-1223 137 0.15% 57.71% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::1280-1287 157 0.18% 57.89% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1344-1351 104 0.12% 58.01% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.56% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.67% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::1536-1543 181 0.20% 60.87% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.94% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::1664-1671 57 0.06% 61.01% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.05% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::1856-1863 31 0.03% 61.24% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.30% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::2112-2119 17 0.02% 61.65% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::2176-2183 32 0.04% 61.69% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::2240-2247 11 0.01% 61.70% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::2304-2311 93 0.10% 61.80% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.82% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::2432-2439 15 0.02% 61.84% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::2496-2503 26 0.03% 61.87% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::2560-2567 91 0.10% 61.97% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.98% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::2688-2695 14 0.02% 62.00% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.01% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.19% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::2880-2887 12 0.01% 62.20% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::2944-2951 12 0.01% 62.22% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.23% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::3072-3079 372 0.41% 62.64% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.66% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::3200-3207 19 0.02% 62.68% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.70% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::3328-3335 153 0.17% 62.87% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.88% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.90% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.91% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::3648-3655 10 0.01% 63.04% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.06% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.10% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.21% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::3968-3975 14 0.02% 63.23% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.51% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::4224-4231 11 0.01% 63.52% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.72% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.73% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::4608-4615 84 0.09% 63.83% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.86% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::4864-4871 89 0.10% 63.96% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.96% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.98% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::5120-5127 434 0.48% 64.47% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.49% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.49% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::5504-5511 65 0.07% 64.62% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.63% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.94% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.02% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::6144-6151 269 0.30% 65.32% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.32% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.35% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.35% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::6656-6663 83 0.09% 65.44% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::6784-6791 3 0.00% 65.45% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::6912-6919 142 0.16% 65.61% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.61% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.61% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::7168-7175 412 0.46% 66.07% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.07% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::7424-7431 84 0.09% 66.16% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.16% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::7680-7687 29 0.03% 66.20% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation
293 system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation
294 system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation
295 system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # Bytes accessed per row activation
296 system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.85% # Bytes accessed per row activation
297 system.physmem.bytesPerActivate::8960-8967 82 0.09% 66.94% # Bytes accessed per row activation
298 system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.94% # Bytes accessed per row activation
299 system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.95% # Bytes accessed per row activation
300 system.physmem.bytesPerActivate::9216-9223 407 0.45% 67.40% # Bytes accessed per row activation
301 system.physmem.bytesPerActivate::9472-9479 149 0.17% 67.57% # Bytes accessed per row activation
302 system.physmem.bytesPerActivate::9728-9735 87 0.10% 67.67% # Bytes accessed per row activation
303 system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.67% # Bytes accessed per row activation
304 system.physmem.bytesPerActivate::9984-9991 18 0.02% 67.69% # Bytes accessed per row activation
305 system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.69% # Bytes accessed per row activation
306 system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.69% # Bytes accessed per row activation
307 system.physmem.bytesPerActivate::10240-10247 273 0.30% 68.00% # Bytes accessed per row activation
308 system.physmem.bytesPerActivate::10496-10503 68 0.08% 68.07% # Bytes accessed per row activation
309 system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.07% # Bytes accessed per row activation
310 system.physmem.bytesPerActivate::10752-10759 146 0.16% 68.24% # Bytes accessed per row activation
311 system.physmem.bytesPerActivate::11008-11015 19 0.02% 68.26% # Bytes accessed per row activation
312 system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.26% # Bytes accessed per row activation
313 system.physmem.bytesPerActivate::11136-11143 6 0.01% 68.26% # Bytes accessed per row activation
314 system.physmem.bytesPerActivate::11264-11271 429 0.48% 68.74% # Bytes accessed per row activation
315 system.physmem.bytesPerActivate::11520-11527 85 0.09% 68.84% # Bytes accessed per row activation
316 system.physmem.bytesPerActivate::11776-11783 79 0.09% 68.93% # Bytes accessed per row activation
317 system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.10% # Bytes accessed per row activation
318 system.physmem.bytesPerActivate::12160-12167 2 0.00% 69.11% # Bytes accessed per row activation
319 system.physmem.bytesPerActivate::12288-12295 208 0.23% 69.34% # Bytes accessed per row activation
320 system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.34% # Bytes accessed per row activation
321 system.physmem.bytesPerActivate::12544-12551 83 0.09% 69.43% # Bytes accessed per row activation
322 system.physmem.bytesPerActivate::12800-12807 89 0.10% 69.53% # Bytes accessed per row activation
323 system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.53% # Bytes accessed per row activation
324 system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.53% # Bytes accessed per row activation
325 system.physmem.bytesPerActivate::13056-13063 144 0.16% 69.69% # Bytes accessed per row activation
326 system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.70% # Bytes accessed per row activation
327 system.physmem.bytesPerActivate::13312-13319 350 0.39% 70.09% # Bytes accessed per row activation
328 system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.09% # Bytes accessed per row activation
329 system.physmem.bytesPerActivate::13568-13575 146 0.16% 70.25% # Bytes accessed per row activation
330 system.physmem.bytesPerActivate::13824-13831 72 0.08% 70.33% # Bytes accessed per row activation
331 system.physmem.bytesPerActivate::14080-14087 82 0.09% 70.42% # Bytes accessed per row activation
332 system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.43% # Bytes accessed per row activation
333 system.physmem.bytesPerActivate::14336-14343 280 0.31% 70.74% # Bytes accessed per row activation
334 system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.74% # Bytes accessed per row activation
335 system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.74% # Bytes accessed per row activation
336 system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.85% # Bytes accessed per row activation
337 system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.85% # Bytes accessed per row activation
338 system.physmem.bytesPerActivate::14848-14855 92 0.10% 70.95% # Bytes accessed per row activation
339 system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.95% # Bytes accessed per row activation
340 system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.95% # Bytes accessed per row activation
341 system.physmem.bytesPerActivate::15104-15111 13 0.01% 70.97% # Bytes accessed per row activation
342 system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.97% # Bytes accessed per row activation
343 system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.97% # Bytes accessed per row activation
344 system.physmem.bytesPerActivate::15360-15367 493 0.55% 71.52% # Bytes accessed per row activation
345 system.physmem.bytesPerActivate::15616-15623 74 0.08% 71.60% # Bytes accessed per row activation
346 system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.61% # Bytes accessed per row activation
347 system.physmem.bytesPerActivate::15872-15879 141 0.16% 71.76% # Bytes accessed per row activation
348 system.physmem.bytesPerActivate::16128-16135 76 0.08% 71.85% # Bytes accessed per row activation
349 system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.85% # Bytes accessed per row activation
350 system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.86% # Bytes accessed per row activation
351 system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.46% # Bytes accessed per row activation
352 system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.54% # Bytes accessed per row activation
353 system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.54% # Bytes accessed per row activation
354 system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.54% # Bytes accessed per row activation
355 system.physmem.bytesPerActivate::16896-16903 148 0.17% 72.71% # Bytes accessed per row activation
356 system.physmem.bytesPerActivate::17152-17159 79 0.09% 72.80% # Bytes accessed per row activation
357 system.physmem.bytesPerActivate::17280-17287 3 0.00% 72.80% # Bytes accessed per row activation
358 system.physmem.bytesPerActivate::17408-17415 492 0.55% 73.35% # Bytes accessed per row activation
359 system.physmem.bytesPerActivate::17664-17671 15 0.02% 73.37% # Bytes accessed per row activation
360 system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.46% # Bytes accessed per row activation
361 system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation
362 system.physmem.bytesPerActivate::18176-18183 100 0.11% 73.58% # Bytes accessed per row activation
363 system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.58% # Bytes accessed per row activation
364 system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.58% # Bytes accessed per row activation
365 system.physmem.bytesPerActivate::18432-18439 274 0.31% 73.89% # Bytes accessed per row activation
366 system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.89% # Bytes accessed per row activation
367 system.physmem.bytesPerActivate::18688-18695 80 0.09% 73.98% # Bytes accessed per row activation
368 system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.98% # Bytes accessed per row activation
369 system.physmem.bytesPerActivate::18944-18951 72 0.08% 74.06% # Bytes accessed per row activation
370 system.physmem.bytesPerActivate::19008-19015 1 0.00% 74.06% # Bytes accessed per row activation
371 system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.06% # Bytes accessed per row activation
372 system.physmem.bytesPerActivate::19200-19207 144 0.16% 74.22% # Bytes accessed per row activation
373 system.physmem.bytesPerActivate::19328-19335 3 0.00% 74.22% # Bytes accessed per row activation
374 system.physmem.bytesPerActivate::19392-19399 2 0.00% 74.23% # Bytes accessed per row activation
375 system.physmem.bytesPerActivate::19456-19463 350 0.39% 74.62% # Bytes accessed per row activation
376 system.physmem.bytesPerActivate::19584-19591 2 0.00% 74.62% # Bytes accessed per row activation
377 system.physmem.bytesPerActivate::19712-19719 134 0.15% 74.77% # Bytes accessed per row activation
378 system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.77% # Bytes accessed per row activation
379 system.physmem.bytesPerActivate::19968-19975 89 0.10% 74.87% # Bytes accessed per row activation
380 system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.87% # Bytes accessed per row activation
381 system.physmem.bytesPerActivate::20224-20231 82 0.09% 74.96% # Bytes accessed per row activation
382 system.physmem.bytesPerActivate::20352-20359 5 0.01% 74.97% # Bytes accessed per row activation
383 system.physmem.bytesPerActivate::20416-20423 2 0.00% 74.97% # Bytes accessed per row activation
384 system.physmem.bytesPerActivate::20480-20487 211 0.24% 75.21% # Bytes accessed per row activation
385 system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.38% # Bytes accessed per row activation
386 system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.46% # Bytes accessed per row activation
387 system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.47% # Bytes accessed per row activation
388 system.physmem.bytesPerActivate::21248-21255 82 0.09% 75.56% # Bytes accessed per row activation
389 system.physmem.bytesPerActivate::21312-21319 2 0.00% 75.56% # Bytes accessed per row activation
390 system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.56% # Bytes accessed per row activation
391 system.physmem.bytesPerActivate::21504-21511 418 0.47% 76.03% # Bytes accessed per row activation
392 system.physmem.bytesPerActivate::21760-21767 17 0.02% 76.05% # Bytes accessed per row activation
393 system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.05% # Bytes accessed per row activation
394 system.physmem.bytesPerActivate::22016-22023 143 0.16% 76.21% # Bytes accessed per row activation
395 system.physmem.bytesPerActivate::22208-22215 1 0.00% 76.21% # Bytes accessed per row activation
396 system.physmem.bytesPerActivate::22272-22279 76 0.08% 76.29% # Bytes accessed per row activation
397 system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.30% # Bytes accessed per row activation
398 system.physmem.bytesPerActivate::22400-22407 5 0.01% 76.30% # Bytes accessed per row activation
399 system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.60% # Bytes accessed per row activation
400 system.physmem.bytesPerActivate::22784-22791 24 0.03% 76.62% # Bytes accessed per row activation
401 system.physmem.bytesPerActivate::23040-23047 84 0.09% 76.72% # Bytes accessed per row activation
402 system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.72% # Bytes accessed per row activation
403 system.physmem.bytesPerActivate::23296-23303 139 0.16% 76.87% # Bytes accessed per row activation
404 system.physmem.bytesPerActivate::23424-23431 3 0.00% 76.88% # Bytes accessed per row activation
405 system.physmem.bytesPerActivate::23552-23559 413 0.46% 77.34% # Bytes accessed per row activation
406 system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.34% # Bytes accessed per row activation
407 system.physmem.bytesPerActivate::23808-23815 81 0.09% 77.43% # Bytes accessed per row activation
408 system.physmem.bytesPerActivate::24064-24071 25 0.03% 77.46% # Bytes accessed per row activation
409 system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.46% # Bytes accessed per row activation
410 system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.46% # Bytes accessed per row activation
411 system.physmem.bytesPerActivate::24320-24327 79 0.09% 77.55% # Bytes accessed per row activation
412 system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.55% # Bytes accessed per row activation
413 system.physmem.bytesPerActivate::24576-24583 398 0.44% 77.99% # Bytes accessed per row activation
414 system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation
415 system.physmem.bytesPerActivate::24832-24839 75 0.08% 78.08% # Bytes accessed per row activation
416 system.physmem.bytesPerActivate::25088-25095 20 0.02% 78.10% # Bytes accessed per row activation
417 system.physmem.bytesPerActivate::25344-25351 86 0.10% 78.20% # Bytes accessed per row activation
418 system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation
419 system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation
420 system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation
421 system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation
422 system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation
423 system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation
424 system.physmem.bytesPerActivate::26112-26119 89 0.10% 78.92% # Bytes accessed per row activation
425 system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation
426 system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.92% # Bytes accessed per row activation
427 system.physmem.bytesPerActivate::26368-26375 21 0.02% 78.94% # Bytes accessed per row activation
428 system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation
429 system.physmem.bytesPerActivate::26624-26631 271 0.30% 79.25% # Bytes accessed per row activation
430 system.physmem.bytesPerActivate::26688-26695 2 0.00% 79.25% # Bytes accessed per row activation
431 system.physmem.bytesPerActivate::26880-26887 70 0.08% 79.33% # Bytes accessed per row activation
432 system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.33% # Bytes accessed per row activation
433 system.physmem.bytesPerActivate::27136-27143 141 0.16% 79.49% # Bytes accessed per row activation
434 system.physmem.bytesPerActivate::27392-27399 22 0.02% 79.51% # Bytes accessed per row activation
435 system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.51% # Bytes accessed per row activation
436 system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.51% # Bytes accessed per row activation
437 system.physmem.bytesPerActivate::27648-27655 415 0.46% 79.98% # Bytes accessed per row activation
438 system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.98% # Bytes accessed per row activation
439 system.physmem.bytesPerActivate::27904-27911 83 0.09% 80.07% # Bytes accessed per row activation
440 system.physmem.bytesPerActivate::27968-27975 2 0.00% 80.07% # Bytes accessed per row activation
441 system.physmem.bytesPerActivate::28032-28039 1 0.00% 80.07% # Bytes accessed per row activation
442 system.physmem.bytesPerActivate::28160-28167 75 0.08% 80.16% # Bytes accessed per row activation
443 system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.16% # Bytes accessed per row activation
444 system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.16% # Bytes accessed per row activation
445 system.physmem.bytesPerActivate::28416-28423 159 0.18% 80.34% # Bytes accessed per row activation
446 system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.34% # Bytes accessed per row activation
447 system.physmem.bytesPerActivate::28672-28679 210 0.23% 80.57% # Bytes accessed per row activation
448 system.physmem.bytesPerActivate::28928-28935 77 0.09% 80.66% # Bytes accessed per row activation
449 system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.66% # Bytes accessed per row activation
450 system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.66% # Bytes accessed per row activation
451 system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.76% # Bytes accessed per row activation
452 system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.76% # Bytes accessed per row activation
453 system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.76% # Bytes accessed per row activation
454 system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation
455 system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation
456 system.physmem.bytesPerActivate::29696-29703 347 0.39% 81.30% # Bytes accessed per row activation
457 system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation
458 system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.31% # Bytes accessed per row activation
459 system.physmem.bytesPerActivate::29952-29959 141 0.16% 81.46% # Bytes accessed per row activation
460 system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.47% # Bytes accessed per row activation
461 system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.47% # Bytes accessed per row activation
462 system.physmem.bytesPerActivate::30208-30215 71 0.08% 81.55% # Bytes accessed per row activation
463 system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.55% # Bytes accessed per row activation
464 system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.55% # Bytes accessed per row activation
465 system.physmem.bytesPerActivate::30464-30471 80 0.09% 81.64% # Bytes accessed per row activation
466 system.physmem.bytesPerActivate::30592-30599 2 0.00% 81.64% # Bytes accessed per row activation
467 system.physmem.bytesPerActivate::30720-30727 274 0.31% 81.95% # Bytes accessed per row activation
468 system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.95% # Bytes accessed per row activation
469 system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.95% # Bytes accessed per row activation
470 system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.05% # Bytes accessed per row activation
471 system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.05% # Bytes accessed per row activation
472 system.physmem.bytesPerActivate::31232-31239 90 0.10% 82.15% # Bytes accessed per row activation
473 system.physmem.bytesPerActivate::31488-31495 17 0.02% 82.17% # Bytes accessed per row activation
474 system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.18% # Bytes accessed per row activation
475 system.physmem.bytesPerActivate::31744-31751 485 0.54% 82.72% # Bytes accessed per row activation
476 system.physmem.bytesPerActivate::32000-32007 77 0.09% 82.80% # Bytes accessed per row activation
477 system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.80% # Bytes accessed per row activation
478 system.physmem.bytesPerActivate::32256-32263 143 0.16% 82.96% # Bytes accessed per row activation
479 system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.97% # Bytes accessed per row activation
480 system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.97% # Bytes accessed per row activation
481 system.physmem.bytesPerActivate::32512-32519 84 0.09% 83.06% # Bytes accessed per row activation
482 system.physmem.bytesPerActivate::32768-32775 538 0.60% 83.66% # Bytes accessed per row activation
483 system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.66% # Bytes accessed per row activation
484 system.physmem.bytesPerActivate::33024-33031 86 0.10% 83.76% # Bytes accessed per row activation
485 system.physmem.bytesPerActivate::33280-33287 150 0.17% 83.93% # Bytes accessed per row activation
486 system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% # Bytes accessed per row activation
487 system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation
488 system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation
489 system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation
490 system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.68% # Bytes accessed per row activation
491 system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation
492 system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation
493 system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation
494 system.physmem.bytesPerActivate::34624-34631 3 0.00% 84.79% # Bytes accessed per row activation
495 system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.79% # Bytes accessed per row activation
496 system.physmem.bytesPerActivate::34816-34823 264 0.29% 85.08% # Bytes accessed per row activation
497 system.physmem.bytesPerActivate::35072-35079 79 0.09% 85.17% # Bytes accessed per row activation
498 system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.17% # Bytes accessed per row activation
499 system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.17% # Bytes accessed per row activation
500 system.physmem.bytesPerActivate::35328-35335 71 0.08% 85.25% # Bytes accessed per row activation
501 system.physmem.bytesPerActivate::35392-35399 1 0.00% 85.25% # Bytes accessed per row activation
502 system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.25% # Bytes accessed per row activation
503 system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.42% # Bytes accessed per row activation
504 system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% # Bytes accessed per row activation
505 system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.42% # Bytes accessed per row activation
506 system.physmem.bytesPerActivate::35840-35847 347 0.39% 85.81% # Bytes accessed per row activation
507 system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation
508 system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.96% # Bytes accessed per row activation
509 system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.96% # Bytes accessed per row activation
510 system.physmem.bytesPerActivate::36352-36359 87 0.10% 86.05% # Bytes accessed per row activation
511 system.physmem.bytesPerActivate::36416-36423 1 0.00% 86.05% # Bytes accessed per row activation
512 system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation
513 system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation
514 system.physmem.bytesPerActivate::36608-36615 78 0.09% 86.14% # Bytes accessed per row activation
515 system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.14% # Bytes accessed per row activation
516 system.physmem.bytesPerActivate::36864-36871 204 0.23% 86.37% # Bytes accessed per row activation
517 system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.37% # Bytes accessed per row activation
518 system.physmem.bytesPerActivate::37120-37127 155 0.17% 86.55% # Bytes accessed per row activation
519 system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.55% # Bytes accessed per row activation
520 system.physmem.bytesPerActivate::37376-37383 74 0.08% 86.63% # Bytes accessed per row activation
521 system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.63% # Bytes accessed per row activation
522 system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation
523 system.physmem.bytesPerActivate::37632-37639 89 0.10% 86.73% # Bytes accessed per row activation
524 system.physmem.bytesPerActivate::37888-37895 419 0.47% 87.20% # Bytes accessed per row activation
525 system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.20% # Bytes accessed per row activation
526 system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation
527 system.physmem.bytesPerActivate::38144-38151 18 0.02% 87.23% # Bytes accessed per row activation
528 system.physmem.bytesPerActivate::38400-38407 140 0.16% 87.38% # Bytes accessed per row activation
529 system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.38% # Bytes accessed per row activation
530 system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.46% # Bytes accessed per row activation
531 system.physmem.bytesPerActivate::38848-38855 2 0.00% 87.46% # Bytes accessed per row activation
532 system.physmem.bytesPerActivate::38912-38919 266 0.30% 87.76% # Bytes accessed per row activation
533 system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.76% # Bytes accessed per row activation
534 system.physmem.bytesPerActivate::39168-39175 19 0.02% 87.78% # Bytes accessed per row activation
535 system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.78% # Bytes accessed per row activation
536 system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.79% # Bytes accessed per row activation
537 system.physmem.bytesPerActivate::39424-39431 88 0.10% 87.88% # Bytes accessed per row activation
538 system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.89% # Bytes accessed per row activation
539 system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.89% # Bytes accessed per row activation
540 system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.05% # Bytes accessed per row activation
541 system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.05% # Bytes accessed per row activation
542 system.physmem.bytesPerActivate::39936-39943 410 0.46% 88.51% # Bytes accessed per row activation
543 system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.51% # Bytes accessed per row activation
544 system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.60% # Bytes accessed per row activation
545 system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.60% # Bytes accessed per row activation
546 system.physmem.bytesPerActivate::40448-40455 17 0.02% 88.62% # Bytes accessed per row activation
547 system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.62% # Bytes accessed per row activation
548 system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.71% # Bytes accessed per row activation
549 system.physmem.bytesPerActivate::40960-40967 397 0.44% 89.15% # Bytes accessed per row activation
550 system.physmem.bytesPerActivate::41216-41223 75 0.08% 89.24% # Bytes accessed per row activation
551 system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.24% # Bytes accessed per row activation
552 system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.24% # Bytes accessed per row activation
553 system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.24% # Bytes accessed per row activation
554 system.physmem.bytesPerActivate::41472-41479 24 0.03% 89.27% # Bytes accessed per row activation
555 system.physmem.bytesPerActivate::41600-41607 3 0.00% 89.27% # Bytes accessed per row activation
556 system.physmem.bytesPerActivate::41728-41735 83 0.09% 89.36% # Bytes accessed per row activation
557 system.physmem.bytesPerActivate::41984-41991 408 0.45% 89.82% # Bytes accessed per row activation
558 system.physmem.bytesPerActivate::42240-42247 140 0.16% 89.98% # Bytes accessed per row activation
559 system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.98% # Bytes accessed per row activation
560 system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.07% # Bytes accessed per row activation
561 system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.07% # Bytes accessed per row activation
562 system.physmem.bytesPerActivate::42752-42759 25 0.03% 90.10% # Bytes accessed per row activation
563 system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.39% # Bytes accessed per row activation
564 system.physmem.bytesPerActivate::43136-43143 2 0.00% 90.40% # Bytes accessed per row activation
565 system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation
566 system.physmem.bytesPerActivate::43264-43271 73 0.08% 90.48% # Bytes accessed per row activation
567 system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.48% # Bytes accessed per row activation
568 system.physmem.bytesPerActivate::43520-43527 142 0.16% 90.64% # Bytes accessed per row activation
569 system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.64% # Bytes accessed per row activation
570 system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.64% # Bytes accessed per row activation
571 system.physmem.bytesPerActivate::43776-43783 17 0.02% 90.66% # Bytes accessed per row activation
572 system.physmem.bytesPerActivate::44032-44039 418 0.47% 91.13% # Bytes accessed per row activation
573 system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.13% # Bytes accessed per row activation
574 system.physmem.bytesPerActivate::44288-44295 82 0.09% 91.22% # Bytes accessed per row activation
575 system.physmem.bytesPerActivate::44544-44551 77 0.09% 91.31% # Bytes accessed per row activation
576 system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.31% # Bytes accessed per row activation
577 system.physmem.bytesPerActivate::44800-44807 156 0.17% 91.49% # Bytes accessed per row activation
578 system.physmem.bytesPerActivate::45056-45063 198 0.22% 91.71% # Bytes accessed per row activation
579 system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.71% # Bytes accessed per row activation
580 system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.71% # Bytes accessed per row activation
581 system.physmem.bytesPerActivate::45312-45319 81 0.09% 91.80% # Bytes accessed per row activation
582 system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation
583 system.physmem.bytesPerActivate::45568-45575 90 0.10% 91.90% # Bytes accessed per row activation
584 system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.91% # Bytes accessed per row activation
585 system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation
586 system.physmem.bytesPerActivate::45824-45831 133 0.15% 92.05% # Bytes accessed per row activation
587 system.physmem.bytesPerActivate::45952-45959 2 0.00% 92.06% # Bytes accessed per row activation
588 system.physmem.bytesPerActivate::46080-46087 350 0.39% 92.45% # Bytes accessed per row activation
589 system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation
590 system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.45% # Bytes accessed per row activation
591 system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation
592 system.physmem.bytesPerActivate::46592-46599 72 0.08% 92.69% # Bytes accessed per row activation
593 system.physmem.bytesPerActivate::46720-46727 3 0.00% 92.69% # Bytes accessed per row activation
594 system.physmem.bytesPerActivate::46848-46855 83 0.09% 92.79% # Bytes accessed per row activation
595 system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation
596 system.physmem.bytesPerActivate::47104-47111 266 0.30% 93.09% # Bytes accessed per row activation
597 system.physmem.bytesPerActivate::47360-47367 97 0.11% 93.20% # Bytes accessed per row activation
598 system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.29% # Bytes accessed per row activation
599 system.physmem.bytesPerActivate::47744-47751 5 0.01% 93.30% # Bytes accessed per row activation
600 system.physmem.bytesPerActivate::47872-47879 17 0.02% 93.32% # Bytes accessed per row activation
601 system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.32% # Bytes accessed per row activation
602 system.physmem.bytesPerActivate::48128-48135 515 0.57% 93.89% # Bytes accessed per row activation
603 system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.90% # Bytes accessed per row activation
604 system.physmem.bytesPerActivate::48256-48263 2 0.00% 93.90% # Bytes accessed per row activation
605 system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.90% # Bytes accessed per row activation
606 system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation
607 system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation
608 system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation
609 system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation
610 system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation
611 system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation
612 system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation
613 system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation
614 system.physmem.bytesPerActivate::total 89677 # Bytes accessed per row activation
615 system.physmem.totQLat 373683436750 # Total ticks spent queuing
616 system.physmem.totMemAccLat 469596379250 # Total ticks spent from burst creation until serviced by the DRAM
617 system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers
618 system.physmem.totBankLat 18447687500 # Total ticks spent accessing banks
619 system.physmem.avgQLat 24119.42 # Average queueing delay per DRAM burst
620 system.physmem.avgBankLat 1190.71 # Average bank access latency per DRAM burst
621 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
622 system.physmem.avgMemAccLat 30310.13 # Average memory access latency per DRAM burst
623 system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s
624 system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s
625 system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s
626 system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s
627 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
628 system.physmem.busUtil 2.98 # Data bus utilization in percentage
629 system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
630 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
631 system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
632 system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing
633 system.physmem.readRowHits 15419160 # Number of row buffer hits during reads
634 system.physmem.writeRowHits 91146 # Number of row buffer hits during writes
635 system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
636 system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes
637 system.physmem.avgGap 160458.28 # Average gap between requests
638 system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
639 system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state
640 system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
641 system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
642 system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
643 system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
644 system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
645 system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
646 system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
647 system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
648 system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
649 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
650 system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
651 system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
652 system.membus.throughput 54116520 # Throughput (bytes/s)
653 system.membus.trans_dist::ReadReq 16546551 # Transaction distribution
654 system.membus.trans_dist::ReadResp 16546551 # Transaction distribution
655 system.membus.trans_dist::WriteReq 763368 # Transaction distribution
656 system.membus.trans_dist::WriteResp 763368 # Transaction distribution
657 system.membus.trans_dist::Writeback 57909 # Transaction distribution
658 system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution
659 system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution
660 system.membus.trans_dist::ReadExReq 132216 # Transaction distribution
661 system.membus.trans_dist::ReadExResp 132216 # Transaction distribution
662 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
663 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
664 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
665 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
666 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes)
667 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes)
668 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
669 system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
670 system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes)
671 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
672 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
673 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
674 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
675 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes)
676 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes)
677 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
678 system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
679 system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes)
680 system.membus.data_through_bus 141597849 # Total data (bytes)
681 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
682 system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks)
683 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
684 system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
685 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
686 system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks)
687 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
688 system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
689 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
690 system.membus.reqLayer6.occupancy 17910610000 # Layer occupancy (ticks)
691 system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
692 system.membus.respLayer1.occupancy 4950347835 # Layer occupancy (ticks)
693 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
694 system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks)
695 system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
696 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
697 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
698 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
699 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
700 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
701 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
702 system.iobus.throughput 47801275 # Throughput (bytes/s)
703 system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution
704 system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution
705 system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
706 system.iobus.trans_dist::WriteResp 8166 # Transaction distribution
707 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
708 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
709 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
710 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
711 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
712 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
713 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
714 system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
715 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
716 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
717 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
718 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
719 system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
720 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
721 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
722 system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
723 system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
724 system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
725 system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
726 system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
727 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
728 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
729 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
730 system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes)
731 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
732 system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
733 system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes)
734 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
735 system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
736 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
737 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
738 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
739 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
740 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
741 system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
742 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
743 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
744 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
745 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
746 system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
747 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
748 system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
749 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
750 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
751 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
752 system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
753 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
754 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
755 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
756 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
757 system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes)
758 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
759 system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
760 system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes)
761 system.iobus.data_through_bus 125073781 # Total data (bytes)
762 system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
763 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
764 system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
765 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
766 system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
767 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
768 system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
769 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
770 system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
771 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
772 system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
773 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
774 system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
775 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
776 system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
777 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
778 system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
779 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
780 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
781 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
782 system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
783 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
784 system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
785 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
786 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
787 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
788 system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
789 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
790 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
791 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
792 system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
793 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
794 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
795 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
796 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
797 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
798 system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
799 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
800 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
801 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
802 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
803 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
804 system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
805 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
806 system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
807 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
808 system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
809 system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
810 system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks)
811 system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
812 system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks)
813 system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
814 system.cpu.dtb.inst_hits 0 # ITB inst hits
815 system.cpu.dtb.inst_misses 0 # ITB inst misses
816 system.cpu.dtb.read_hits 14995644 # DTB read hits
817 system.cpu.dtb.read_misses 7334 # DTB read misses
818 system.cpu.dtb.write_hits 11230146 # DTB write hits
819 system.cpu.dtb.write_misses 2212 # DTB write misses
820 system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
821 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
822 system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
823 system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
824 system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB
825 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
826 system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch
827 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
828 system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
829 system.cpu.dtb.read_accesses 15002978 # DTB read accesses
830 system.cpu.dtb.write_accesses 11232358 # DTB write accesses
831 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
832 system.cpu.dtb.hits 26225790 # DTB hits
833 system.cpu.dtb.misses 9546 # DTB misses
834 system.cpu.dtb.accesses 26235336 # DTB accesses
835 system.cpu.itb.inst_hits 61491413 # ITB inst hits
836 system.cpu.itb.inst_misses 4471 # ITB inst misses
837 system.cpu.itb.read_hits 0 # DTB read hits
838 system.cpu.itb.read_misses 0 # DTB read misses
839 system.cpu.itb.write_hits 0 # DTB write hits
840 system.cpu.itb.write_misses 0 # DTB write misses
841 system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
842 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
843 system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
844 system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
845 system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
846 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
847 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
848 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
849 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
850 system.cpu.itb.read_accesses 0 # DTB read accesses
851 system.cpu.itb.write_accesses 0 # DTB write accesses
852 system.cpu.itb.inst_accesses 61495884 # ITB inst accesses
853 system.cpu.itb.hits 61491413 # DTB hits
854 system.cpu.itb.misses 4471 # DTB misses
855 system.cpu.itb.accesses 61495884 # DTB accesses
856 system.cpu.numCycles 5233072966 # number of cpu cycles simulated
857 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
858 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
859 system.cpu.committedInsts 60197580 # Number of instructions committed
860 system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed
861 system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses
862 system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
863 system.cpu.num_func_calls 2140403 # number of times a function call or return occured
864 system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls
865 system.cpu.num_int_insts 68871033 # number of integer instructions
866 system.cpu.num_fp_insts 10269 # number of float instructions
867 system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read
868 system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written
869 system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
870 system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
871 system.cpu.num_mem_refs 27393280 # number of memory refs
872 system.cpu.num_load_insts 15659727 # Number of load instructions
873 system.cpu.num_store_insts 11733553 # Number of store instructions
874 system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles
875 system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles
876 system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles
877 system.cpu.idle_fraction 0.875495 # Percentage of idle cycles
878 system.cpu.kern.inst.arm 0 # number of arm instructions executed
879 system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed
880 system.cpu.icache.tags.replacements 856260 # number of replacements
881 system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use
882 system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks.
883 system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks.
884 system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks.
885 system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit.
886 system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor
887 system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy
888 system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy
889 system.cpu.icache.ReadReq_hits::cpu.inst 60634641 # number of ReadReq hits
890 system.cpu.icache.ReadReq_hits::total 60634641 # number of ReadReq hits
891 system.cpu.icache.demand_hits::cpu.inst 60634641 # number of demand (read+write) hits
892 system.cpu.icache.demand_hits::total 60634641 # number of demand (read+write) hits
893 system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits
894 system.cpu.icache.overall_hits::total 60634641 # number of overall hits
895 system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses
896 system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses
897 system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses
898 system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses
899 system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses
900 system.cpu.icache.overall_misses::total 856772 # number of overall misses
901 system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773713250 # number of ReadReq miss cycles
902 system.cpu.icache.ReadReq_miss_latency::total 11773713250 # number of ReadReq miss cycles
903 system.cpu.icache.demand_miss_latency::cpu.inst 11773713250 # number of demand (read+write) miss cycles
904 system.cpu.icache.demand_miss_latency::total 11773713250 # number of demand (read+write) miss cycles
905 system.cpu.icache.overall_miss_latency::cpu.inst 11773713250 # number of overall miss cycles
906 system.cpu.icache.overall_miss_latency::total 11773713250 # number of overall miss cycles
907 system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses)
908 system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses)
909 system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses
910 system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses
911 system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses
912 system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses
913 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses
914 system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses
915 system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses
916 system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses
917 system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses
918 system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses
919 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.944473 # average ReadReq miss latency
920 system.cpu.icache.ReadReq_avg_miss_latency::total 13741.944473 # average ReadReq miss latency
921 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency
922 system.cpu.icache.demand_avg_miss_latency::total 13741.944473 # average overall miss latency
923 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency
924 system.cpu.icache.overall_avg_miss_latency::total 13741.944473 # average overall miss latency
925 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
926 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
927 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
928 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
929 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
930 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
931 system.cpu.icache.fast_writes 0 # number of fast writes performed
932 system.cpu.icache.cache_copies 0 # number of cache copies performed
933 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses
934 system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses
935 system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses
936 system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses
937 system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses
938 system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses
939 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056122750 # number of ReadReq MSHR miss cycles
940 system.cpu.icache.ReadReq_mshr_miss_latency::total 10056122750 # number of ReadReq MSHR miss cycles
941 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056122750 # number of demand (read+write) MSHR miss cycles
942 system.cpu.icache.demand_mshr_miss_latency::total 10056122750 # number of demand (read+write) MSHR miss cycles
943 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056122750 # number of overall MSHR miss cycles
944 system.cpu.icache.overall_mshr_miss_latency::total 10056122750 # number of overall MSHR miss cycles
945 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles
946 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles
947 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles
948 system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles
949 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses
950 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses
951 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses
952 system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses
953 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses
954 system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses
955 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.221513 # average ReadReq mshr miss latency
956 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.221513 # average ReadReq mshr miss latency
957 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency
958 system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency
959 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency
960 system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency
961 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
962 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
963 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
964 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
965 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
966 system.cpu.l2cache.tags.replacements 62509 # number of replacements
967 system.cpu.l2cache.tags.tagsinuse 50754.670351 # Cycle average of tags in use
968 system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks.
969 system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks.
970 system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks.
971 system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit.
972 system.cpu.l2cache.tags.occ_blocks::writebacks 37718.407530 # Average occupied blocks per requestor
973 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor
974 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor
975 system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400299 # Average occupied blocks per requestor
976 system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977449 # Average occupied blocks per requestor
977 system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy
978 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
979 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
980 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy
981 system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy
982 system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy
983 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits
984 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits
985 system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits
986 system.cpu.l2cache.ReadReq_hits::cpu.data 369631 # number of ReadReq hits
987 system.cpu.l2cache.ReadReq_hits::total 1226419 # number of ReadReq hits
988 system.cpu.l2cache.Writeback_hits::writebacks 595233 # number of Writeback hits
989 system.cpu.l2cache.Writeback_hits::total 595233 # number of Writeback hits
990 system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
991 system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
992 system.cpu.l2cache.ReadExReq_hits::cpu.data 113388 # number of ReadExReq hits
993 system.cpu.l2cache.ReadExReq_hits::total 113388 # number of ReadExReq hits
994 system.cpu.l2cache.demand_hits::cpu.dtb.walker 8705 # number of demand (read+write) hits
995 system.cpu.l2cache.demand_hits::cpu.itb.walker 3532 # number of demand (read+write) hits
996 system.cpu.l2cache.demand_hits::cpu.inst 844551 # number of demand (read+write) hits
997 system.cpu.l2cache.demand_hits::cpu.data 483019 # number of demand (read+write) hits
998 system.cpu.l2cache.demand_hits::total 1339807 # number of demand (read+write) hits
999 system.cpu.l2cache.overall_hits::cpu.dtb.walker 8705 # number of overall hits
1000 system.cpu.l2cache.overall_hits::cpu.itb.walker 3532 # number of overall hits
1001 system.cpu.l2cache.overall_hits::cpu.inst 844551 # number of overall hits
1002 system.cpu.l2cache.overall_hits::cpu.data 483019 # number of overall hits
1003 system.cpu.l2cache.overall_hits::total 1339807 # number of overall hits
1004 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
1005 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
1006 system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses
1007 system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses
1008 system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses
1009 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2908 # number of UpgradeReq misses
1010 system.cpu.l2cache.UpgradeReq_misses::total 2908 # number of UpgradeReq misses
1011 system.cpu.l2cache.ReadExReq_misses::cpu.data 133823 # number of ReadExReq misses
1012 system.cpu.l2cache.ReadExReq_misses::total 133823 # number of ReadExReq misses
1013 system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
1014 system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
1015 system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses
1016 system.cpu.l2cache.demand_misses::cpu.data 143632 # number of demand (read+write) misses
1017 system.cpu.l2cache.demand_misses::total 154224 # number of demand (read+write) misses
1018 system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
1019 system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
1020 system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses
1021 system.cpu.l2cache.overall_misses::cpu.data 143632 # number of overall misses
1022 system.cpu.l2cache.overall_misses::total 154224 # number of overall misses
1023 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles
1024 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles
1025 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752204750 # number of ReadReq miss cycles
1026 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 737637250 # number of ReadReq miss cycles
1027 system.cpu.l2cache.ReadReq_miss_latency::total 1490297250 # number of ReadReq miss cycles
1028 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles
1029 system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles
1030 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9620282393 # number of ReadExReq miss cycles
1031 system.cpu.l2cache.ReadExReq_miss_latency::total 9620282393 # number of ReadExReq miss cycles
1032 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles
1033 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles
1034 system.cpu.l2cache.demand_miss_latency::cpu.inst 752204750 # number of demand (read+write) miss cycles
1035 system.cpu.l2cache.demand_miss_latency::cpu.data 10357919643 # number of demand (read+write) miss cycles
1036 system.cpu.l2cache.demand_miss_latency::total 11110579643 # number of demand (read+write) miss cycles
1037 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles
1038 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles
1039 system.cpu.l2cache.overall_miss_latency::cpu.inst 752204750 # number of overall miss cycles
1040 system.cpu.l2cache.overall_miss_latency::cpu.data 10357919643 # number of overall miss cycles
1041 system.cpu.l2cache.overall_miss_latency::total 11110579643 # number of overall miss cycles
1042 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses)
1043 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses)
1044 system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses)
1045 system.cpu.l2cache.ReadReq_accesses::cpu.data 379440 # number of ReadReq accesses(hits+misses)
1046 system.cpu.l2cache.ReadReq_accesses::total 1246820 # number of ReadReq accesses(hits+misses)
1047 system.cpu.l2cache.Writeback_accesses::writebacks 595233 # number of Writeback accesses(hits+misses)
1048 system.cpu.l2cache.Writeback_accesses::total 595233 # number of Writeback accesses(hits+misses)
1049 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2934 # number of UpgradeReq accesses(hits+misses)
1050 system.cpu.l2cache.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses)
1051 system.cpu.l2cache.ReadExReq_accesses::cpu.data 247211 # number of ReadExReq accesses(hits+misses)
1052 system.cpu.l2cache.ReadExReq_accesses::total 247211 # number of ReadExReq accesses(hits+misses)
1053 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8710 # number of demand (read+write) accesses
1054 system.cpu.l2cache.demand_accesses::cpu.itb.walker 3534 # number of demand (read+write) accesses
1055 system.cpu.l2cache.demand_accesses::cpu.inst 855136 # number of demand (read+write) accesses
1056 system.cpu.l2cache.demand_accesses::cpu.data 626651 # number of demand (read+write) accesses
1057 system.cpu.l2cache.demand_accesses::total 1494031 # number of demand (read+write) accesses
1058 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8710 # number of overall (read+write) accesses
1059 system.cpu.l2cache.overall_accesses::cpu.itb.walker 3534 # number of overall (read+write) accesses
1060 system.cpu.l2cache.overall_accesses::cpu.inst 855136 # number of overall (read+write) accesses
1061 system.cpu.l2cache.overall_accesses::cpu.data 626651 # number of overall (read+write) accesses
1062 system.cpu.l2cache.overall_accesses::total 1494031 # number of overall (read+write) accesses
1063 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
1064 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses
1065 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses
1066 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 # miss rate for ReadReq accesses
1067 system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses
1068 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991138 # miss rate for UpgradeReq accesses
1069 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991138 # miss rate for UpgradeReq accesses
1070 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541331 # miss rate for ReadExReq accesses
1071 system.cpu.l2cache.ReadExReq_miss_rate::total 0.541331 # miss rate for ReadExReq accesses
1072 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
1073 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses
1074 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses
1075 system.cpu.l2cache.demand_miss_rate::cpu.data 0.229206 # miss rate for demand accesses
1076 system.cpu.l2cache.demand_miss_rate::total 0.103227 # miss rate for demand accesses
1077 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
1078 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses
1079 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses
1080 system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 # miss rate for overall accesses
1081 system.cpu.l2cache.overall_miss_rate::total 0.103227 # miss rate for overall accesses
1082 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency
1083 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency
1084 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71063.273500 # average ReadReq miss latency
1085 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75200.045876 # average ReadReq miss latency
1086 system.cpu.l2cache.ReadReq_avg_miss_latency::total 73050.205872 # average ReadReq miss latency
1087 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency
1088 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency
1089 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71888.108868 # average ReadExReq miss latency
1090 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71888.108868 # average ReadExReq miss latency
1091 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
1092 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
1093 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency
1094 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency
1095 system.cpu.l2cache.demand_avg_miss_latency::total 72041.832938 # average overall miss latency
1096 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
1097 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
1098 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency
1099 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency
1100 system.cpu.l2cache.overall_avg_miss_latency::total 72041.832938 # average overall miss latency
1101 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1102 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1103 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1104 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1105 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1106 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1107 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1108 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1109 system.cpu.l2cache.writebacks::writebacks 57909 # number of writebacks
1110 system.cpu.l2cache.writebacks::total 57909 # number of writebacks
1111 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
1112 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1113 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses
1114 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses
1115 system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses
1116 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2908 # number of UpgradeReq MSHR misses
1117 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses
1118 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133823 # number of ReadExReq MSHR misses
1119 system.cpu.l2cache.ReadExReq_mshr_misses::total 133823 # number of ReadExReq MSHR misses
1120 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
1121 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1122 system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses
1123 system.cpu.l2cache.demand_mshr_misses::cpu.data 143632 # number of demand (read+write) MSHR misses
1124 system.cpu.l2cache.demand_mshr_misses::total 154224 # number of demand (read+write) MSHR misses
1125 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
1126 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
1127 system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses
1128 system.cpu.l2cache.overall_mshr_misses::cpu.data 143632 # number of overall MSHR misses
1129 system.cpu.l2cache.overall_mshr_misses::total 154224 # number of overall MSHR misses
1130 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles
1131 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
1132 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619637750 # number of ReadReq MSHR miss cycles
1133 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614753750 # number of ReadReq MSHR miss cycles
1134 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1234759250 # number of ReadReq MSHR miss cycles
1135 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles
1136 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles
1137 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7945647607 # number of ReadExReq MSHR miss cycles
1138 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7945647607 # number of ReadExReq MSHR miss cycles
1139 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles
1140 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
1141 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619637750 # number of demand (read+write) MSHR miss cycles
1142 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8560401357 # number of demand (read+write) MSHR miss cycles
1143 system.cpu.l2cache.demand_mshr_miss_latency::total 9180406857 # number of demand (read+write) MSHR miss cycles
1144 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles
1145 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
1146 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619637750 # number of overall MSHR miss cycles
1147 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8560401357 # number of overall MSHR miss cycles
1148 system.cpu.l2cache.overall_mshr_miss_latency::total 9180406857 # number of overall MSHR miss cycles
1149 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 343871250 # number of ReadReq MSHR uncacheable cycles
1150 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166656947250 # number of ReadReq MSHR uncacheable cycles
1151 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167000818500 # number of ReadReq MSHR uncacheable cycles
1152 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635150 # number of WriteReq MSHR uncacheable cycles
1153 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635150 # number of WriteReq MSHR uncacheable cycles
1154 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 343871250 # number of overall MSHR uncacheable cycles
1155 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582400 # number of overall MSHR uncacheable cycles
1156 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703453650 # number of overall MSHR uncacheable cycles
1157 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
1158 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses
1159 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses
1160 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses
1161 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses
1162 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses
1163 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses
1164 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541331 # mshr miss rate for ReadExReq accesses
1165 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541331 # mshr miss rate for ReadExReq accesses
1166 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
1167 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses
1168 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses
1169 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for demand accesses
1170 system.cpu.l2cache.demand_mshr_miss_rate::total 0.103227 # mshr miss rate for demand accesses
1171 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
1172 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses
1173 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses
1174 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses
1175 system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses
1176 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency
1177 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
1178 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58539.230043 # average ReadReq mshr miss latency
1179 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62672.418187 # average ReadReq mshr miss latency
1180 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60524.447331 # average ReadReq mshr miss latency
1181 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency
1182 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency
1183 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59374.304918 # average ReadExReq mshr miss latency
1184 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59374.304918 # average ReadExReq mshr miss latency
1185 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
1186 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
1187 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency
1188 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency
1189 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency
1190 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
1191 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
1192 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency
1193 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency
1194 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency
1195 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1196 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1197 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1198 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1199 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1200 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1201 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1202 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1203 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1204 system.cpu.dcache.tags.replacements 626139 # number of replacements
1205 system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use
1206 system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks.
1207 system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks.
1208 system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks.
1209 system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit.
1210 system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor
1211 system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy
1212 system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy
1213 system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits
1214 system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits
1215 system.cpu.dcache.WriteReq_hits::cpu.data 9972594 # number of WriteReq hits
1216 system.cpu.dcache.WriteReq_hits::total 9972594 # number of WriteReq hits
1217 system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits
1218 system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits
1219 system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits
1220 system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits
1221 system.cpu.dcache.demand_hits::cpu.data 23168335 # number of demand (read+write) hits
1222 system.cpu.dcache.demand_hits::total 23168335 # number of demand (read+write) hits
1223 system.cpu.dcache.overall_hits::cpu.data 23168335 # number of overall hits
1224 system.cpu.dcache.overall_hits::total 23168335 # number of overall hits
1225 system.cpu.dcache.ReadReq_misses::cpu.data 368054 # number of ReadReq misses
1226 system.cpu.dcache.ReadReq_misses::total 368054 # number of ReadReq misses
1227 system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses
1228 system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses
1229 system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses
1230 system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses
1231 system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses
1232 system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses
1233 system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses
1234 system.cpu.dcache.overall_misses::total 618199 # number of overall misses
1235 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416240000 # number of ReadReq miss cycles
1236 system.cpu.dcache.ReadReq_miss_latency::total 5416240000 # number of ReadReq miss cycles
1237 system.cpu.dcache.WriteReq_miss_latency::cpu.data 11622215515 # number of WriteReq miss cycles
1238 system.cpu.dcache.WriteReq_miss_latency::total 11622215515 # number of WriteReq miss cycles
1239 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158376750 # number of LoadLockedReq miss cycles
1240 system.cpu.dcache.LoadLockedReq_miss_latency::total 158376750 # number of LoadLockedReq miss cycles
1241 system.cpu.dcache.demand_miss_latency::cpu.data 17038455515 # number of demand (read+write) miss cycles
1242 system.cpu.dcache.demand_miss_latency::total 17038455515 # number of demand (read+write) miss cycles
1243 system.cpu.dcache.overall_miss_latency::cpu.data 17038455515 # number of overall miss cycles
1244 system.cpu.dcache.overall_miss_latency::total 17038455515 # number of overall miss cycles
1245 system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses)
1246 system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses)
1247 system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses)
1248 system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses)
1249 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses)
1250 system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses)
1251 system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses)
1252 system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses)
1253 system.cpu.dcache.demand_accesses::cpu.data 23786534 # number of demand (read+write) accesses
1254 system.cpu.dcache.demand_accesses::total 23786534 # number of demand (read+write) accesses
1255 system.cpu.dcache.overall_accesses::cpu.data 23786534 # number of overall (read+write) accesses
1256 system.cpu.dcache.overall_accesses::total 23786534 # number of overall (read+write) accesses
1257 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses
1258 system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses
1259 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses
1260 system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses
1261 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses
1262 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses
1263 system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses
1264 system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses
1265 system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses
1266 system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses
1267 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14715.884082 # average ReadReq miss latency
1268 system.cpu.dcache.ReadReq_avg_miss_latency::total 14715.884082 # average ReadReq miss latency
1269 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46461.914150 # average WriteReq miss latency
1270 system.cpu.dcache.WriteReq_avg_miss_latency::total 46461.914150 # average WriteReq miss latency
1271 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.779554 # average LoadLockedReq miss latency
1272 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.779554 # average LoadLockedReq miss latency
1273 system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency
1274 system.cpu.dcache.demand_avg_miss_latency::total 27561.441405 # average overall miss latency
1275 system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency
1276 system.cpu.dcache.overall_avg_miss_latency::total 27561.441405 # average overall miss latency
1277 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1278 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1279 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1280 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1281 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1282 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1283 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1284 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1285 system.cpu.dcache.writebacks::writebacks 595233 # number of writebacks
1286 system.cpu.dcache.writebacks::total 595233 # number of writebacks
1287 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368054 # number of ReadReq MSHR misses
1288 system.cpu.dcache.ReadReq_mshr_misses::total 368054 # number of ReadReq MSHR misses
1289 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses
1290 system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses
1291 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses
1292 system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses
1293 system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses
1294 system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses
1295 system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses
1296 system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses
1297 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677837000 # number of ReadReq MSHR miss cycles
1298 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677837000 # number of ReadReq MSHR miss cycles
1299 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069989485 # number of WriteReq MSHR miss cycles
1300 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069989485 # number of WriteReq MSHR miss cycles
1301 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135550250 # number of LoadLockedReq MSHR miss cycles
1302 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135550250 # number of LoadLockedReq MSHR miss cycles
1303 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747826485 # number of demand (read+write) MSHR miss cycles
1304 system.cpu.dcache.demand_mshr_miss_latency::total 15747826485 # number of demand (read+write) MSHR miss cycles
1305 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747826485 # number of overall MSHR miss cycles
1306 system.cpu.dcache.overall_mshr_miss_latency::total 15747826485 # number of overall MSHR miss cycles
1307 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles
1308 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles
1309 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles
1310 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles
1311 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles
1312 system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles
1313 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses
1314 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses
1315 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses
1316 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses
1317 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses
1318 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses
1319 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses
1320 system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses
1321 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses
1322 system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses
1323 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12709.648584 # average ReadReq mshr miss latency
1324 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12709.648584 # average ReadReq mshr miss latency
1325 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44254.290452 # average WriteReq mshr miss latency
1326 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44254.290452 # average WriteReq mshr miss latency
1327 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.992974 # average LoadLockedReq mshr miss latency
1328 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.992974 # average LoadLockedReq mshr miss latency
1329 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency
1330 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency
1331 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency
1332 system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency
1333 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1334 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1335 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1336 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1337 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1338 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1339 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1340 system.cpu.toL2Bus.throughput 52965193 # Throughput (bytes/s)
1341 system.cpu.toL2Bus.trans_dist::ReadReq 2454584 # Transaction distribution
1342 system.cpu.toL2Bus.trans_dist::ReadResp 2454584 # Transaction distribution
1343 system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
1344 system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
1345 system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution
1346 system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution
1347 system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution
1348 system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution
1349 system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution
1350 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725150 # Packet count per connected master and slave (bytes)
1351 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749349 # Packet count per connected master and slave (bytes)
1352 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes)
1353 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes)
1354 system.cpu.toL2Bus.pkt_count::total 7514389 # Packet count per connected master and slave (bytes)
1355 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755188 # Cumulative packet size per connected master and slave (bytes)
1356 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614885 # Cumulative packet size per connected master and slave (bytes)
1357 system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes)
1358 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes)
1359 system.cpu.toL2Bus.tot_pkt_size::total 138419049 # Cumulative packet size per connected master and slave (bytes)
1360 system.cpu.toL2Bus.data_through_bus 138419049 # Total data (bytes)
1361 system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes)
1362 system.cpu.toL2Bus.reqLayer0.occupancy 3008582500 # Layer occupancy (ticks)
1363 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1364 system.cpu.toL2Bus.respLayer0.occupancy 1295439000 # Layer occupancy (ticks)
1365 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1366 system.cpu.toL2Bus.respLayer1.occupancy 2534381165 # Layer occupancy (ticks)
1367 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1368 system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
1369 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1370 system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks)
1371 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1372 system.iocache.tags.replacements 0 # number of replacements
1373 system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
1374 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1375 system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
1376 system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
1377 system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1378 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1379 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1380 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1381 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1382 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1383 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1384 system.iocache.fast_writes 0 # number of fast writes performed
1385 system.iocache.cache_copies 0 # number of cache copies performed
1386 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of ReadReq MSHR uncacheable cycles
1387 system.iocache.ReadReq_mshr_uncacheable_latency::total 1538393065750 # number of ReadReq MSHR uncacheable cycles
1388 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of overall MSHR uncacheable cycles
1389 system.iocache.overall_mshr_uncacheable_latency::total 1538393065750 # number of overall MSHR uncacheable cycles
1390 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1391 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1392 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1393 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1394 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1396 ---------- End Simulation Statistics ----------
projects / gem5.git / blob