2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.909596 # Number of seconds simulated
4 sim_ticks 2909596171500 # Number of ticks simulated
5 final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 612420 # Simulator instruction rate (inst/s)
8 host_op_rate 738388 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 15845377688 # Simulator tick rate (ticks/s)
10 host_mem_usage 579872 # Number of bytes of host memory used
11 host_seconds 183.62 # Real time elapsed on the host
12 sim_insts 112455206 # Number of instructions simulated
13 sim_ops 135585876 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 8901796 # Number of bytes read from this memory
20 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory
27 system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 139610 # Number of read requests responded to by this memory
31 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory
34 system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.inst 407756 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.data 3059461 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 3467744 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 407756 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 407756 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 2581758 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 2587780 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 2581758 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.inst 407756 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.data 3065484 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 6055525 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.readReqs 166625 # Number of read requests accepted
55 system.physmem.writeReqs 121754 # Number of write requests accepted
56 system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue
57 system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue
58 system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM
59 system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
60 system.physmem.bytesWritten 7541952 # Total number of bytes written to DRAM
61 system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side
62 system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side
63 system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue
64 system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
65 system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write
66 system.physmem.perBankRdBursts::0 10077 # Per bank write bursts
67 system.physmem.perBankRdBursts::1 9979 # Per bank write bursts
68 system.physmem.perBankRdBursts::2 10695 # Per bank write bursts
69 system.physmem.perBankRdBursts::3 10661 # Per bank write bursts
70 system.physmem.perBankRdBursts::4 18797 # Per bank write bursts
71 system.physmem.perBankRdBursts::5 9659 # Per bank write bursts
72 system.physmem.perBankRdBursts::6 9663 # Per bank write bursts
73 system.physmem.perBankRdBursts::7 10485 # Per bank write bursts
74 system.physmem.perBankRdBursts::8 9276 # Per bank write bursts
75 system.physmem.perBankRdBursts::9 9973 # Per bank write bursts
76 system.physmem.perBankRdBursts::10 9232 # Per bank write bursts
77 system.physmem.perBankRdBursts::11 8679 # Per bank write bursts
78 system.physmem.perBankRdBursts::12 9817 # Per bank write bursts
79 system.physmem.perBankRdBursts::13 10379 # Per bank write bursts
80 system.physmem.perBankRdBursts::14 9722 # Per bank write bursts
81 system.physmem.perBankRdBursts::15 9413 # Per bank write bursts
82 system.physmem.perBankWrBursts::0 7393 # Per bank write bursts
83 system.physmem.perBankWrBursts::1 7263 # Per bank write bursts
84 system.physmem.perBankWrBursts::2 8282 # Per bank write bursts
85 system.physmem.perBankWrBursts::3 8171 # Per bank write bursts
86 system.physmem.perBankWrBursts::4 7489 # Per bank write bursts
87 system.physmem.perBankWrBursts::5 7265 # Per bank write bursts
88 system.physmem.perBankWrBursts::6 7108 # Per bank write bursts
89 system.physmem.perBankWrBursts::7 7659 # Per bank write bursts
90 system.physmem.perBankWrBursts::8 7080 # Per bank write bursts
91 system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
92 system.physmem.perBankWrBursts::10 6695 # Per bank write bursts
93 system.physmem.perBankWrBursts::11 6470 # Per bank write bursts
94 system.physmem.perBankWrBursts::12 7534 # Per bank write bursts
95 system.physmem.perBankWrBursts::13 7859 # Per bank write bursts
96 system.physmem.perBankWrBursts::14 7264 # Per bank write bursts
97 system.physmem.perBankWrBursts::15 6788 # Per bank write bursts
98 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99 system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
100 system.physmem.totGap 2909595814500 # Total gap between requests
101 system.physmem.readPktSize::0 0 # Read request sizes (log2)
102 system.physmem.readPktSize::1 0 # Read request sizes (log2)
103 system.physmem.readPktSize::2 9558 # Read request sizes (log2)
104 system.physmem.readPktSize::3 14 # Read request sizes (log2)
105 system.physmem.readPktSize::4 0 # Read request sizes (log2)
106 system.physmem.readPktSize::5 0 # Read request sizes (log2)
107 system.physmem.readPktSize::6 157053 # Read request sizes (log2)
108 system.physmem.writePktSize::0 0 # Write request sizes (log2)
109 system.physmem.writePktSize::1 0 # Write request sizes (log2)
110 system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111 system.physmem.writePktSize::3 0 # Write request sizes (log2)
112 system.physmem.writePktSize::4 0 # Write request sizes (log2)
113 system.physmem.writePktSize::5 0 # Write request sizes (log2)
114 system.physmem.writePktSize::6 117373 # Write request sizes (log2)
115 system.physmem.rdQLenPdf::0 165628 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::15 2125 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::16 2431 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::17 5974 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::18 5923 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::19 6296 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::20 6381 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::21 7297 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::23 7756 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::24 7889 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::25 7774 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::26 9310 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::27 7123 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::29 6775 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::30 6274 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::32 5950 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::39 93 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::46 86 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::53 91 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::56 54 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
211 system.physmem.bytesPerActivate::samples 58778 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::mean 309.611351 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::gmean 182.749688 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::stdev 329.493771 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::0-127 21450 36.49% 36.49% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::128-255 14701 25.01% 61.50% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::256-383 6086 10.35% 71.86% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::384-511 3214 5.47% 77.33% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::512-639 2550 4.34% 81.66% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::640-767 1476 2.51% 84.18% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-895 1054 1.79% 85.97% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::896-1023 1089 1.85% 87.82% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1024-1151 7158 12.18% 100.00% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::total 58778 # Bytes accessed per row activation
225 system.physmem.rdPerTurnAround::samples 5758 # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::mean 28.915596 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::stdev 590.311059 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::0-2047 5757 99.98% 99.98% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::total 5758 # Reads before turning the bus around for writes
231 system.physmem.wrPerTurnAround::samples 5758 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::mean 20.465960 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::gmean 18.711564 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::stdev 13.116644 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::16-19 4961 86.16% 86.16% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::20-23 87 1.51% 87.67% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::24-27 33 0.57% 88.24% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::28-31 172 2.99% 91.23% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::32-35 23 0.40% 91.63% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::36-39 160 2.78% 94.41% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::40-43 50 0.87% 95.28% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::44-47 6 0.10% 95.38% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::48-51 7 0.12% 95.50% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::52-55 22 0.38% 95.88% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::56-59 2 0.03% 95.92% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::60-63 6 0.10% 96.02% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::64-67 163 2.83% 98.85% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::68-71 3 0.05% 98.91% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::72-75 10 0.17% 99.08% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::76-79 20 0.35% 99.43% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::88-91 1 0.02% 99.48% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::100-103 1 0.02% 99.50% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::108-111 2 0.03% 99.53% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::128-131 16 0.28% 99.86% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::total 5758 # Writes before turning the bus around for reads
267 system.physmem.totQLat 1616458000 # Total ticks spent queuing
268 system.physmem.totMemAccLat 4738464250 # Total ticks spent from burst creation until serviced by the DRAM
269 system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers
270 system.physmem.avgQLat 9708.05 # Average queueing delay per DRAM burst
271 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
272 system.physmem.avgMemAccLat 28458.05 # Average memory access latency per DRAM burst
273 system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
274 system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
275 system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
276 system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
277 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
278 system.physmem.busUtil 0.05 # Data bus utilization in percentage
279 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
280 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
281 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
282 system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing
283 system.physmem.readRowHits 136072 # Number of row buffer hits during reads
284 system.physmem.writeRowHits 89499 # Number of row buffer hits during writes
285 system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads
286 system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes
287 system.physmem.avgGap 10089485.76 # Average gap between requests
288 system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined
289 system.physmem_0.actEnergy 230958000 # Energy for activate commands per rank (pJ)
290 system.physmem_0.preEnergy 126018750 # Energy for precharge commands per rank (pJ)
291 system.physmem_0.readEnergy 702124800 # Energy for read commands per rank (pJ)
292 system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ)
293 system.physmem_0.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ)
294 system.physmem_0.actBackEnergy 90366604425 # Energy for active background per rank (pJ)
295 system.physmem_0.preBackEnergy 1666484751750 # Energy for precharge background per rank (pJ)
296 system.physmem_0.totalEnergy 1948343566605 # Total energy per rank (pJ)
297 system.physmem_0.averagePower 669.628332 # Core power per rank (mW)
298 system.physmem_0.memoryStateTime::IDLE 2772164122000 # Time in different power states
299 system.physmem_0.memoryStateTime::REF 97157580000 # Time in different power states
300 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
301 system.physmem_0.memoryStateTime::ACT 40267816750 # Time in different power states
302 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
303 system.physmem_1.actEnergy 213403680 # Energy for activate commands per rank (pJ)
304 system.physmem_1.preEnergy 116440500 # Energy for precharge commands per rank (pJ)
305 system.physmem_1.readEnergy 596622000 # Energy for read commands per rank (pJ)
306 system.physmem_1.writeEnergy 370740240 # Energy for write commands per rank (pJ)
307 system.physmem_1.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ)
308 system.physmem_1.actBackEnergy 88072375230 # Energy for active background per rank (pJ)
309 system.physmem_1.preBackEnergy 1668497233500 # Energy for precharge background per rank (pJ)
310 system.physmem_1.totalEnergy 1947907041630 # Total energy per rank (pJ)
311 system.physmem_1.averagePower 669.478302 # Core power per rank (mW)
312 system.physmem_1.memoryStateTime::IDLE 2775541834250 # Time in different power states
313 system.physmem_1.memoryStateTime::REF 97157580000 # Time in different power states
314 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
315 system.physmem_1.memoryStateTime::ACT 36896609250 # Time in different power states
316 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
317 system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
318 system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
319 system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
320 system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
321 system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
322 system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
323 system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
324 system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
325 system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
326 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
327 system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
328 system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
329 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
330 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
331 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
332 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
333 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
334 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
335 system.cpu_clk_domain.clock 500 # Clock period in ticks
336 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
337 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
338 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
339 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
340 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
341 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
342 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
343 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
344 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
345 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
346 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
347 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
348 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
349 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
350 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
351 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
352 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
353 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
354 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
355 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
356 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
357 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
358 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
359 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
360 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
361 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
362 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
363 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
364 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
365 system.cpu.dtb.walker.walks 9546 # Table walker walks requested
366 system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors
367 system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate
368 system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate
369 system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency
370 system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency
371 system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency
372 system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency
373 system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982 # Table walker service (enqueue to completion) latency
374 system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330 # Table walker service (enqueue to completion) latency
375 system.cpu.dtb.walker.walkCompletionTime::stdev 8540.848722 # Table walker service (enqueue to completion) latency
376 system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency
377 system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
378 system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
379 system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency
380 system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution
381 system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution
382 system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution
383 system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated
384 system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated
385 system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated
386 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst
387 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
388 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst
389 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst
390 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
391 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst
392 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst
393 system.cpu.dtb.inst_hits 0 # ITB inst hits
394 system.cpu.dtb.inst_misses 0 # ITB inst misses
395 system.cpu.dtb.read_hits 24520178 # DTB read hits
396 system.cpu.dtb.read_misses 8124 # DTB read misses
397 system.cpu.dtb.write_hits 19606457 # DTB write hits
398 system.cpu.dtb.write_misses 1422 # DTB write misses
399 system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
400 system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
401 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
402 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
403 system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
404 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
405 system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch
406 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
407 system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
408 system.cpu.dtb.read_accesses 24528302 # DTB read accesses
409 system.cpu.dtb.write_accesses 19607879 # DTB write accesses
410 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
411 system.cpu.dtb.hits 44126635 # DTB hits
412 system.cpu.dtb.misses 9546 # DTB misses
413 system.cpu.dtb.accesses 44136181 # DTB accesses
414 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
415 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
416 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
417 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
418 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
419 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
420 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
421 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
422 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
423 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
424 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
425 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
426 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
427 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
428 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
429 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
430 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
431 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
432 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
433 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
434 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
435 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
436 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
437 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
438 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
439 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
440 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
441 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
442 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
443 system.cpu.itb.walker.walks 4763 # Table walker walks requested
444 system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
445 system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
446 system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
447 system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
448 system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
449 system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
450 system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
451 system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency
452 system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency
453 system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency
454 system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency
455 system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency
456 system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
457 system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
458 system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution
459 system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution
460 system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution
461 system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
462 system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
463 system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
464 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
465 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
466 system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
467 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
468 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
469 system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
470 system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
471 system.cpu.itb.inst_hits 115552414 # ITB inst hits
472 system.cpu.itb.inst_misses 4763 # ITB inst misses
473 system.cpu.itb.read_hits 0 # DTB read hits
474 system.cpu.itb.read_misses 0 # DTB read misses
475 system.cpu.itb.write_hits 0 # DTB write hits
476 system.cpu.itb.write_misses 0 # DTB write misses
477 system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
478 system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
479 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
480 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
481 system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
482 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
483 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
484 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
485 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
486 system.cpu.itb.read_accesses 0 # DTB read accesses
487 system.cpu.itb.write_accesses 0 # DTB write accesses
488 system.cpu.itb.inst_accesses 115557177 # ITB inst accesses
489 system.cpu.itb.hits 115552414 # DTB hits
490 system.cpu.itb.misses 4763 # DTB misses
491 system.cpu.itb.accesses 115557177 # DTB accesses
492 system.cpu.numCycles 5819192343 # number of cpu cycles simulated
493 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
494 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
495 system.cpu.kern.inst.arm 0 # number of arm instructions executed
496 system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
497 system.cpu.committedInsts 112455206 # Number of instructions committed
498 system.cpu.committedOps 135585876 # Number of ops (including micro ops) committed
499 system.cpu.num_int_alu_accesses 119891340 # Number of integer alu accesses
500 system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
501 system.cpu.num_func_calls 9892021 # number of times a function call or return occured
502 system.cpu.num_conditional_control_insts 15230391 # number of instructions that are conditional controls
503 system.cpu.num_int_insts 119891340 # number of integer instructions
504 system.cpu.num_fp_insts 11161 # number of float instructions
505 system.cpu.num_int_register_reads 218059811 # number of times the integer registers were read
506 system.cpu.num_int_register_writes 82644916 # number of times the integer registers were written
507 system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
508 system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
509 system.cpu.num_cc_register_reads 489735153 # number of times the CC registers were read
510 system.cpu.num_cc_register_writes 51893214 # number of times the CC registers were written
511 system.cpu.num_mem_refs 45407055 # number of memory refs
512 system.cpu.num_load_insts 24842618 # Number of load instructions
513 system.cpu.num_store_insts 20564437 # Number of store instructions
514 system.cpu.num_idle_cycles 5379072985.844151 # Number of idle cycles
515 system.cpu.num_busy_cycles 440119357.155849 # Number of busy cycles
516 system.cpu.not_idle_fraction 0.075632 # Percentage of non-idle cycles
517 system.cpu.idle_fraction 0.924368 # Percentage of idle cycles
518 system.cpu.Branches 25916470 # Number of branches fetched
519 system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
520 system.cpu.op_class::IntAlu 93173703 67.17% 67.18% # Class of executed instruction
521 system.cpu.op_class::IntMult 114388 0.08% 67.26% # Class of executed instruction
522 system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
523 system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
524 system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
525 system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
526 system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
527 system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
528 system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
529 system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
530 system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
531 system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
532 system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
533 system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
534 system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
535 system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
536 system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
537 system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
538 system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
539 system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
540 system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
541 system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
542 system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
543 system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
544 system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
545 system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction
546 system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
547 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
548 system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
549 system.cpu.op_class::MemRead 24842618 17.91% 85.17% # Class of executed instruction
550 system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction
551 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
552 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
553 system.cpu.op_class::total 138705936 # Class of executed instruction
554 system.cpu.dcache.tags.replacements 819217 # number of replacements
555 system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use
556 system.cpu.dcache.tags.total_refs 43235406 # Total number of references to valid blocks.
557 system.cpu.dcache.tags.sampled_refs 819729 # Sample count of references to valid blocks.
558 system.cpu.dcache.tags.avg_refs 52.743536 # Average number of references to valid blocks.
559 system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.
560 system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor
561 system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy
562 system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy
563 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
564 system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
565 system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
566 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
567 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
568 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
569 system.cpu.dcache.tags.tag_accesses 177109321 # Number of tag accesses
570 system.cpu.dcache.tags.data_accesses 177109321 # Number of data accesses
571 system.cpu.dcache.ReadReq_hits::cpu.data 23112521 # number of ReadReq hits
572 system.cpu.dcache.ReadReq_hits::total 23112521 # number of ReadReq hits
573 system.cpu.dcache.WriteReq_hits::cpu.data 18823879 # number of WriteReq hits
574 system.cpu.dcache.WriteReq_hits::total 18823879 # number of WriteReq hits
575 system.cpu.dcache.SoftPFReq_hits::cpu.data 392783 # number of SoftPFReq hits
576 system.cpu.dcache.SoftPFReq_hits::total 392783 # number of SoftPFReq hits
577 system.cpu.dcache.LoadLockedReq_hits::cpu.data 443242 # number of LoadLockedReq hits
578 system.cpu.dcache.LoadLockedReq_hits::total 443242 # number of LoadLockedReq hits
579 system.cpu.dcache.StoreCondReq_hits::cpu.data 460216 # number of StoreCondReq hits
580 system.cpu.dcache.StoreCondReq_hits::total 460216 # number of StoreCondReq hits
581 system.cpu.dcache.demand_hits::cpu.data 41936400 # number of demand (read+write) hits
582 system.cpu.dcache.demand_hits::total 41936400 # number of demand (read+write) hits
583 system.cpu.dcache.overall_hits::cpu.data 42329183 # number of overall hits
584 system.cpu.dcache.overall_hits::total 42329183 # number of overall hits
585 system.cpu.dcache.ReadReq_misses::cpu.data 399911 # number of ReadReq misses
586 system.cpu.dcache.ReadReq_misses::total 399911 # number of ReadReq misses
587 system.cpu.dcache.WriteReq_misses::cpu.data 298704 # number of WriteReq misses
588 system.cpu.dcache.WriteReq_misses::total 298704 # number of WriteReq misses
589 system.cpu.dcache.SoftPFReq_misses::cpu.data 118377 # number of SoftPFReq misses
590 system.cpu.dcache.SoftPFReq_misses::total 118377 # number of SoftPFReq misses
591 system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses
592 system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses
593 system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
594 system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
595 system.cpu.dcache.demand_misses::cpu.data 698615 # number of demand (read+write) misses
596 system.cpu.dcache.demand_misses::total 698615 # number of demand (read+write) misses
597 system.cpu.dcache.overall_misses::cpu.data 816992 # number of overall misses
598 system.cpu.dcache.overall_misses::total 816992 # number of overall misses
599 system.cpu.dcache.ReadReq_miss_latency::cpu.data 6486417000 # number of ReadReq miss cycles
600 system.cpu.dcache.ReadReq_miss_latency::total 6486417000 # number of ReadReq miss cycles
601 system.cpu.dcache.WriteReq_miss_latency::cpu.data 19109109000 # number of WriteReq miss cycles
602 system.cpu.dcache.WriteReq_miss_latency::total 19109109000 # number of WriteReq miss cycles
603 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294489000 # number of LoadLockedReq miss cycles
604 system.cpu.dcache.LoadLockedReq_miss_latency::total 294489000 # number of LoadLockedReq miss cycles
605 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
606 system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
607 system.cpu.dcache.demand_miss_latency::cpu.data 25595526000 # number of demand (read+write) miss cycles
608 system.cpu.dcache.demand_miss_latency::total 25595526000 # number of demand (read+write) miss cycles
609 system.cpu.dcache.overall_miss_latency::cpu.data 25595526000 # number of overall miss cycles
610 system.cpu.dcache.overall_miss_latency::total 25595526000 # number of overall miss cycles
611 system.cpu.dcache.ReadReq_accesses::cpu.data 23512432 # number of ReadReq accesses(hits+misses)
612 system.cpu.dcache.ReadReq_accesses::total 23512432 # number of ReadReq accesses(hits+misses)
613 system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses)
614 system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses)
615 system.cpu.dcache.SoftPFReq_accesses::cpu.data 511160 # number of SoftPFReq accesses(hits+misses)
616 system.cpu.dcache.SoftPFReq_accesses::total 511160 # number of SoftPFReq accesses(hits+misses)
617 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465999 # number of LoadLockedReq accesses(hits+misses)
618 system.cpu.dcache.LoadLockedReq_accesses::total 465999 # number of LoadLockedReq accesses(hits+misses)
619 system.cpu.dcache.StoreCondReq_accesses::cpu.data 460218 # number of StoreCondReq accesses(hits+misses)
620 system.cpu.dcache.StoreCondReq_accesses::total 460218 # number of StoreCondReq accesses(hits+misses)
621 system.cpu.dcache.demand_accesses::cpu.data 42635015 # number of demand (read+write) accesses
622 system.cpu.dcache.demand_accesses::total 42635015 # number of demand (read+write) accesses
623 system.cpu.dcache.overall_accesses::cpu.data 43146175 # number of overall (read+write) accesses
624 system.cpu.dcache.overall_accesses::total 43146175 # number of overall (read+write) accesses
625 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses
626 system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses
627 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses
628 system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses
629 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231585 # miss rate for SoftPFReq accesses
630 system.cpu.dcache.SoftPFReq_miss_rate::total 0.231585 # miss rate for SoftPFReq accesses
631 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048835 # miss rate for LoadLockedReq accesses
632 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048835 # miss rate for LoadLockedReq accesses
633 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
634 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
635 system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses
636 system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
637 system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses
638 system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses
639 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372 # average ReadReq miss latency
640 system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372 # average ReadReq miss latency
641 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067 # average WriteReq miss latency
642 system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067 # average WriteReq miss latency
643 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709 # average LoadLockedReq miss latency
644 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709 # average LoadLockedReq miss latency
645 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
646 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
647 system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107 # average overall miss latency
648 system.cpu.dcache.demand_avg_miss_latency::total 36637.527107 # average overall miss latency
649 system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966 # average overall miss latency
650 system.cpu.dcache.overall_avg_miss_latency::total 31328.979966 # average overall miss latency
651 system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
652 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
653 system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
654 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
655 system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
656 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
657 system.cpu.dcache.fast_writes 0 # number of fast writes performed
658 system.cpu.dcache.cache_copies 0 # number of cache copies performed
659 system.cpu.dcache.writebacks::writebacks 683842 # number of writebacks
660 system.cpu.dcache.writebacks::total 683842 # number of writebacks
661 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 930 # number of ReadReq MSHR hits
662 system.cpu.dcache.ReadReq_mshr_hits::total 930 # number of ReadReq MSHR hits
663 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14247 # number of LoadLockedReq MSHR hits
664 system.cpu.dcache.LoadLockedReq_mshr_hits::total 14247 # number of LoadLockedReq MSHR hits
665 system.cpu.dcache.demand_mshr_hits::cpu.data 930 # number of demand (read+write) MSHR hits
666 system.cpu.dcache.demand_mshr_hits::total 930 # number of demand (read+write) MSHR hits
667 system.cpu.dcache.overall_mshr_hits::cpu.data 930 # number of overall MSHR hits
668 system.cpu.dcache.overall_mshr_hits::total 930 # number of overall MSHR hits
669 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398981 # number of ReadReq MSHR misses
670 system.cpu.dcache.ReadReq_mshr_misses::total 398981 # number of ReadReq MSHR misses
671 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298704 # number of WriteReq MSHR misses
672 system.cpu.dcache.WriteReq_mshr_misses::total 298704 # number of WriteReq MSHR misses
673 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116321 # number of SoftPFReq MSHR misses
674 system.cpu.dcache.SoftPFReq_mshr_misses::total 116321 # number of SoftPFReq MSHR misses
675 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses
676 system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses
677 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
678 system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
679 system.cpu.dcache.demand_mshr_misses::cpu.data 697685 # number of demand (read+write) MSHR misses
680 system.cpu.dcache.demand_mshr_misses::total 697685 # number of demand (read+write) MSHR misses
681 system.cpu.dcache.overall_mshr_misses::cpu.data 814006 # number of overall MSHR misses
682 system.cpu.dcache.overall_mshr_misses::total 814006 # number of overall MSHR misses
683 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
684 system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
685 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
686 system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
687 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
688 system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
689 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058107000 # number of ReadReq MSHR miss cycles
690 system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058107000 # number of ReadReq MSHR miss cycles
691 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18810405000 # number of WriteReq MSHR miss cycles
692 system.cpu.dcache.WriteReq_mshr_miss_latency::total 18810405000 # number of WriteReq MSHR miss cycles
693 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1614233500 # number of SoftPFReq MSHR miss cycles
694 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1614233500 # number of SoftPFReq MSHR miss cycles
695 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115353500 # number of LoadLockedReq MSHR miss cycles
696 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115353500 # number of LoadLockedReq MSHR miss cycles
697 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
698 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles
699 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24868512000 # number of demand (read+write) MSHR miss cycles
700 system.cpu.dcache.demand_mshr_miss_latency::total 24868512000 # number of demand (read+write) MSHR miss cycles
701 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26482745500 # number of overall MSHR miss cycles
702 system.cpu.dcache.overall_mshr_miss_latency::total 26482745500 # number of overall MSHR miss cycles
703 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278172000 # number of ReadReq MSHR uncacheable cycles
704 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278172000 # number of ReadReq MSHR uncacheable cycles
705 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089977500 # number of WriteReq MSHR uncacheable cycles
706 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089977500 # number of WriteReq MSHR uncacheable cycles
707 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368149500 # number of overall MSHR uncacheable cycles
708 system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368149500 # number of overall MSHR uncacheable cycles
709 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses
710 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses
711 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
712 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses
713 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227563 # mshr miss rate for SoftPFReq accesses
714 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227563 # mshr miss rate for SoftPFReq accesses
715 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses
716 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses
717 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
718 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
719 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 # mshr miss rate for demand accesses
720 system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses
721 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses
722 system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses
723 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609 # average ReadReq mshr miss latency
724 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609 # average ReadReq mshr miss latency
725 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067 # average WriteReq mshr miss latency
726 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067 # average WriteReq mshr miss latency
727 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908 # average SoftPFReq mshr miss latency
728 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908 # average SoftPFReq mshr miss latency
729 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879 # average LoadLockedReq mshr miss latency
730 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879 # average LoadLockedReq mshr miss latency
731 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
732 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
733 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594 # average overall mshr miss latency
734 system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594 # average overall mshr miss latency
735 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574 # average overall mshr miss latency
736 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574 # average overall mshr miss latency
737 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864 # average ReadReq mshr uncacheable latency
738 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864 # average ReadReq mshr uncacheable latency
739 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458 # average WriteReq mshr uncacheable latency
740 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458 # average WriteReq mshr uncacheable latency
741 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044 # average overall mshr uncacheable latency
742 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044 # average overall mshr uncacheable latency
743 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
744 system.cpu.icache.tags.replacements 1695565 # number of replacements
745 system.cpu.icache.tags.tagsinuse 510.436866 # Cycle average of tags in use
746 system.cpu.icache.tags.total_refs 113856331 # Total number of references to valid blocks.
747 system.cpu.icache.tags.sampled_refs 1696077 # Sample count of references to valid blocks.
748 system.cpu.icache.tags.avg_refs 67.129223 # Average number of references to valid blocks.
749 system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit.
750 system.cpu.icache.tags.occ_blocks::cpu.inst 510.436866 # Average occupied blocks per requestor
751 system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy
752 system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy
753 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
754 system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
755 system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
756 system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
757 system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
758 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
759 system.cpu.icache.tags.tag_accesses 117248497 # Number of tag accesses
760 system.cpu.icache.tags.data_accesses 117248497 # Number of data accesses
761 system.cpu.icache.ReadReq_hits::cpu.inst 113856331 # number of ReadReq hits
762 system.cpu.icache.ReadReq_hits::total 113856331 # number of ReadReq hits
763 system.cpu.icache.demand_hits::cpu.inst 113856331 # number of demand (read+write) hits
764 system.cpu.icache.demand_hits::total 113856331 # number of demand (read+write) hits
765 system.cpu.icache.overall_hits::cpu.inst 113856331 # number of overall hits
766 system.cpu.icache.overall_hits::total 113856331 # number of overall hits
767 system.cpu.icache.ReadReq_misses::cpu.inst 1696083 # number of ReadReq misses
768 system.cpu.icache.ReadReq_misses::total 1696083 # number of ReadReq misses
769 system.cpu.icache.demand_misses::cpu.inst 1696083 # number of demand (read+write) misses
770 system.cpu.icache.demand_misses::total 1696083 # number of demand (read+write) misses
771 system.cpu.icache.overall_misses::cpu.inst 1696083 # number of overall misses
772 system.cpu.icache.overall_misses::total 1696083 # number of overall misses
773 system.cpu.icache.ReadReq_miss_latency::cpu.inst 24267960000 # number of ReadReq miss cycles
774 system.cpu.icache.ReadReq_miss_latency::total 24267960000 # number of ReadReq miss cycles
775 system.cpu.icache.demand_miss_latency::cpu.inst 24267960000 # number of demand (read+write) miss cycles
776 system.cpu.icache.demand_miss_latency::total 24267960000 # number of demand (read+write) miss cycles
777 system.cpu.icache.overall_miss_latency::cpu.inst 24267960000 # number of overall miss cycles
778 system.cpu.icache.overall_miss_latency::total 24267960000 # number of overall miss cycles
779 system.cpu.icache.ReadReq_accesses::cpu.inst 115552414 # number of ReadReq accesses(hits+misses)
780 system.cpu.icache.ReadReq_accesses::total 115552414 # number of ReadReq accesses(hits+misses)
781 system.cpu.icache.demand_accesses::cpu.inst 115552414 # number of demand (read+write) accesses
782 system.cpu.icache.demand_accesses::total 115552414 # number of demand (read+write) accesses
783 system.cpu.icache.overall_accesses::cpu.inst 115552414 # number of overall (read+write) accesses
784 system.cpu.icache.overall_accesses::total 115552414 # number of overall (read+write) accesses
785 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses
786 system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses
787 system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses
788 system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses
789 system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses
790 system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses
791 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453 # average ReadReq miss latency
792 system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453 # average ReadReq miss latency
793 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency
794 system.cpu.icache.demand_avg_miss_latency::total 14308.238453 # average overall miss latency
795 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency
796 system.cpu.icache.overall_avg_miss_latency::total 14308.238453 # average overall miss latency
797 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
798 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
799 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
800 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
801 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
802 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
803 system.cpu.icache.fast_writes 0 # number of fast writes performed
804 system.cpu.icache.cache_copies 0 # number of cache copies performed
805 system.cpu.icache.writebacks::writebacks 1695565 # number of writebacks
806 system.cpu.icache.writebacks::total 1695565 # number of writebacks
807 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696083 # number of ReadReq MSHR misses
808 system.cpu.icache.ReadReq_mshr_misses::total 1696083 # number of ReadReq MSHR misses
809 system.cpu.icache.demand_mshr_misses::cpu.inst 1696083 # number of demand (read+write) MSHR misses
810 system.cpu.icache.demand_mshr_misses::total 1696083 # number of demand (read+write) MSHR misses
811 system.cpu.icache.overall_mshr_misses::cpu.inst 1696083 # number of overall MSHR misses
812 system.cpu.icache.overall_mshr_misses::total 1696083 # number of overall MSHR misses
813 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
814 system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
815 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
816 system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
817 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22571877000 # number of ReadReq MSHR miss cycles
818 system.cpu.icache.ReadReq_mshr_miss_latency::total 22571877000 # number of ReadReq MSHR miss cycles
819 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22571877000 # number of demand (read+write) MSHR miss cycles
820 system.cpu.icache.demand_mshr_miss_latency::total 22571877000 # number of demand (read+write) MSHR miss cycles
821 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22571877000 # number of overall MSHR miss cycles
822 system.cpu.icache.overall_mshr_miss_latency::total 22571877000 # number of overall MSHR miss cycles
823 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
824 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
825 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
826 system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles
827 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses
828 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses
829 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses
830 system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses
831 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses
832 system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses
833 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453 # average ReadReq mshr miss latency
834 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453 # average ReadReq mshr miss latency
835 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency
836 system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency
837 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency
838 system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency
839 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
840 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
841 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
842 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
843 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
844 system.cpu.l2cache.tags.replacements 87562 # number of replacements
845 system.cpu.l2cache.tags.tagsinuse 64865.195753 # Cycle average of tags in use
846 system.cpu.l2cache.tags.total_refs 4544223 # Total number of references to valid blocks.
847 system.cpu.l2cache.tags.sampled_refs 152797 # Sample count of references to valid blocks.
848 system.cpu.l2cache.tags.avg_refs 29.740263 # Average number of references to valid blocks.
849 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
850 system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494 # Average occupied blocks per requestor
851 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor
852 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012652 # Average occupied blocks per requestor
853 system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.731977 # Average occupied blocks per requestor
854 system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.980293 # Average occupied blocks per requestor
855 system.cpu.l2cache.tags.occ_percent::writebacks 0.765940 # Average percentage of cache occupancy
856 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
857 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
858 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy
859 system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy
860 system.cpu.l2cache.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy
861 system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
862 system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id
863 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
864 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
865 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
866 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id
867 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id
868 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id
869 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
870 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id
871 system.cpu.l2cache.tags.tag_accesses 40509810 # Number of tag accesses
872 system.cpu.l2cache.tags.data_accesses 40509810 # Number of data accesses
873 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7810 # number of ReadReq hits
874 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits
875 system.cpu.l2cache.ReadReq_hits::total 11849 # number of ReadReq hits
876 system.cpu.l2cache.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits
877 system.cpu.l2cache.WritebackDirty_hits::total 683842 # number of WritebackDirty hits
878 system.cpu.l2cache.WritebackClean_hits::writebacks 1664795 # number of WritebackClean hits
879 system.cpu.l2cache.WritebackClean_hits::total 1664795 # number of WritebackClean hits
880 system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
881 system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
882 system.cpu.l2cache.ReadExReq_hits::cpu.data 167026 # number of ReadExReq hits
883 system.cpu.l2cache.ReadExReq_hits::total 167026 # number of ReadExReq hits
884 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678074 # number of ReadCleanReq hits
885 system.cpu.l2cache.ReadCleanReq_hits::total 1678074 # number of ReadCleanReq hits
886 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511640 # number of ReadSharedReq hits
887 system.cpu.l2cache.ReadSharedReq_hits::total 511640 # number of ReadSharedReq hits
888 system.cpu.l2cache.demand_hits::cpu.dtb.walker 7810 # number of demand (read+write) hits
889 system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits
890 system.cpu.l2cache.demand_hits::cpu.inst 1678074 # number of demand (read+write) hits
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892 system.cpu.l2cache.demand_hits::total 2368589 # number of demand (read+write) hits
893 system.cpu.l2cache.overall_hits::cpu.dtb.walker 7810 # number of overall hits
894 system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits
895 system.cpu.l2cache.overall_hits::cpu.inst 1678074 # number of overall hits
896 system.cpu.l2cache.overall_hits::cpu.data 678666 # number of overall hits
897 system.cpu.l2cache.overall_hits::total 2368589 # number of overall hits
898 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
899 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
900 system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
901 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 # number of UpgradeReq misses
902 system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses
903 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
904 system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
905 system.cpu.l2cache.ReadExReq_misses::cpu.data 128915 # number of ReadExReq misses
906 system.cpu.l2cache.ReadExReq_misses::total 128915 # number of ReadExReq misses
907 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses
908 system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses
909 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses
910 system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses
911 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
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913 system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses
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915 system.cpu.l2cache.demand_misses::total 159072 # number of demand (read+write) misses
916 system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
917 system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
918 system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses
919 system.cpu.l2cache.overall_misses::cpu.data 141087 # number of overall misses
920 system.cpu.l2cache.overall_misses::total 159072 # number of overall misses
921 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles
922 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles
923 system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles
924 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles
925 system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles
926 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
927 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
928 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16383348000 # number of ReadExReq miss cycles
929 system.cpu.l2cache.ReadExReq_miss_latency::total 16383348000 # number of ReadExReq miss cycles
930 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2349142000 # number of ReadCleanReq miss cycles
931 system.cpu.l2cache.ReadCleanReq_miss_latency::total 2349142000 # number of ReadCleanReq miss cycles
932 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1612524000 # number of ReadSharedReq miss cycles
933 system.cpu.l2cache.ReadSharedReq_miss_latency::total 1612524000 # number of ReadSharedReq miss cycles
934 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles
935 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles
936 system.cpu.l2cache.demand_miss_latency::cpu.inst 2349142000 # number of demand (read+write) miss cycles
937 system.cpu.l2cache.demand_miss_latency::cpu.data 17995872000 # number of demand (read+write) miss cycles
938 system.cpu.l2cache.demand_miss_latency::total 20346237500 # number of demand (read+write) miss cycles
939 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles
940 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles
941 system.cpu.l2cache.overall_miss_latency::cpu.inst 2349142000 # number of overall miss cycles
942 system.cpu.l2cache.overall_miss_latency::cpu.data 17995872000 # number of overall miss cycles
943 system.cpu.l2cache.overall_miss_latency::total 20346237500 # number of overall miss cycles
944 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7817 # number of ReadReq accesses(hits+misses)
945 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses)
946 system.cpu.l2cache.ReadReq_accesses::total 11858 # number of ReadReq accesses(hits+misses)
947 system.cpu.l2cache.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses)
948 system.cpu.l2cache.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses)
949 system.cpu.l2cache.WritebackClean_accesses::writebacks 1664795 # number of WritebackClean accesses(hits+misses)
950 system.cpu.l2cache.WritebackClean_accesses::total 1664795 # number of WritebackClean accesses(hits+misses)
951 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses)
952 system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses)
953 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
954 system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
955 system.cpu.l2cache.ReadExReq_accesses::cpu.data 295941 # number of ReadExReq accesses(hits+misses)
956 system.cpu.l2cache.ReadExReq_accesses::total 295941 # number of ReadExReq accesses(hits+misses)
957 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696050 # number of ReadCleanReq accesses(hits+misses)
958 system.cpu.l2cache.ReadCleanReq_accesses::total 1696050 # number of ReadCleanReq accesses(hits+misses)
959 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523812 # number of ReadSharedReq accesses(hits+misses)
960 system.cpu.l2cache.ReadSharedReq_accesses::total 523812 # number of ReadSharedReq accesses(hits+misses)
961 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7817 # number of demand (read+write) accesses
962 system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses
963 system.cpu.l2cache.demand_accesses::cpu.inst 1696050 # number of demand (read+write) accesses
964 system.cpu.l2cache.demand_accesses::cpu.data 819753 # number of demand (read+write) accesses
965 system.cpu.l2cache.demand_accesses::total 2527661 # number of demand (read+write) accesses
966 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7817 # number of overall (read+write) accesses
967 system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses
968 system.cpu.l2cache.overall_accesses::cpu.inst 1696050 # number of overall (read+write) accesses
969 system.cpu.l2cache.overall_accesses::cpu.data 819753 # number of overall (read+write) accesses
970 system.cpu.l2cache.overall_accesses::total 2527661 # number of overall (read+write) accesses
971 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000895 # miss rate for ReadReq accesses
972 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses
973 system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses
974 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991676 # miss rate for UpgradeReq accesses
975 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses
976 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
977 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
978 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435610 # miss rate for ReadExReq accesses
979 system.cpu.l2cache.ReadExReq_miss_rate::total 0.435610 # miss rate for ReadExReq accesses
980 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010599 # miss rate for ReadCleanReq accesses
981 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses
982 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023237 # miss rate for ReadSharedReq accesses
983 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023237 # miss rate for ReadSharedReq accesses
984 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000895 # miss rate for demand accesses
985 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses
986 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010599 # miss rate for demand accesses
987 system.cpu.l2cache.demand_miss_rate::cpu.data 0.172109 # miss rate for demand accesses
988 system.cpu.l2cache.demand_miss_rate::total 0.062932 # miss rate for demand accesses
989 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000895 # miss rate for overall accesses
990 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses
991 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010599 # miss rate for overall accesses
992 system.cpu.l2cache.overall_miss_rate::cpu.data 0.172109 # miss rate for overall accesses
993 system.cpu.l2cache.overall_miss_rate::total 0.062932 # miss rate for overall accesses
994 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency
995 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency
996 system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency
997 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency
998 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency
999 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
1000 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
1001 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799 # average ReadExReq miss latency
1002 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799 # average ReadExReq miss latency
1003 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130682.131731 # average ReadCleanReq miss latency
1004 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731 # average ReadCleanReq miss latency
1005 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132478.146566 # average ReadSharedReq miss latency
1006 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566 # average ReadSharedReq miss latency
1007 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
1008 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
1009 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency
1010 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency
1011 system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237 # average overall miss latency
1012 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
1013 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
1014 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency
1015 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency
1016 system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237 # average overall miss latency
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1018 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1019 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1020 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1021 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1022 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1023 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1024 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1025 system.cpu.l2cache.writebacks::writebacks 81183 # number of writebacks
1026 system.cpu.l2cache.writebacks::total 81183 # number of writebacks
1027 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
1028 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1029 system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
1030 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 # number of UpgradeReq MSHR misses
1031 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses
1032 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1033 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1034 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128915 # number of ReadExReq MSHR misses
1035 system.cpu.l2cache.ReadExReq_mshr_misses::total 128915 # number of ReadExReq MSHR misses
1036 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17976 # number of ReadCleanReq MSHR misses
1037 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17976 # number of ReadCleanReq MSHR misses
1038 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses
1039 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses
1040 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
1041 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1042 system.cpu.l2cache.demand_mshr_misses::cpu.inst 17976 # number of demand (read+write) MSHR misses
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1053 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
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1055 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
1056 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
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1058 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 887500 # number of ReadReq MSHR miss cycles
1059 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles
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1061 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003500 # number of UpgradeReq MSHR miss cycles
1062 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003500 # number of UpgradeReq MSHR miss cycles
1063 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles
1064 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
1065 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15094198000 # number of ReadExReq MSHR miss cycles
1066 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15094198000 # number of ReadExReq MSHR miss cycles
1067 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2169382000 # number of ReadCleanReq MSHR miss cycles
1068 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2169382000 # number of ReadCleanReq MSHR miss cycles
1069 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1490804000 # number of ReadSharedReq MSHR miss cycles
1070 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1490804000 # number of ReadSharedReq MSHR miss cycles
1071 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles
1072 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles
1073 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2169382000 # number of demand (read+write) MSHR miss cycles
1074 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16585002000 # number of demand (read+write) MSHR miss cycles
1075 system.cpu.l2cache.demand_mshr_miss_latency::total 18755517500 # number of demand (read+write) MSHR miss cycles
1076 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles
1077 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles
1078 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169382000 # number of overall MSHR miss cycles
1079 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16585002000 # number of overall MSHR miss cycles
1080 system.cpu.l2cache.overall_mshr_miss_latency::total 18755517500 # number of overall MSHR miss cycles
1081 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles
1082 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888826500 # number of ReadReq MSHR uncacheable cycles
1083 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918592500 # number of ReadReq MSHR uncacheable cycles
1084 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574000 # number of WriteReq MSHR uncacheable cycles
1085 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574000 # number of WriteReq MSHR uncacheable cycles
1086 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles
1087 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661400500 # number of overall MSHR uncacheable cycles
1088 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691166500 # number of overall MSHR uncacheable cycles
1089 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses
1090 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
1091 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses
1092 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses
1093 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses
1094 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1095 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1096 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435610 # mshr miss rate for ReadExReq accesses
1097 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435610 # mshr miss rate for ReadExReq accesses
1098 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses
1099 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses
1100 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023237 # mshr miss rate for ReadSharedReq accesses
1101 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023237 # mshr miss rate for ReadSharedReq accesses
1102 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses
1103 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
1104 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses
1105 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for demand accesses
1106 system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses
1107 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses
1108 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
1109 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses
1110 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for overall accesses
1111 system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses
1112 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency
1113 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency
1114 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency
1115 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080 # average UpgradeReq mshr miss latency
1116 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080 # average UpgradeReq mshr miss latency
1117 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
1118 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
1119 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799 # average ReadExReq mshr miss latency
1120 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799 # average ReadExReq mshr miss latency
1121 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731 # average ReadCleanReq mshr miss latency
1122 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731 # average ReadCleanReq mshr miss latency
1123 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566 # average ReadSharedReq mshr miss latency
1124 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566 # average ReadSharedReq mshr miss latency
1125 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
1126 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
1127 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency
1128 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency
1129 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency
1130 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
1131 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
1132 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency
1133 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency
1134 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency
1135 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency
1136 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994 # average ReadReq mshr uncacheable latency
1137 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661 # average ReadReq mshr uncacheable latency
1138 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435 # average WriteReq mshr uncacheable latency
1139 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435 # average WriteReq mshr uncacheable latency
1140 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency
1141 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460 # average overall mshr uncacheable latency
1142 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271 # average overall mshr uncacheable latency
1143 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1144 system.cpu.toL2Bus.snoop_filter.tot_requests 5052537 # Total number of requests made to the snoop filter.
1145 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536723 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1146 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1147 system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter.
1148 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1149 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1150 system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution
1151 system.cpu.toL2Bus.trans_dist::ReadResp 2287321 # Transaction distribution
1152 system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
1153 system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
1154 system.cpu.toL2Bus.trans_dist::WritebackDirty 801217 # Transaction distribution
1155 system.cpu.toL2Bus.trans_dist::WritebackClean 1664795 # Transaction distribution
1156 system.cpu.toL2Bus.trans_dist::CleanEvict 134627 # Transaction distribution
1157 system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution
1158 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1159 system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution
1160 system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution
1161 system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution
1162 system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696083 # Transaction distribution
1163 system.cpu.toL2Bus.trans_dist::ReadSharedReq 524040 # Transaction distribution
1164 system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1165 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074972 # Packet count per connected master and slave (bytes)
1166 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574565 # Packet count per connected master and slave (bytes)
1167 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes)
1168 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25654 # Packet count per connected master and slave (bytes)
1169 system.cpu.toL2Bus.pkt_count::total 7688448 # Packet count per connected master and slave (bytes)
1170 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215130168 # Cumulative packet size per connected master and slave (bytes)
1171 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96426845 # Cumulative packet size per connected master and slave (bytes)
1172 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes)
1173 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31268 # Cumulative packet size per connected master and slave (bytes)
1174 system.cpu.toL2Bus.pkt_size::total 311604445 # Cumulative packet size per connected master and slave (bytes)
1175 system.cpu.toL2Bus.snoops 175875 # Total snoops (count)
1176 system.cpu.toL2Bus.snoop_fanout::samples 2773837 # Request fanout histogram
1177 system.cpu.toL2Bus.snoop_fanout::mean 0.020867 # Request fanout histogram
1178 system.cpu.toL2Bus.snoop_fanout::stdev 0.142939 # Request fanout histogram
1179 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1180 system.cpu.toL2Bus.snoop_fanout::0 2715955 97.91% 97.91% # Request fanout histogram
1181 system.cpu.toL2Bus.snoop_fanout::1 57882 2.09% 100.00% # Request fanout histogram
1182 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1183 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1184 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1185 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1186 system.cpu.toL2Bus.snoop_fanout::total 2773837 # Request fanout histogram
1187 system.cpu.toL2Bus.reqLayer0.occupancy 4957294000 # Layer occupancy (ticks)
1188 system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1189 system.cpu.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks)
1190 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1191 system.cpu.toL2Bus.respLayer0.occupancy 2553146500 # Layer occupancy (ticks)
1192 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1193 system.cpu.toL2Bus.respLayer1.occupancy 1275944500 # Layer occupancy (ticks)
1194 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1195 system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
1196 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1197 system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks)
1198 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1199 system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
1200 system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
1201 system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1202 system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1203 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1204 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1205 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1206 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1207 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1208 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1209 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1210 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1211 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1212 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1213 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1214 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
1215 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1216 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1217 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1218 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1219 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1220 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1221 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1222 system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1223 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes)
1224 system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes)
1225 system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
1226 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1227 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1228 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
1229 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1230 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1231 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1232 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1233 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1234 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1235 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1236 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1237 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
1238 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1239 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1240 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1241 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1242 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1243 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1244 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1245 system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1246 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
1247 system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
1248 system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)
1249 system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)
1250 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1251 system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
1252 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1253 system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
1254 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1255 system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
1256 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1257 system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
1258 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1259 system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
1260 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1261 system.iobus.reqLayer8.occupancy 644500 # Layer occupancy (ticks)
1262 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1263 system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
1264 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1265 system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
1266 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1267 system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
1268 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1269 system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
1270 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1271 system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks)
1272 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1273 system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
1274 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1275 system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
1276 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1277 system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1278 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1279 system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
1280 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1281 system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
1282 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1283 system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks)
1284 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1285 system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
1286 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1287 system.iobus.reqLayer25.occupancy 186221548 # Layer occupancy (ticks)
1288 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1289 system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1290 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1291 system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
1292 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1293 system.iocache.tags.replacements 36418 # number of replacements
1294 system.iocache.tags.tagsinuse 1.084130 # Cycle average of tags in use
1295 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1296 system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
1297 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1298 system.iocache.tags.warmup_cycle 313812613000 # Cycle when the warmup percentage was hit.
1299 system.iocache.tags.occ_blocks::realview.ide 1.084130 # Average occupied blocks per requestor
1300 system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy
1301 system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy
1302 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1303 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1304 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1305 system.iocache.tags.tag_accesses 328068 # Number of tag accesses
1306 system.iocache.tags.data_accesses 328068 # Number of data accesses
1307 system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
1308 system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
1309 system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1310 system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1311 system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
1312 system.iocache.demand_misses::total 228 # number of demand (read+write) misses
1313 system.iocache.overall_misses::realview.ide 228 # number of overall misses
1314 system.iocache.overall_misses::total 228 # number of overall misses
1315 system.iocache.ReadReq_miss_latency::realview.ide 28228376 # number of ReadReq miss cycles
1316 system.iocache.ReadReq_miss_latency::total 28228376 # number of ReadReq miss cycles
1317 system.iocache.WriteLineReq_miss_latency::realview.ide 4717653172 # number of WriteLineReq miss cycles
1318 system.iocache.WriteLineReq_miss_latency::total 4717653172 # number of WriteLineReq miss cycles
1319 system.iocache.demand_miss_latency::realview.ide 28228376 # number of demand (read+write) miss cycles
1320 system.iocache.demand_miss_latency::total 28228376 # number of demand (read+write) miss cycles
1321 system.iocache.overall_miss_latency::realview.ide 28228376 # number of overall miss cycles
1322 system.iocache.overall_miss_latency::total 28228376 # number of overall miss cycles
1323 system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
1324 system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
1325 system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1326 system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1327 system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
1328 system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
1329 system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
1330 system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
1331 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1332 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1333 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1334 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1335 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1336 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1337 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1338 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1339 system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667 # average ReadReq miss latency
1340 system.iocache.ReadReq_avg_miss_latency::total 123808.666667 # average ReadReq miss latency
1341 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807 # average WriteLineReq miss latency
1342 system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807 # average WriteLineReq miss latency
1343 system.iocache.demand_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency
1344 system.iocache.demand_avg_miss_latency::total 123808.666667 # average overall miss latency
1345 system.iocache.overall_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency
1346 system.iocache.overall_avg_miss_latency::total 123808.666667 # average overall miss latency
1347 system.iocache.blocked_cycles::no_mshrs 910 # number of cycles access was blocked
1348 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1349 system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked
1350 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1351 system.iocache.avg_blocked_cycles::no_mshrs 11.234568 # average number of cycles each access was blocked
1352 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1353 system.iocache.fast_writes 0 # number of fast writes performed
1354 system.iocache.cache_copies 0 # number of cache copies performed
1355 system.iocache.writebacks::writebacks 36190 # number of writebacks
1356 system.iocache.writebacks::total 36190 # number of writebacks
1357 system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
1358 system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
1359 system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1360 system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1361 system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
1362 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
1363 system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
1364 system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
1365 system.iocache.ReadReq_mshr_miss_latency::realview.ide 16828376 # number of ReadReq MSHR miss cycles
1366 system.iocache.ReadReq_mshr_miss_latency::total 16828376 # number of ReadReq MSHR miss cycles
1367 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906453172 # number of WriteLineReq MSHR miss cycles
1368 system.iocache.WriteLineReq_mshr_miss_latency::total 2906453172 # number of WriteLineReq MSHR miss cycles
1369 system.iocache.demand_mshr_miss_latency::realview.ide 16828376 # number of demand (read+write) MSHR miss cycles
1370 system.iocache.demand_mshr_miss_latency::total 16828376 # number of demand (read+write) MSHR miss cycles
1371 system.iocache.overall_mshr_miss_latency::realview.ide 16828376 # number of overall MSHR miss cycles
1372 system.iocache.overall_mshr_miss_latency::total 16828376 # number of overall MSHR miss cycles
1373 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1374 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1375 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1376 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1377 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1378 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1379 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1380 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1381 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667 # average ReadReq mshr miss latency
1382 system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667 # average ReadReq mshr miss latency
1383 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807 # average WriteLineReq mshr miss latency
1384 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807 # average WriteLineReq mshr miss latency
1385 system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency
1386 system.iocache.demand_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency
1387 system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency
1388 system.iocache.overall_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency
1389 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1390 system.membus.trans_dist::ReadReq 40160 # Transaction distribution
1391 system.membus.trans_dist::ReadResp 70545 # Transaction distribution
1392 system.membus.trans_dist::WriteReq 27589 # Transaction distribution
1393 system.membus.trans_dist::WriteResp 27589 # Transaction distribution
1394 system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution
1395 system.membus.trans_dist::CleanEvict 6392 # Transaction distribution
1396 system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution
1397 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1398 system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution
1399 system.membus.trans_dist::ReadExReq 127158 # Transaction distribution
1400 system.membus.trans_dist::ReadExResp 127158 # Transaction distribution
1401 system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution
1402 system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
1403 system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
1404 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1405 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
1406 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
1407 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438817 # Packet count per connected master and slave (bytes)
1408 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546409 # Packet count per connected master and slave (bytes)
1409 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
1410 system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
1411 system.membus.pkt_count::total 655303 # Packet count per connected master and slave (bytes)
1412 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1413 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
1414 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
1415 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes)
1416 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes)
1417 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1418 system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
1419 system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes)
1420 system.membus.snoops 492 # Total snoops (count)
1421 system.membus.snoop_fanout::samples 389997 # Request fanout histogram
1422 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1423 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1424 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1425 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1426 system.membus.snoop_fanout::1 389997 100.00% 100.00% # Request fanout histogram
1427 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1428 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1429 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1430 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1431 system.membus.snoop_fanout::total 389997 # Request fanout histogram
1432 system.membus.reqLayer0.occupancy 90470000 # Layer occupancy (ticks)
1433 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1434 system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1435 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1436 system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks)
1437 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1438 system.membus.reqLayer5.occupancy 823068661 # Layer occupancy (ticks)
1439 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1440 system.membus.respLayer2.occupancy 952238748 # Layer occupancy (ticks)
1441 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1442 system.membus.respLayer3.occupancy 64113741 # Layer occupancy (ticks)
1443 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1444 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1445 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1446 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1447 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1448 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1449 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1450 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1451 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1452 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1453 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1454 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1455 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1456 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1457 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1458 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1459 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1460 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1461 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1462 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1463 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1464 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1465 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1466 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1467 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1468 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1469 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1470 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1471 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1472 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1473 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1474 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1475 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1476 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1477 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1478 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1479 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1480 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1481 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1482 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1483 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1484 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1486 ---------- End Simulation Statistics ----------
projects / gem5.git / blob