8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/dist/m5/system/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
24 gic_cpu_addr=738205696
25 have_large_asid_64=false
28 have_virtualization=false
29 highest_el_is_64=false
31 kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
32 kernel_addr_check=true
33 load_addr_mask=268435455
34 load_offset=2147483648
35 machine_type=VExpress_EMM
37 mem_ranges=2147483648:2415919103
38 memories=system.physmem system.realview.nvmem system.realview.vram
39 mmap_using_noreserve=false
46 readfile=/z/atgutier/gem5/gem5/tests/halt.sh
49 work_begin_ckpt_count=0
50 work_begin_cpu_id_exit=-1
51 work_begin_exit_count=0
52 work_cpus_ckpt_count=0
56 system_port=system.membus.slave[1]
60 clk_domain=system.clk_domain
63 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
66 master=system.iobus.slave[0]
67 slave=system.membus.master[0]
75 image=system.cf0.image
80 child=system.cf0.image.child
86 [system.cf0.image.child]
89 image_file=/dist/m5/system/disks/linux-aarch32-ael.img
98 voltage_domain=system.voltage_domain
102 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
105 clk_domain=system.cpu_clk_domain
107 do_checkpoint_insts=true
109 do_statistics_insts=true
110 dstage2_mmu=system.cpu0.dstage2_mmu
114 function_trace_start=0
115 interrupts=system.cpu0.interrupts
117 istage2_mmu=system.cpu0.istage2_mmu
119 max_insts_all_threads=0
120 max_insts_any_thread=0
121 max_loads_all_threads=0
122 max_loads_any_thread=0
126 simpoint_start_insts=
130 tracer=system.cpu0.tracer
132 dcache_port=system.cpu0.dcache.cpu_side
133 icache_port=system.cpu0.icache.cpu_side
138 addr_ranges=0:18446744073709551615
140 clk_domain=system.cpu_clk_domain
141 clusivity=mostly_incl
142 demand_mshr_reserve=1
149 prefetch_on_access=false
152 sequential_access=false
155 tags=system.cpu0.dcache.tags
159 cpu_side=system.cpu0.dcache_port
160 mem_side=system.cpu0.toL2Bus.slave[1]
162 [system.cpu0.dcache.tags]
166 clk_domain=system.cpu_clk_domain
169 sequential_access=false
172 [system.cpu0.dstage2_mmu]
176 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
180 [system.cpu0.dstage2_mmu.stage2_tlb]
186 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
188 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
190 clk_domain=system.cpu_clk_domain
193 num_squash_per_cycle=2
202 walker=system.cpu0.dtb.walker
204 [system.cpu0.dtb.walker]
206 clk_domain=system.cpu_clk_domain
209 num_squash_per_cycle=2
211 port=system.cpu0.toL2Bus.slave[3]
216 addr_ranges=0:18446744073709551615
218 clk_domain=system.cpu_clk_domain
219 clusivity=mostly_incl
220 demand_mshr_reserve=1
227 prefetch_on_access=false
230 sequential_access=false
233 tags=system.cpu0.icache.tags
237 cpu_side=system.cpu0.icache_port
238 mem_side=system.cpu0.toL2Bus.slave[0]
240 [system.cpu0.icache.tags]
244 clk_domain=system.cpu_clk_domain
247 sequential_access=false
250 [system.cpu0.interrupts]
256 decoderFlavour=Generic
261 id_aa64dfr0_el1=1052678
265 id_aa64mmfr0_el1=15728642
285 [system.cpu0.istage2_mmu]
289 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
293 [system.cpu0.istage2_mmu.stage2_tlb]
299 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
301 [system.cpu0.istage2_mmu.stage2_tlb.walker]
303 clk_domain=system.cpu_clk_domain
306 num_squash_per_cycle=2
315 walker=system.cpu0.itb.walker
317 [system.cpu0.itb.walker]
319 clk_domain=system.cpu_clk_domain
322 num_squash_per_cycle=2
324 port=system.cpu0.toL2Bus.slave[2]
326 [system.cpu0.l2cache]
328 children=prefetcher tags
329 addr_ranges=0:18446744073709551615
331 clk_domain=system.cpu_clk_domain
332 clusivity=mostly_excl
333 demand_mshr_reserve=1
340 prefetch_on_access=true
341 prefetcher=system.cpu0.l2cache.prefetcher
343 sequential_access=false
346 tags=system.cpu0.l2cache.tags
349 writeback_clean=false
350 cpu_side=system.cpu0.toL2Bus.master[0]
351 mem_side=system.toL2Bus.slave[0]
353 [system.cpu0.l2cache.prefetcher]
354 type=StridePrefetcher
356 clk_domain=system.cpu_clk_domain
378 [system.cpu0.l2cache.tags]
382 clk_domain=system.cpu_clk_domain
385 sequential_access=false
388 [system.cpu0.toL2Bus]
390 children=snoop_filter
391 clk_domain=system.cpu_clk_domain
396 snoop_filter=system.cpu0.toL2Bus.snoop_filter
397 snoop_response_latency=1
399 use_default_range=false
401 master=system.cpu0.l2cache.cpu_side
402 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
404 [system.cpu0.toL2Bus.snoop_filter]
417 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
420 clk_domain=system.cpu_clk_domain
422 do_checkpoint_insts=true
424 do_statistics_insts=true
425 dstage2_mmu=system.cpu1.dstage2_mmu
429 function_trace_start=0
430 interrupts=system.cpu1.interrupts
432 istage2_mmu=system.cpu1.istage2_mmu
434 max_insts_all_threads=0
435 max_insts_any_thread=0
436 max_loads_all_threads=0
437 max_loads_any_thread=0
441 simpoint_start_insts=
445 tracer=system.cpu1.tracer
447 dcache_port=system.cpu1.dcache.cpu_side
448 icache_port=system.cpu1.icache.cpu_side
453 addr_ranges=0:18446744073709551615
455 clk_domain=system.cpu_clk_domain
456 clusivity=mostly_incl
457 demand_mshr_reserve=1
464 prefetch_on_access=false
467 sequential_access=false
470 tags=system.cpu1.dcache.tags
474 cpu_side=system.cpu1.dcache_port
475 mem_side=system.cpu1.toL2Bus.slave[1]
477 [system.cpu1.dcache.tags]
481 clk_domain=system.cpu_clk_domain
484 sequential_access=false
487 [system.cpu1.dstage2_mmu]
491 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
495 [system.cpu1.dstage2_mmu.stage2_tlb]
501 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
503 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
505 clk_domain=system.cpu_clk_domain
508 num_squash_per_cycle=2
517 walker=system.cpu1.dtb.walker
519 [system.cpu1.dtb.walker]
521 clk_domain=system.cpu_clk_domain
524 num_squash_per_cycle=2
526 port=system.cpu1.toL2Bus.slave[3]
531 addr_ranges=0:18446744073709551615
533 clk_domain=system.cpu_clk_domain
534 clusivity=mostly_incl
535 demand_mshr_reserve=1
542 prefetch_on_access=false
545 sequential_access=false
548 tags=system.cpu1.icache.tags
552 cpu_side=system.cpu1.icache_port
553 mem_side=system.cpu1.toL2Bus.slave[0]
555 [system.cpu1.icache.tags]
559 clk_domain=system.cpu_clk_domain
562 sequential_access=false
565 [system.cpu1.interrupts]
571 decoderFlavour=Generic
576 id_aa64dfr0_el1=1052678
580 id_aa64mmfr0_el1=15728642
600 [system.cpu1.istage2_mmu]
604 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
608 [system.cpu1.istage2_mmu.stage2_tlb]
614 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
616 [system.cpu1.istage2_mmu.stage2_tlb.walker]
618 clk_domain=system.cpu_clk_domain
621 num_squash_per_cycle=2
630 walker=system.cpu1.itb.walker
632 [system.cpu1.itb.walker]
634 clk_domain=system.cpu_clk_domain
637 num_squash_per_cycle=2
639 port=system.cpu1.toL2Bus.slave[2]
641 [system.cpu1.l2cache]
643 children=prefetcher tags
644 addr_ranges=0:18446744073709551615
646 clk_domain=system.cpu_clk_domain
647 clusivity=mostly_excl
648 demand_mshr_reserve=1
655 prefetch_on_access=true
656 prefetcher=system.cpu1.l2cache.prefetcher
658 sequential_access=false
661 tags=system.cpu1.l2cache.tags
664 writeback_clean=false
665 cpu_side=system.cpu1.toL2Bus.master[0]
666 mem_side=system.toL2Bus.slave[1]
668 [system.cpu1.l2cache.prefetcher]
669 type=StridePrefetcher
671 clk_domain=system.cpu_clk_domain
693 [system.cpu1.l2cache.tags]
697 clk_domain=system.cpu_clk_domain
700 sequential_access=false
703 [system.cpu1.toL2Bus]
705 children=snoop_filter
706 clk_domain=system.cpu_clk_domain
711 snoop_filter=system.cpu1.toL2Bus.snoop_filter
712 snoop_response_latency=1
714 use_default_range=false
716 master=system.cpu1.l2cache.cpu_side
717 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
719 [system.cpu1.toL2Bus.snoop_filter]
730 [system.cpu_clk_domain]
736 voltage_domain=system.voltage_domain
738 [system.dvfs_handler]
743 sys_clk_domain=system.clk_domain
744 transition_latency=100000000
753 clk_domain=system.clk_domain
758 use_default_range=false
760 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
761 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
766 addr_ranges=2147483648:2415919103
768 clk_domain=system.clk_domain
769 clusivity=mostly_incl
770 demand_mshr_reserve=1
777 prefetch_on_access=false
780 sequential_access=false
783 tags=system.iocache.tags
786 writeback_clean=false
787 cpu_side=system.iobus.master[25]
788 mem_side=system.membus.slave[3]
790 [system.iocache.tags]
794 clk_domain=system.clk_domain
797 sequential_access=false
803 addr_ranges=0:18446744073709551615
805 clk_domain=system.cpu_clk_domain
806 clusivity=mostly_incl
807 demand_mshr_reserve=1
814 prefetch_on_access=false
817 sequential_access=false
823 writeback_clean=false
824 cpu_side=system.toL2Bus.master[0]
825 mem_side=system.membus.slave[2]
831 clk_domain=system.cpu_clk_domain
834 sequential_access=false
839 children=badaddr_responder
840 clk_domain=system.clk_domain
846 snoop_response_latency=4
848 use_default_range=false
850 default=system.membus.badaddr_responder.pio
851 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
852 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
854 [system.membus.badaddr_responder]
856 clk_domain=system.clk_domain
864 ret_data32=4294967295
865 ret_data64=18446744073709551615
870 pio=system.membus.default
899 addr_mapping=RoRaBaCoCh
900 bank_groups_per_rank=0
904 clk_domain=system.clk_domain
905 conf_table_reported=true
907 device_rowbuffer_size=1024
908 device_size=536870912
913 max_accesses_per_row=16
914 mem_sched_policy=frfcfs
915 min_writes_per_switch=16
917 page_policy=open_adaptive
918 range=2147483648:2415919103
921 static_backend_latency=10000
922 static_frontend_latency=10000
945 write_high_thresh_perc=85
946 write_low_thresh_perc=50
947 port=system.membus.master[5]
951 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
953 intrctrl=system.intrctrl
956 [system.realview.aaci_fake]
959 clk_domain=system.clk_domain
965 pio=system.iobus.master[18]
967 [system.realview.cf_ctrl]
1006 MSICAPMsgUpperAddr=0
1007 MSICAPNextCapability=0
1011 MSIXCAPNextCapability=0
1021 PMCAPNextCapability=0
1026 PXCAPDevCapabilities=0
1033 PXCAPNextCapability=0
1041 clk_domain=system.clk_domain
1042 config_latency=20000
1046 host=system.realview.pci_host
1053 dma=system.iobus.slave[2]
1054 pio=system.iobus.master[9]
1056 [system.realview.clcd]
1059 clk_domain=system.clk_domain
1062 gic=system.realview.gic
1068 vnc=system.vncserver
1069 dma=system.iobus.slave[1]
1070 pio=system.iobus.master[5]
1072 [system.realview.dcc]
1074 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1077 [system.realview.dcc.osc_cpu]
1083 parent=system.realview.realview_io
1086 voltage_domain=system.voltage_domain
1088 [system.realview.dcc.osc_ddr]
1094 parent=system.realview.realview_io
1097 voltage_domain=system.voltage_domain
1099 [system.realview.dcc.osc_hsbm]
1105 parent=system.realview.realview_io
1108 voltage_domain=system.voltage_domain
1110 [system.realview.dcc.osc_pxl]
1116 parent=system.realview.realview_io
1119 voltage_domain=system.voltage_domain
1121 [system.realview.dcc.osc_smb]
1127 parent=system.realview.realview_io
1130 voltage_domain=system.voltage_domain
1132 [system.realview.dcc.osc_sys]
1138 parent=system.realview.realview_io
1141 voltage_domain=system.voltage_domain
1143 [system.realview.energy_ctrl]
1145 clk_domain=system.clk_domain
1146 dvfs_handler=system.dvfs_handler
1151 pio=system.iobus.master[22]
1153 [system.realview.ethernet]
1192 MSICAPMsgUpperAddr=0
1193 MSICAPNextCapability=0
1197 MSIXCAPNextCapability=0
1207 PMCAPNextCapability=0
1212 PXCAPDevCapabilities=0
1219 PXCAPNextCapability=0
1225 SubsystemVendorID=32902
1227 clk_domain=system.clk_domain
1228 config_latency=20000
1230 fetch_comp_delay=10000
1232 hardware_address=00:90:00:00:00:01
1233 host=system.realview.pci_host
1240 rx_desc_cache_size=64
1244 tx_desc_cache_size=64
1249 dma=system.iobus.slave[4]
1250 pio=system.iobus.master[24]
1252 [system.realview.generic_timer]
1255 gic=system.realview.gic
1260 [system.realview.gic]
1262 clk_domain=system.clk_domain
1266 dist_pio_delay=10000
1270 platform=system.realview
1272 pio=system.membus.master[2]
1274 [system.realview.hdlcd]
1277 clk_domain=system.clk_domain
1280 gic=system.realview.gic
1284 pixel_buffer_size=2048
1286 pxl_clk=system.realview.dcc.osc_pxl
1288 vnc=system.vncserver
1289 workaround_dma_line_count=true
1290 workaround_swap_rb=true
1291 dma=system.membus.slave[0]
1292 pio=system.iobus.master[6]
1294 [system.realview.ide]
1333 MSICAPMsgUpperAddr=0
1334 MSICAPNextCapability=0
1338 MSIXCAPNextCapability=0
1348 PMCAPNextCapability=0
1353 PXCAPDevCapabilities=0
1360 PXCAPNextCapability=0
1368 clk_domain=system.clk_domain
1369 config_latency=20000
1373 host=system.realview.pci_host
1380 dma=system.iobus.slave[3]
1381 pio=system.iobus.master[23]
1383 [system.realview.kmi0]
1386 clk_domain=system.clk_domain
1388 gic=system.realview.gic
1395 vnc=system.vncserver
1396 pio=system.iobus.master[7]
1398 [system.realview.kmi1]
1401 clk_domain=system.clk_domain
1403 gic=system.realview.gic
1410 vnc=system.vncserver
1411 pio=system.iobus.master[8]
1413 [system.realview.l2x0_fake]
1415 clk_domain=system.clk_domain
1423 ret_data32=4294967295
1424 ret_data64=18446744073709551615
1429 pio=system.iobus.master[12]
1431 [system.realview.lan_fake]
1433 clk_domain=system.clk_domain
1441 ret_data32=4294967295
1442 ret_data64=18446744073709551615
1447 pio=system.iobus.master[19]
1449 [system.realview.local_cpu_timer]
1451 clk_domain=system.clk_domain
1453 gic=system.realview.gic
1459 pio=system.membus.master[4]
1461 [system.realview.mcc]
1463 children=osc_clcd osc_mcc osc_peripheral osc_system_bus
1466 [system.realview.mcc.osc_clcd]
1472 parent=system.realview.realview_io
1475 voltage_domain=system.voltage_domain
1477 [system.realview.mcc.osc_mcc]
1483 parent=system.realview.realview_io
1486 voltage_domain=system.voltage_domain
1488 [system.realview.mcc.osc_peripheral]
1494 parent=system.realview.realview_io
1497 voltage_domain=system.voltage_domain
1499 [system.realview.mcc.osc_system_bus]
1505 parent=system.realview.realview_io
1508 voltage_domain=system.voltage_domain
1510 [system.realview.mmc_fake]
1513 clk_domain=system.clk_domain
1519 pio=system.iobus.master[21]
1521 [system.realview.nvmem]
1524 clk_domain=system.clk_domain
1525 conf_table_reported=false
1532 port=system.membus.master[1]
1534 [system.realview.pci_host]
1536 clk_domain=system.clk_domain
1544 platform=system.realview
1546 pio=system.iobus.master[2]
1548 [system.realview.realview_io]
1550 clk_domain=system.clk_domain
1558 pio=system.iobus.master[1]
1560 [system.realview.rtc]
1563 clk_domain=system.clk_domain
1565 gic=system.realview.gic
1571 time=Thu Jan 1 00:00:00 2009
1572 pio=system.iobus.master[10]
1574 [system.realview.sp810_fake]
1577 clk_domain=system.clk_domain
1583 pio=system.iobus.master[16]
1585 [system.realview.timer0]
1588 clk_domain=system.clk_domain
1592 gic=system.realview.gic
1598 pio=system.iobus.master[3]
1600 [system.realview.timer1]
1603 clk_domain=system.clk_domain
1607 gic=system.realview.gic
1613 pio=system.iobus.master[4]
1615 [system.realview.uart]
1617 clk_domain=system.clk_domain
1620 gic=system.realview.gic
1625 platform=system.realview
1627 terminal=system.terminal
1628 pio=system.iobus.master[0]
1630 [system.realview.uart1_fake]
1633 clk_domain=system.clk_domain
1639 pio=system.iobus.master[13]
1641 [system.realview.uart2_fake]
1644 clk_domain=system.clk_domain
1650 pio=system.iobus.master[14]
1652 [system.realview.uart3_fake]
1655 clk_domain=system.clk_domain
1661 pio=system.iobus.master[15]
1663 [system.realview.usb_fake]
1665 clk_domain=system.clk_domain
1673 ret_data32=4294967295
1674 ret_data64=18446744073709551615
1679 pio=system.iobus.master[20]
1681 [system.realview.vgic]
1683 clk_domain=system.clk_domain
1685 gic=system.realview.gic
1688 platform=system.realview
1692 pio=system.membus.master[3]
1694 [system.realview.vram]
1697 clk_domain=system.clk_domain
1698 conf_table_reported=false
1704 range=402653184:436207615
1705 port=system.iobus.master[11]
1707 [system.realview.watchdog_fake]
1710 clk_domain=system.clk_domain
1716 pio=system.iobus.master[17]
1721 intr_control=system.intrctrl
1728 children=snoop_filter
1729 clk_domain=system.cpu_clk_domain
1734 snoop_filter=system.toL2Bus.snoop_filter
1735 snoop_response_latency=1
1737 use_default_range=false
1739 master=system.l2c.cpu_side
1740 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1742 [system.toL2Bus.snoop_filter]
1746 max_capacity=8388608
1756 [system.voltage_domain]