2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.195792 # Number of seconds simulated
4 sim_ticks 1195791950500 # Number of ticks simulated
5 final_tick 1195791950500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 418462 # Simulator instruction rate (inst/s)
8 host_op_rate 533251 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 8153682245 # Simulator tick rate (ticks/s)
10 host_mem_usage 447424 # Number of bytes of host memory used
11 host_seconds 146.66 # Real time elapsed on the host
12 sim_insts 61370228 # Number of instructions simulated
13 sim_ops 78204808 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.data 6626164 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.data 2903920 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 62155172 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory
26 system.physmem.bytes_written::writebacks 4136128 # Number of bytes written to this memory
27 system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
28 system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
29 system.physmem.bytes_written::total 7163472 # Number of bytes written to this memory
30 system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu0.data 103606 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu1.data 45400 # Number of read requests responded to by this memory
38 system.physmem.num_reads::total 6654629 # Number of read requests responded to by this memory
39 system.physmem.num_writes::writebacks 64627 # Number of write requests responded to by this memory
40 system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
41 system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
42 system.physmem.num_writes::total 821463 # Number of write requests responded to by this memory
43 system.physmem.bw_read::realview.clcd 43405972 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu0.inst 387790 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::cpu0.data 5541235 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_read::cpu1.inst 214429 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu1.data 2428449 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::total 51978249 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_inst_read::cpu0.inst 387790 # Instruction read bandwidth from this memory (bytes/s)
53 system.physmem.bw_inst_read::cpu1.inst 214429 # Instruction read bandwidth from this memory (bytes/s)
54 system.physmem.bw_inst_read::total 602218 # Instruction read bandwidth from this memory (bytes/s)
55 system.physmem.bw_write::writebacks 3458903 # Write bandwidth from this memory (bytes/s)
56 system.physmem.bw_write::cpu0.data 2531631 # Write bandwidth from this memory (bytes/s)
57 system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
58 system.physmem.bw_write::total 5990567 # Write bandwidth from this memory (bytes/s)
59 system.physmem.bw_total::writebacks 3458903 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::realview.clcd 43405972 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
62 system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
63 system.physmem.bw_total::cpu0.inst 387790 # Total bandwidth to/from this memory (bytes/s)
64 system.physmem.bw_total::cpu0.data 8072866 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
66 system.physmem.bw_total::cpu1.inst 214429 # Total bandwidth to/from this memory (bytes/s)
67 system.physmem.bw_total::cpu1.data 2428483 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::total 57968816 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.readReqs 6654629 # Number of read requests accepted
70 system.physmem.writeReqs 821463 # Number of write requests accepted
71 system.physmem.readBursts 6654629 # Number of DRAM read bursts, including those serviced by the write queue
72 system.physmem.writeBursts 821463 # Number of DRAM write bursts, including those merged in the write queue
73 system.physmem.bytesReadDRAM 425873472 # Total number of bytes read from DRAM
74 system.physmem.bytesReadWrQ 22784 # Total number of bytes read from write queue
75 system.physmem.bytesWritten 7293184 # Total number of bytes written to DRAM
76 system.physmem.bytesReadSys 62155172 # Total read bytes from the system interface side
77 system.physmem.bytesWrittenSys 7163472 # Total written bytes from the system interface side
78 system.physmem.servicedByWrQ 356 # Number of DRAM read bursts serviced by the write queue
79 system.physmem.mergedWrBursts 707504 # Number of DRAM write bursts merged with an existing one
80 system.physmem.neitherReadNorWriteReqs 10661 # Number of requests that are neither read nor write
81 system.physmem.perBankRdBursts::0 415730 # Per bank write bursts
82 system.physmem.perBankRdBursts::1 415559 # Per bank write bursts
83 system.physmem.perBankRdBursts::2 414961 # Per bank write bursts
84 system.physmem.perBankRdBursts::3 415335 # Per bank write bursts
85 system.physmem.perBankRdBursts::4 422368 # Per bank write bursts
86 system.physmem.perBankRdBursts::5 415375 # Per bank write bursts
87 system.physmem.perBankRdBursts::6 415446 # Per bank write bursts
88 system.physmem.perBankRdBursts::7 415289 # Per bank write bursts
89 system.physmem.perBankRdBursts::8 415350 # Per bank write bursts
90 system.physmem.perBankRdBursts::9 415631 # Per bank write bursts
91 system.physmem.perBankRdBursts::10 415265 # Per bank write bursts
92 system.physmem.perBankRdBursts::11 414898 # Per bank write bursts
93 system.physmem.perBankRdBursts::12 415491 # Per bank write bursts
94 system.physmem.perBankRdBursts::13 416088 # Per bank write bursts
95 system.physmem.perBankRdBursts::14 415759 # Per bank write bursts
96 system.physmem.perBankRdBursts::15 415728 # Per bank write bursts
97 system.physmem.perBankWrBursts::0 7313 # Per bank write bursts
98 system.physmem.perBankWrBursts::1 7201 # Per bank write bursts
99 system.physmem.perBankWrBursts::2 6692 # Per bank write bursts
100 system.physmem.perBankWrBursts::3 6866 # Per bank write bursts
101 system.physmem.perBankWrBursts::4 7393 # Per bank write bursts
102 system.physmem.perBankWrBursts::5 6958 # Per bank write bursts
103 system.physmem.perBankWrBursts::6 7169 # Per bank write bursts
104 system.physmem.perBankWrBursts::7 6986 # Per bank write bursts
105 system.physmem.perBankWrBursts::8 6988 # Per bank write bursts
106 system.physmem.perBankWrBursts::9 7250 # Per bank write bursts
107 system.physmem.perBankWrBursts::10 6972 # Per bank write bursts
108 system.physmem.perBankWrBursts::11 6687 # Per bank write bursts
109 system.physmem.perBankWrBursts::12 7223 # Per bank write bursts
110 system.physmem.perBankWrBursts::13 7529 # Per bank write bursts
111 system.physmem.perBankWrBursts::14 7375 # Per bank write bursts
112 system.physmem.perBankWrBursts::15 7354 # Per bank write bursts
113 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
114 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
115 system.physmem.totGap 1195787534500 # Total gap between requests
116 system.physmem.readPktSize::0 0 # Read request sizes (log2)
117 system.physmem.readPktSize::1 0 # Read request sizes (log2)
118 system.physmem.readPktSize::2 6825 # Read request sizes (log2)
119 system.physmem.readPktSize::3 6488064 # Read request sizes (log2)
120 system.physmem.readPktSize::4 0 # Read request sizes (log2)
121 system.physmem.readPktSize::5 0 # Read request sizes (log2)
122 system.physmem.readPktSize::6 159740 # Read request sizes (log2)
123 system.physmem.writePktSize::0 0 # Write request sizes (log2)
124 system.physmem.writePktSize::1 0 # Write request sizes (log2)
125 system.physmem.writePktSize::2 756836 # Write request sizes (log2)
126 system.physmem.writePktSize::3 0 # Write request sizes (log2)
127 system.physmem.writePktSize::4 0 # Write request sizes (log2)
128 system.physmem.writePktSize::5 0 # Write request sizes (log2)
129 system.physmem.writePktSize::6 64627 # Write request sizes (log2)
130 system.physmem.rdQLenPdf::0 636769 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::1 483388 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::2 484627 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::3 1579502 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::4 1123930 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::5 1118197 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::6 1114450 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::7 25137 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::8 24391 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::9 9450 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::10 9387 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::11 9266 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::12 8971 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::13 8900 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::14 8855 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::15 8823 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::16 219 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
162 system.physmem.wrQLenPdf::0 5178 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::1 5187 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::2 5182 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::3 5179 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::4 5180 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::5 5179 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::6 5179 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::7 5180 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::8 5177 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::9 5179 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::10 5177 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::11 5178 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::12 5178 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::13 5178 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::14 5179 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::15 5179 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::16 5178 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::19 5180 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::20 5184 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::21 5183 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
194 system.physmem.bytesPerActivate::samples 74963 # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::mean 5778.397556 # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::gmean 392.859970 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::stdev 13041.482454 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::64-71 26098 34.81% 34.81% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::128-135 15301 20.41% 55.23% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::192-199 3417 4.56% 59.78% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::256-263 2337 3.12% 62.90% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::320-327 1552 2.07% 64.97% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-391 1311 1.75% 66.72% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::448-455 1048 1.40% 68.12% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::512-519 1133 1.51% 69.63% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::576-583 708 0.94% 70.57% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::640-647 576 0.77% 71.34% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::704-711 588 0.78% 72.13% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::768-775 600 0.80% 72.93% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::832-839 313 0.42% 73.35% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::896-903 304 0.41% 73.75% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::960-967 211 0.28% 74.03% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::1024-1031 484 0.65% 74.68% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::1088-1095 181 0.24% 74.92% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::1152-1159 133 0.18% 75.10% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::1216-1223 163 0.22% 75.31% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::1280-1287 181 0.24% 75.56% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::1344-1351 117 0.16% 75.71% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::1408-1415 2275 3.03% 78.75% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1472-1479 133 0.18% 78.92% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::1536-1543 94 0.13% 79.05% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::1600-1607 64 0.09% 79.14% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1664-1671 60 0.08% 79.22% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::1728-1735 43 0.06% 79.27% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::1792-1799 123 0.16% 79.44% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.51% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::1920-1927 29 0.04% 79.55% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.57% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::2048-2055 191 0.25% 79.83% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::2112-2119 19 0.03% 79.85% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::2176-2183 18 0.02% 79.88% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::2240-2247 24 0.03% 79.91% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::2304-2311 41 0.05% 79.96% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.98% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::2432-2439 25 0.03% 80.02% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::2496-2503 28 0.04% 80.05% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::2560-2567 24 0.03% 80.09% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::2624-2631 25 0.03% 80.12% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::2688-2695 17 0.02% 80.14% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::2752-2759 20 0.03% 80.17% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::2816-2823 20 0.03% 80.20% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.20% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::2944-2951 20 0.03% 80.23% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::3008-3015 6 0.01% 80.24% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::3072-3079 190 0.25% 80.49% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::3136-3143 23 0.03% 80.52% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::3200-3207 8 0.01% 80.53% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::3264-3271 10 0.01% 80.55% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::3328-3335 98 0.13% 80.68% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.69% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::3456-3463 7 0.01% 80.70% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::3520-3527 16 0.02% 80.72% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::3584-3591 20 0.03% 80.75% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::3648-3655 6 0.01% 80.75% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.78% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::3776-3783 37 0.05% 80.83% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::3840-3847 47 0.06% 80.89% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::3904-3911 17 0.02% 80.91% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::3968-3975 8 0.01% 80.93% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::4032-4039 6 0.01% 80.93% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::4096-4103 197 0.26% 81.20% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::4160-4167 7 0.01% 81.21% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::4224-4231 10 0.01% 81.22% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::4288-4295 14 0.02% 81.24% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.34% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.35% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::4480-4487 14 0.02% 81.37% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.37% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::4608-4615 33 0.04% 81.42% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::4672-4679 14 0.02% 81.43% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.44% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.44% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::4864-4871 23 0.03% 81.47% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::4928-4935 5 0.01% 81.48% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::4992-4999 7 0.01% 81.49% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.51% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::5120-5127 154 0.21% 81.72% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.72% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::5248-5255 14 0.02% 81.74% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::5312-5319 6 0.01% 81.75% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::5376-5383 35 0.05% 81.79% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::5440-5447 170 0.23% 82.02% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::5504-5511 59 0.08% 82.10% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::5632-5639 78 0.10% 82.20% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.20% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::5888-5895 9 0.01% 82.22% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::6144-6151 89 0.12% 82.34% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::6272-6279 2 0.00% 82.34% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::6400-6407 70 0.09% 82.43% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::6464-6471 1 0.00% 82.43% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.44% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.44% # Bytes accessed per row activation
293 system.physmem.bytesPerActivate::6656-6663 108 0.14% 82.58% # Bytes accessed per row activation
294 system.physmem.bytesPerActivate::6848-6855 1 0.00% 82.58% # Bytes accessed per row activation
295 system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.60% # Bytes accessed per row activation
296 system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.61% # Bytes accessed per row activation
297 system.physmem.bytesPerActivate::7168-7175 32 0.04% 82.65% # Bytes accessed per row activation
298 system.physmem.bytesPerActivate::7424-7431 132 0.18% 82.82% # Bytes accessed per row activation
299 system.physmem.bytesPerActivate::7680-7687 28 0.04% 82.86% # Bytes accessed per row activation
300 system.physmem.bytesPerActivate::7936-7943 74 0.10% 82.96% # Bytes accessed per row activation
301 system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.96% # Bytes accessed per row activation
302 system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.96% # Bytes accessed per row activation
303 system.physmem.bytesPerActivate::8192-8199 29 0.04% 83.00% # Bytes accessed per row activation
304 system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.00% # Bytes accessed per row activation
305 system.physmem.bytesPerActivate::8448-8455 75 0.10% 83.10% # Bytes accessed per row activation
306 system.physmem.bytesPerActivate::8704-8711 29 0.04% 83.14% # Bytes accessed per row activation
307 system.physmem.bytesPerActivate::8832-8839 2 0.00% 83.15% # Bytes accessed per row activation
308 system.physmem.bytesPerActivate::8960-8967 130 0.17% 83.32% # Bytes accessed per row activation
309 system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.32% # Bytes accessed per row activation
310 system.physmem.bytesPerActivate::9216-9223 29 0.04% 83.36% # Bytes accessed per row activation
311 system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.36% # Bytes accessed per row activation
312 system.physmem.bytesPerActivate::9472-9479 17 0.02% 83.38% # Bytes accessed per row activation
313 system.physmem.bytesPerActivate::9728-9735 100 0.13% 83.52% # Bytes accessed per row activation
314 system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.52% # Bytes accessed per row activation
315 system.physmem.bytesPerActivate::9984-9991 74 0.10% 83.62% # Bytes accessed per row activation
316 system.physmem.bytesPerActivate::10240-10247 86 0.11% 83.73% # Bytes accessed per row activation
317 system.physmem.bytesPerActivate::10496-10503 12 0.02% 83.75% # Bytes accessed per row activation
318 system.physmem.bytesPerActivate::10752-10759 80 0.11% 83.85% # Bytes accessed per row activation
319 system.physmem.bytesPerActivate::11008-11015 29 0.04% 83.89% # Bytes accessed per row activation
320 system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.89% # Bytes accessed per row activation
321 system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.90% # Bytes accessed per row activation
322 system.physmem.bytesPerActivate::11264-11271 147 0.20% 84.09% # Bytes accessed per row activation
323 system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.09% # Bytes accessed per row activation
324 system.physmem.bytesPerActivate::11520-11527 8 0.01% 84.10% # Bytes accessed per row activation
325 system.physmem.bytesPerActivate::11776-11783 25 0.03% 84.14% # Bytes accessed per row activation
326 system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation
327 system.physmem.bytesPerActivate::12032-12039 77 0.10% 84.24% # Bytes accessed per row activation
328 system.physmem.bytesPerActivate::12288-12295 181 0.24% 84.48% # Bytes accessed per row activation
329 system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.48% # Bytes accessed per row activation
330 system.physmem.bytesPerActivate::12544-12551 36 0.05% 84.53% # Bytes accessed per row activation
331 system.physmem.bytesPerActivate::12800-12807 17 0.02% 84.56% # Bytes accessed per row activation
332 system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.56% # Bytes accessed per row activation
333 system.physmem.bytesPerActivate::13056-13063 77 0.10% 84.66% # Bytes accessed per row activation
334 system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.66% # Bytes accessed per row activation
335 system.physmem.bytesPerActivate::13312-13319 164 0.22% 84.88% # Bytes accessed per row activation
336 system.physmem.bytesPerActivate::13568-13575 12 0.02% 84.90% # Bytes accessed per row activation
337 system.physmem.bytesPerActivate::13824-13831 12 0.02% 84.91% # Bytes accessed per row activation
338 system.physmem.bytesPerActivate::13952-13959 1 0.00% 84.91% # Bytes accessed per row activation
339 system.physmem.bytesPerActivate::14080-14087 27 0.04% 84.95% # Bytes accessed per row activation
340 system.physmem.bytesPerActivate::14144-14151 1 0.00% 84.95% # Bytes accessed per row activation
341 system.physmem.bytesPerActivate::14208-14215 3 0.00% 84.95% # Bytes accessed per row activation
342 system.physmem.bytesPerActivate::14336-14343 162 0.22% 85.17% # Bytes accessed per row activation
343 system.physmem.bytesPerActivate::14592-14599 88 0.12% 85.29% # Bytes accessed per row activation
344 system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.29% # Bytes accessed per row activation
345 system.physmem.bytesPerActivate::14848-14855 21 0.03% 85.32% # Bytes accessed per row activation
346 system.physmem.bytesPerActivate::15040-15047 2 0.00% 85.32% # Bytes accessed per row activation
347 system.physmem.bytesPerActivate::15104-15111 28 0.04% 85.36% # Bytes accessed per row activation
348 system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.36% # Bytes accessed per row activation
349 system.physmem.bytesPerActivate::15360-15367 218 0.29% 85.65% # Bytes accessed per row activation
350 system.physmem.bytesPerActivate::15616-15623 20 0.03% 85.68% # Bytes accessed per row activation
351 system.physmem.bytesPerActivate::15872-15879 17 0.02% 85.70% # Bytes accessed per row activation
352 system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.70% # Bytes accessed per row activation
353 system.physmem.bytesPerActivate::16128-16135 8 0.01% 85.71% # Bytes accessed per row activation
354 system.physmem.bytesPerActivate::16256-16263 2 0.00% 85.71% # Bytes accessed per row activation
355 system.physmem.bytesPerActivate::16384-16391 272 0.36% 86.08% # Bytes accessed per row activation
356 system.physmem.bytesPerActivate::16640-16647 7 0.01% 86.09% # Bytes accessed per row activation
357 system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.09% # Bytes accessed per row activation
358 system.physmem.bytesPerActivate::16896-16903 16 0.02% 86.11% # Bytes accessed per row activation
359 system.physmem.bytesPerActivate::17152-17159 23 0.03% 86.14% # Bytes accessed per row activation
360 system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.14% # Bytes accessed per row activation
361 system.physmem.bytesPerActivate::17408-17415 224 0.30% 86.44% # Bytes accessed per row activation
362 system.physmem.bytesPerActivate::17600-17607 2 0.00% 86.44% # Bytes accessed per row activation
363 system.physmem.bytesPerActivate::17664-17671 24 0.03% 86.47% # Bytes accessed per row activation
364 system.physmem.bytesPerActivate::17920-17927 18 0.02% 86.50% # Bytes accessed per row activation
365 system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.50% # Bytes accessed per row activation
366 system.physmem.bytesPerActivate::18176-18183 85 0.11% 86.61% # Bytes accessed per row activation
367 system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation
368 system.physmem.bytesPerActivate::18432-18439 154 0.21% 86.82% # Bytes accessed per row activation
369 system.physmem.bytesPerActivate::18688-18695 30 0.04% 86.86% # Bytes accessed per row activation
370 system.physmem.bytesPerActivate::18944-18951 16 0.02% 86.88% # Bytes accessed per row activation
371 system.physmem.bytesPerActivate::19200-19207 19 0.03% 86.91% # Bytes accessed per row activation
372 system.physmem.bytesPerActivate::19328-19335 1 0.00% 86.91% # Bytes accessed per row activation
373 system.physmem.bytesPerActivate::19456-19463 169 0.23% 87.13% # Bytes accessed per row activation
374 system.physmem.bytesPerActivate::19712-19719 71 0.09% 87.23% # Bytes accessed per row activation
375 system.physmem.bytesPerActivate::19968-19975 12 0.02% 87.24% # Bytes accessed per row activation
376 system.physmem.bytesPerActivate::20224-20231 44 0.06% 87.30% # Bytes accessed per row activation
377 system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.30% # Bytes accessed per row activation
378 system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.30% # Bytes accessed per row activation
379 system.physmem.bytesPerActivate::20480-20487 167 0.22% 87.53% # Bytes accessed per row activation
380 system.physmem.bytesPerActivate::20608-20615 3 0.00% 87.53% # Bytes accessed per row activation
381 system.physmem.bytesPerActivate::20736-20743 78 0.10% 87.64% # Bytes accessed per row activation
382 system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.64% # Bytes accessed per row activation
383 system.physmem.bytesPerActivate::20864-20871 1 0.00% 87.64% # Bytes accessed per row activation
384 system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.67% # Bytes accessed per row activation
385 system.physmem.bytesPerActivate::21184-21191 2 0.00% 87.67% # Bytes accessed per row activation
386 system.physmem.bytesPerActivate::21248-21255 12 0.02% 87.69% # Bytes accessed per row activation
387 system.physmem.bytesPerActivate::21376-21383 1 0.00% 87.69% # Bytes accessed per row activation
388 system.physmem.bytesPerActivate::21504-21511 139 0.19% 87.88% # Bytes accessed per row activation
389 system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.91% # Bytes accessed per row activation
390 system.physmem.bytesPerActivate::22016-22023 79 0.11% 88.01% # Bytes accessed per row activation
391 system.physmem.bytesPerActivate::22208-22215 1 0.00% 88.01% # Bytes accessed per row activation
392 system.physmem.bytesPerActivate::22272-22279 9 0.01% 88.03% # Bytes accessed per row activation
393 system.physmem.bytesPerActivate::22528-22535 89 0.12% 88.14% # Bytes accessed per row activation
394 system.physmem.bytesPerActivate::22592-22599 2 0.00% 88.15% # Bytes accessed per row activation
395 system.physmem.bytesPerActivate::22784-22791 71 0.09% 88.24% # Bytes accessed per row activation
396 system.physmem.bytesPerActivate::23040-23047 103 0.14% 88.38% # Bytes accessed per row activation
397 system.physmem.bytesPerActivate::23296-23303 16 0.02% 88.40% # Bytes accessed per row activation
398 system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.40% # Bytes accessed per row activation
399 system.physmem.bytesPerActivate::23552-23559 26 0.03% 88.44% # Bytes accessed per row activation
400 system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.44% # Bytes accessed per row activation
401 system.physmem.bytesPerActivate::23808-23815 131 0.17% 88.61% # Bytes accessed per row activation
402 system.physmem.bytesPerActivate::24064-24071 26 0.03% 88.65% # Bytes accessed per row activation
403 system.physmem.bytesPerActivate::24320-24327 72 0.10% 88.74% # Bytes accessed per row activation
404 system.physmem.bytesPerActivate::24384-24391 1 0.00% 88.75% # Bytes accessed per row activation
405 system.physmem.bytesPerActivate::24576-24583 23 0.03% 88.78% # Bytes accessed per row activation
406 system.physmem.bytesPerActivate::24832-24839 77 0.10% 88.88% # Bytes accessed per row activation
407 system.physmem.bytesPerActivate::25088-25095 26 0.03% 88.91% # Bytes accessed per row activation
408 system.physmem.bytesPerActivate::25216-25223 1 0.00% 88.91% # Bytes accessed per row activation
409 system.physmem.bytesPerActivate::25344-25351 132 0.18% 89.09% # Bytes accessed per row activation
410 system.physmem.bytesPerActivate::25600-25607 29 0.04% 89.13% # Bytes accessed per row activation
411 system.physmem.bytesPerActivate::25856-25863 15 0.02% 89.15% # Bytes accessed per row activation
412 system.physmem.bytesPerActivate::26112-26119 98 0.13% 89.28% # Bytes accessed per row activation
413 system.physmem.bytesPerActivate::26240-26247 1 0.00% 89.28% # Bytes accessed per row activation
414 system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.28% # Bytes accessed per row activation
415 system.physmem.bytesPerActivate::26368-26375 75 0.10% 89.38% # Bytes accessed per row activation
416 system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.39% # Bytes accessed per row activation
417 system.physmem.bytesPerActivate::26560-26567 1 0.00% 89.39% # Bytes accessed per row activation
418 system.physmem.bytesPerActivate::26624-26631 84 0.11% 89.50% # Bytes accessed per row activation
419 system.physmem.bytesPerActivate::26880-26887 13 0.02% 89.52% # Bytes accessed per row activation
420 system.physmem.bytesPerActivate::27136-27143 81 0.11% 89.62% # Bytes accessed per row activation
421 system.physmem.bytesPerActivate::27392-27399 23 0.03% 89.65% # Bytes accessed per row activation
422 system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.66% # Bytes accessed per row activation
423 system.physmem.bytesPerActivate::27648-27655 143 0.19% 89.85% # Bytes accessed per row activation
424 system.physmem.bytesPerActivate::27840-27847 1 0.00% 89.85% # Bytes accessed per row activation
425 system.physmem.bytesPerActivate::27904-27911 9 0.01% 89.86% # Bytes accessed per row activation
426 system.physmem.bytesPerActivate::28032-28039 1 0.00% 89.86% # Bytes accessed per row activation
427 system.physmem.bytesPerActivate::28160-28167 25 0.03% 89.90% # Bytes accessed per row activation
428 system.physmem.bytesPerActivate::28288-28295 1 0.00% 89.90% # Bytes accessed per row activation
429 system.physmem.bytesPerActivate::28416-28423 80 0.11% 90.00% # Bytes accessed per row activation
430 system.physmem.bytesPerActivate::28544-28551 3 0.00% 90.01% # Bytes accessed per row activation
431 system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.01% # Bytes accessed per row activation
432 system.physmem.bytesPerActivate::28672-28679 176 0.23% 90.24% # Bytes accessed per row activation
433 system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.24% # Bytes accessed per row activation
434 system.physmem.bytesPerActivate::28928-28935 40 0.05% 90.30% # Bytes accessed per row activation
435 system.physmem.bytesPerActivate::29184-29191 16 0.02% 90.32% # Bytes accessed per row activation
436 system.physmem.bytesPerActivate::29440-29447 72 0.10% 90.42% # Bytes accessed per row activation
437 system.physmem.bytesPerActivate::29632-29639 1 0.00% 90.42% # Bytes accessed per row activation
438 system.physmem.bytesPerActivate::29696-29703 167 0.22% 90.64% # Bytes accessed per row activation
439 system.physmem.bytesPerActivate::29760-29767 1 0.00% 90.64% # Bytes accessed per row activation
440 system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.66% # Bytes accessed per row activation
441 system.physmem.bytesPerActivate::30208-30215 6 0.01% 90.67% # Bytes accessed per row activation
442 system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.67% # Bytes accessed per row activation
443 system.physmem.bytesPerActivate::30464-30471 29 0.04% 90.71% # Bytes accessed per row activation
444 system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation
445 system.physmem.bytesPerActivate::30720-30727 150 0.20% 90.91% # Bytes accessed per row activation
446 system.physmem.bytesPerActivate::30848-30855 1 0.00% 90.91% # Bytes accessed per row activation
447 system.physmem.bytesPerActivate::30976-30983 84 0.11% 91.02% # Bytes accessed per row activation
448 system.physmem.bytesPerActivate::31232-31239 19 0.03% 91.05% # Bytes accessed per row activation
449 system.physmem.bytesPerActivate::31488-31495 30 0.04% 91.09% # Bytes accessed per row activation
450 system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation
451 system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.09% # Bytes accessed per row activation
452 system.physmem.bytesPerActivate::31744-31751 220 0.29% 91.38% # Bytes accessed per row activation
453 system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.39% # Bytes accessed per row activation
454 system.physmem.bytesPerActivate::32000-32007 20 0.03% 91.41% # Bytes accessed per row activation
455 system.physmem.bytesPerActivate::32256-32263 17 0.02% 91.43% # Bytes accessed per row activation
456 system.physmem.bytesPerActivate::32512-32519 10 0.01% 91.45% # Bytes accessed per row activation
457 system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.45% # Bytes accessed per row activation
458 system.physmem.bytesPerActivate::32768-32775 269 0.36% 91.81% # Bytes accessed per row activation
459 system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.83% # Bytes accessed per row activation
460 system.physmem.bytesPerActivate::33216-33223 1 0.00% 91.83% # Bytes accessed per row activation
461 system.physmem.bytesPerActivate::33280-33287 25 0.03% 91.86% # Bytes accessed per row activation
462 system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.86% # Bytes accessed per row activation
463 system.physmem.bytesPerActivate::33536-33543 22 0.03% 91.89% # Bytes accessed per row activation
464 system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.89% # Bytes accessed per row activation
465 system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.90% # Bytes accessed per row activation
466 system.physmem.bytesPerActivate::33728-33735 1 0.00% 91.90% # Bytes accessed per row activation
467 system.physmem.bytesPerActivate::33792-33799 216 0.29% 92.19% # Bytes accessed per row activation
468 system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.19% # Bytes accessed per row activation
469 system.physmem.bytesPerActivate::34048-34055 26 0.03% 92.22% # Bytes accessed per row activation
470 system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.22% # Bytes accessed per row activation
471 system.physmem.bytesPerActivate::34304-34311 19 0.03% 92.25% # Bytes accessed per row activation
472 system.physmem.bytesPerActivate::34560-34567 84 0.11% 92.36% # Bytes accessed per row activation
473 system.physmem.bytesPerActivate::34688-34695 2 0.00% 92.36% # Bytes accessed per row activation
474 system.physmem.bytesPerActivate::34816-34823 148 0.20% 92.56% # Bytes accessed per row activation
475 system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.56% # Bytes accessed per row activation
476 system.physmem.bytesPerActivate::35072-35079 27 0.04% 92.60% # Bytes accessed per row activation
477 system.physmem.bytesPerActivate::35328-35335 6 0.01% 92.61% # Bytes accessed per row activation
478 system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.62% # Bytes accessed per row activation
479 system.physmem.bytesPerActivate::35776-35783 1 0.00% 92.62% # Bytes accessed per row activation
480 system.physmem.bytesPerActivate::35840-35847 165 0.22% 92.84% # Bytes accessed per row activation
481 system.physmem.bytesPerActivate::35904-35911 1 0.00% 92.85% # Bytes accessed per row activation
482 system.physmem.bytesPerActivate::36096-36103 71 0.09% 92.94% # Bytes accessed per row activation
483 system.physmem.bytesPerActivate::36352-36359 14 0.02% 92.96% # Bytes accessed per row activation
484 system.physmem.bytesPerActivate::36480-36487 1 0.00% 92.96% # Bytes accessed per row activation
485 system.physmem.bytesPerActivate::36608-36615 37 0.05% 93.01% # Bytes accessed per row activation
486 system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.01% # Bytes accessed per row activation
487 system.physmem.bytesPerActivate::36864-36871 169 0.23% 93.24% # Bytes accessed per row activation
488 system.physmem.bytesPerActivate::36928-36935 1 0.00% 93.24% # Bytes accessed per row activation
489 system.physmem.bytesPerActivate::36992-36999 2 0.00% 93.24% # Bytes accessed per row activation
490 system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.35% # Bytes accessed per row activation
491 system.physmem.bytesPerActivate::37248-37255 1 0.00% 93.35% # Bytes accessed per row activation
492 system.physmem.bytesPerActivate::37376-37383 25 0.03% 93.38% # Bytes accessed per row activation
493 system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.38% # Bytes accessed per row activation
494 system.physmem.bytesPerActivate::37632-37639 9 0.01% 93.39% # Bytes accessed per row activation
495 system.physmem.bytesPerActivate::37888-37895 142 0.19% 93.58% # Bytes accessed per row activation
496 system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.58% # Bytes accessed per row activation
497 system.physmem.bytesPerActivate::38144-38151 22 0.03% 93.61% # Bytes accessed per row activation
498 system.physmem.bytesPerActivate::38400-38407 79 0.11% 93.72% # Bytes accessed per row activation
499 system.physmem.bytesPerActivate::38656-38663 11 0.01% 93.73% # Bytes accessed per row activation
500 system.physmem.bytesPerActivate::38912-38919 85 0.11% 93.85% # Bytes accessed per row activation
501 system.physmem.bytesPerActivate::38976-38983 1 0.00% 93.85% # Bytes accessed per row activation
502 system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.85% # Bytes accessed per row activation
503 system.physmem.bytesPerActivate::39168-39175 73 0.10% 93.95% # Bytes accessed per row activation
504 system.physmem.bytesPerActivate::39232-39239 2 0.00% 93.95% # Bytes accessed per row activation
505 system.physmem.bytesPerActivate::39424-39431 96 0.13% 94.08% # Bytes accessed per row activation
506 system.physmem.bytesPerActivate::39680-39687 14 0.02% 94.10% # Bytes accessed per row activation
507 system.physmem.bytesPerActivate::39936-39943 27 0.04% 94.13% # Bytes accessed per row activation
508 system.physmem.bytesPerActivate::40192-40199 131 0.17% 94.31% # Bytes accessed per row activation
509 system.physmem.bytesPerActivate::40320-40327 1 0.00% 94.31% # Bytes accessed per row activation
510 system.physmem.bytesPerActivate::40448-40455 24 0.03% 94.34% # Bytes accessed per row activation
511 system.physmem.bytesPerActivate::40512-40519 1 0.00% 94.34% # Bytes accessed per row activation
512 system.physmem.bytesPerActivate::40704-40711 75 0.10% 94.44% # Bytes accessed per row activation
513 system.physmem.bytesPerActivate::40768-40775 1 0.00% 94.44% # Bytes accessed per row activation
514 system.physmem.bytesPerActivate::40960-40967 23 0.03% 94.47% # Bytes accessed per row activation
515 system.physmem.bytesPerActivate::41152-41159 1 0.00% 94.48% # Bytes accessed per row activation
516 system.physmem.bytesPerActivate::41216-41223 72 0.10% 94.57% # Bytes accessed per row activation
517 system.physmem.bytesPerActivate::41344-41351 1 0.00% 94.57% # Bytes accessed per row activation
518 system.physmem.bytesPerActivate::41472-41479 24 0.03% 94.61% # Bytes accessed per row activation
519 system.physmem.bytesPerActivate::41728-41735 130 0.17% 94.78% # Bytes accessed per row activation
520 system.physmem.bytesPerActivate::41984-41991 25 0.03% 94.81% # Bytes accessed per row activation
521 system.physmem.bytesPerActivate::42240-42247 15 0.02% 94.83% # Bytes accessed per row activation
522 system.physmem.bytesPerActivate::42496-42503 101 0.13% 94.97% # Bytes accessed per row activation
523 system.physmem.bytesPerActivate::42752-42759 70 0.09% 95.06% # Bytes accessed per row activation
524 system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.06% # Bytes accessed per row activation
525 system.physmem.bytesPerActivate::43008-43015 85 0.11% 95.17% # Bytes accessed per row activation
526 system.physmem.bytesPerActivate::43264-43271 8 0.01% 95.19% # Bytes accessed per row activation
527 system.physmem.bytesPerActivate::43520-43527 78 0.10% 95.29% # Bytes accessed per row activation
528 system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.29% # Bytes accessed per row activation
529 system.physmem.bytesPerActivate::43776-43783 24 0.03% 95.32% # Bytes accessed per row activation
530 system.physmem.bytesPerActivate::44032-44039 140 0.19% 95.51% # Bytes accessed per row activation
531 system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.53% # Bytes accessed per row activation
532 system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.53% # Bytes accessed per row activation
533 system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.53% # Bytes accessed per row activation
534 system.physmem.bytesPerActivate::44544-44551 23 0.03% 95.56% # Bytes accessed per row activation
535 system.physmem.bytesPerActivate::44800-44807 80 0.11% 95.67% # Bytes accessed per row activation
536 system.physmem.bytesPerActivate::44928-44935 2 0.00% 95.67% # Bytes accessed per row activation
537 system.physmem.bytesPerActivate::45056-45063 165 0.22% 95.89% # Bytes accessed per row activation
538 system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.89% # Bytes accessed per row activation
539 system.physmem.bytesPerActivate::45248-45255 1 0.00% 95.89% # Bytes accessed per row activation
540 system.physmem.bytesPerActivate::45312-45319 38 0.05% 95.94% # Bytes accessed per row activation
541 system.physmem.bytesPerActivate::45568-45575 12 0.02% 95.96% # Bytes accessed per row activation
542 system.physmem.bytesPerActivate::45824-45831 71 0.09% 96.05% # Bytes accessed per row activation
543 system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.05% # Bytes accessed per row activation
544 system.physmem.bytesPerActivate::46080-46087 165 0.22% 96.27% # Bytes accessed per row activation
545 system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.28% # Bytes accessed per row activation
546 system.physmem.bytesPerActivate::46336-46343 15 0.02% 96.30% # Bytes accessed per row activation
547 system.physmem.bytesPerActivate::46592-46599 12 0.02% 96.31% # Bytes accessed per row activation
548 system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.31% # Bytes accessed per row activation
549 system.physmem.bytesPerActivate::46848-46855 31 0.04% 96.35% # Bytes accessed per row activation
550 system.physmem.bytesPerActivate::47104-47111 151 0.20% 96.56% # Bytes accessed per row activation
551 system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.56% # Bytes accessed per row activation
552 system.physmem.bytesPerActivate::47360-47367 87 0.12% 96.67% # Bytes accessed per row activation
553 system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.67% # Bytes accessed per row activation
554 system.physmem.bytesPerActivate::47616-47623 21 0.03% 96.70% # Bytes accessed per row activation
555 system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.70% # Bytes accessed per row activation
556 system.physmem.bytesPerActivate::47872-47879 24 0.03% 96.74% # Bytes accessed per row activation
557 system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.74% # Bytes accessed per row activation
558 system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.74% # Bytes accessed per row activation
559 system.physmem.bytesPerActivate::48128-48135 239 0.32% 97.06% # Bytes accessed per row activation
560 system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.06% # Bytes accessed per row activation
561 system.physmem.bytesPerActivate::48256-48263 1 0.00% 97.06% # Bytes accessed per row activation
562 system.physmem.bytesPerActivate::48384-48391 36 0.05% 97.11% # Bytes accessed per row activation
563 system.physmem.bytesPerActivate::48640-48647 14 0.02% 97.13% # Bytes accessed per row activation
564 system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation
565 system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.15% # Bytes accessed per row activation
566 system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.16% # Bytes accessed per row activation
567 system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.16% # Bytes accessed per row activation
568 system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation
569 system.physmem.bytesPerActivate::49152-49159 2125 2.83% 100.00% # Bytes accessed per row activation
570 system.physmem.bytesPerActivate::total 74963 # Bytes accessed per row activation
571 system.physmem.totQLat 159518930750 # Total ticks spent queuing
572 system.physmem.totMemAccLat 202571234500 # Total ticks spent from burst creation until serviced by the DRAM
573 system.physmem.totBusLat 33271365000 # Total ticks spent in databus transfers
574 system.physmem.totBankLat 9780938750 # Total ticks spent accessing banks
575 system.physmem.avgQLat 23972.41 # Average queueing delay per DRAM burst
576 system.physmem.avgBankLat 1469.87 # Average bank access latency per DRAM burst
577 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
578 system.physmem.avgMemAccLat 30442.28 # Average memory access latency per DRAM burst
579 system.physmem.avgRdBW 356.14 # Average DRAM read bandwidth in MiByte/s
580 system.physmem.avgWrBW 6.10 # Average achieved write bandwidth in MiByte/s
581 system.physmem.avgRdBWSys 51.98 # Average system read bandwidth in MiByte/s
582 system.physmem.avgWrBWSys 5.99 # Average system write bandwidth in MiByte/s
583 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
584 system.physmem.busUtil 2.83 # Data bus utilization in percentage
585 system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads
586 system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
587 system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
588 system.physmem.avgWrQLen 12.12 # Average write queue length when enqueuing
589 system.physmem.readRowHits 6598430 # Number of row buffer hits during reads
590 system.physmem.writeRowHits 94836 # Number of row buffer hits during writes
591 system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads
592 system.physmem.writeRowHitRate 83.22 # Row buffer hit rate for writes
593 system.physmem.avgGap 159948.21 # Average gap between requests
594 system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined
595 system.physmem.prechargeAllPercent 4.87 # Percentage of time for which DRAM has all the banks in precharge state
596 system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
597 system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
598 system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
599 system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
600 system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
601 system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
602 system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
603 system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
604 system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
605 system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
606 system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
607 system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
608 system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
609 system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
610 system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
611 system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
612 system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
613 system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
614 system.membus.throughput 59983824 # Throughput (bytes/s)
615 system.membus.trans_dist::ReadReq 7703157 # Transaction distribution
616 system.membus.trans_dist::ReadResp 7703157 # Transaction distribution
617 system.membus.trans_dist::WriteReq 767205 # Transaction distribution
618 system.membus.trans_dist::WriteResp 767205 # Transaction distribution
619 system.membus.trans_dist::Writeback 64627 # Transaction distribution
620 system.membus.trans_dist::UpgradeReq 27746 # Transaction distribution
621 system.membus.trans_dist::SCUpgradeReq 16446 # Transaction distribution
622 system.membus.trans_dist::UpgradeResp 10661 # Transaction distribution
623 system.membus.trans_dist::ReadExReq 137744 # Transaction distribution
624 system.membus.trans_dist::ReadExResp 137297 # Transaction distribution
625 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes)
626 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
627 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes)
628 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
629 system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes)
630 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966729 # Packet count per connected master and slave (bytes)
631 system.membus.pkt_count_system.l2c.mem_side::total 4359117 # Packet count per connected master and slave (bytes)
632 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
633 system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
634 system.membus.pkt_count::total 17335245 # Packet count per connected master and slave (bytes)
635 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes)
636 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
637 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes)
638 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
639 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes)
640 system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes)
641 system.membus.tot_pkt_size_system.l2c.mem_side::total 19823662 # Cumulative packet size per connected master and slave (bytes)
642 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
643 system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
644 system.membus.tot_pkt_size::total 71728174 # Cumulative packet size per connected master and slave (bytes)
645 system.membus.data_through_bus 71728174 # Total data (bytes)
646 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
647 system.membus.reqLayer0.occupancy 1224786000 # Layer occupancy (ticks)
648 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
649 system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
650 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
651 system.membus.reqLayer2.occupancy 7986500 # Layer occupancy (ticks)
652 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
653 system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
654 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
655 system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks)
656 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
657 system.membus.reqLayer6.occupancy 9213145499 # Layer occupancy (ticks)
658 system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
659 system.membus.respLayer1.occupancy 5079077969 # Layer occupancy (ticks)
660 system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
661 system.membus.respLayer2.occupancy 14657796999 # Layer occupancy (ticks)
662 system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
663 system.l2c.tags.replacements 69622 # number of replacements
664 system.l2c.tags.tagsinuse 53154.714662 # Cycle average of tags in use
665 system.l2c.tags.total_refs 1651251 # Total number of references to valid blocks.
666 system.l2c.tags.sampled_refs 134786 # Sample count of references to valid blocks.
667 system.l2c.tags.avg_refs 12.250909 # Average number of references to valid blocks.
668 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
669 system.l2c.tags.occ_blocks::writebacks 40043.388352 # Average occupied blocks per requestor
670 system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667642 # Average occupied blocks per requestor
671 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor
672 system.l2c.tags.occ_blocks::cpu0.inst 4637.694613 # Average occupied blocks per requestor
673 system.l2c.tags.occ_blocks::cpu0.data 5787.547519 # Average occupied blocks per requestor
674 system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor
675 system.l2c.tags.occ_blocks::cpu1.inst 1927.667021 # Average occupied blocks per requestor
676 system.l2c.tags.occ_blocks::cpu1.data 755.746308 # Average occupied blocks per requestor
677 system.l2c.tags.occ_percent::writebacks 0.611014 # Average percentage of cache occupancy
678 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy
679 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
680 system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy
681 system.l2c.tags.occ_percent::cpu0.data 0.088311 # Average percentage of cache occupancy
682 system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
683 system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy
684 system.l2c.tags.occ_percent::cpu1.data 0.011532 # Average percentage of cache occupancy
685 system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy
686 system.l2c.ReadReq_hits::cpu0.dtb.walker 4526 # number of ReadReq hits
687 system.l2c.ReadReq_hits::cpu0.itb.walker 1443 # number of ReadReq hits
688 system.l2c.ReadReq_hits::cpu0.inst 483144 # number of ReadReq hits
689 system.l2c.ReadReq_hits::cpu0.data 241974 # number of ReadReq hits
690 system.l2c.ReadReq_hits::cpu1.dtb.walker 3792 # number of ReadReq hits
691 system.l2c.ReadReq_hits::cpu1.itb.walker 1866 # number of ReadReq hits
692 system.l2c.ReadReq_hits::cpu1.inst 372505 # number of ReadReq hits
693 system.l2c.ReadReq_hits::cpu1.data 110561 # number of ReadReq hits
694 system.l2c.ReadReq_hits::total 1219811 # number of ReadReq hits
695 system.l2c.Writeback_hits::writebacks 576138 # number of Writeback hits
696 system.l2c.Writeback_hits::total 576138 # number of Writeback hits
697 system.l2c.UpgradeReq_hits::cpu0.data 1247 # number of UpgradeReq hits
698 system.l2c.UpgradeReq_hits::cpu1.data 445 # number of UpgradeReq hits
699 system.l2c.UpgradeReq_hits::total 1692 # number of UpgradeReq hits
700 system.l2c.SCUpgradeReq_hits::cpu0.data 260 # number of SCUpgradeReq hits
701 system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits
702 system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits
703 system.l2c.ReadExReq_hits::cpu0.data 65526 # number of ReadExReq hits
704 system.l2c.ReadExReq_hits::cpu1.data 45407 # number of ReadExReq hits
705 system.l2c.ReadExReq_hits::total 110933 # number of ReadExReq hits
706 system.l2c.demand_hits::cpu0.dtb.walker 4526 # number of demand (read+write) hits
707 system.l2c.demand_hits::cpu0.itb.walker 1443 # number of demand (read+write) hits
708 system.l2c.demand_hits::cpu0.inst 483144 # number of demand (read+write) hits
709 system.l2c.demand_hits::cpu0.data 307500 # number of demand (read+write) hits
710 system.l2c.demand_hits::cpu1.dtb.walker 3792 # number of demand (read+write) hits
711 system.l2c.demand_hits::cpu1.itb.walker 1866 # number of demand (read+write) hits
712 system.l2c.demand_hits::cpu1.inst 372505 # number of demand (read+write) hits
713 system.l2c.demand_hits::cpu1.data 155968 # number of demand (read+write) hits
714 system.l2c.demand_hits::total 1330744 # number of demand (read+write) hits
715 system.l2c.overall_hits::cpu0.dtb.walker 4526 # number of overall hits
716 system.l2c.overall_hits::cpu0.itb.walker 1443 # number of overall hits
717 system.l2c.overall_hits::cpu0.inst 483144 # number of overall hits
718 system.l2c.overall_hits::cpu0.data 307500 # number of overall hits
719 system.l2c.overall_hits::cpu1.dtb.walker 3792 # number of overall hits
720 system.l2c.overall_hits::cpu1.itb.walker 1866 # number of overall hits
721 system.l2c.overall_hits::cpu1.inst 372505 # number of overall hits
722 system.l2c.overall_hits::cpu1.data 155968 # number of overall hits
723 system.l2c.overall_hits::total 1330744 # number of overall hits
724 system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
725 system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
726 system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses
727 system.l2c.ReadReq_misses::cpu0.data 9714 # number of ReadReq misses
728 system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
729 system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses
730 system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses
731 system.l2c.ReadReq_misses::total 22444 # number of ReadReq misses
732 system.l2c.UpgradeReq_misses::cpu0.data 3977 # number of UpgradeReq misses
733 system.l2c.UpgradeReq_misses::cpu1.data 3384 # number of UpgradeReq misses
734 system.l2c.UpgradeReq_misses::total 7361 # number of UpgradeReq misses
735 system.l2c.SCUpgradeReq_misses::cpu0.data 388 # number of SCUpgradeReq misses
736 system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses
737 system.l2c.SCUpgradeReq_misses::total 867 # number of SCUpgradeReq misses
738 system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses
739 system.l2c.ReadExReq_misses::cpu1.data 44594 # number of ReadExReq misses
740 system.l2c.ReadExReq_misses::total 139730 # number of ReadExReq misses
741 system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
742 system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
743 system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses
744 system.l2c.demand_misses::cpu0.data 104850 # number of demand (read+write) misses
745 system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
746 system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses
747 system.l2c.demand_misses::cpu1.data 46484 # number of demand (read+write) misses
748 system.l2c.demand_misses::total 162174 # number of demand (read+write) misses
749 system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
750 system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
751 system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses
752 system.l2c.overall_misses::cpu0.data 104850 # number of overall misses
753 system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
754 system.l2c.overall_misses::cpu1.inst 4001 # number of overall misses
755 system.l2c.overall_misses::cpu1.data 46484 # number of overall misses
756 system.l2c.overall_misses::total 162174 # number of overall misses
757 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 303000 # number of ReadReq miss cycles
758 system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
759 system.l2c.ReadReq_miss_latency::cpu0.inst 496292750 # number of ReadReq miss cycles
760 system.l2c.ReadReq_miss_latency::cpu0.data 730648247 # number of ReadReq miss cycles
761 system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles
762 system.l2c.ReadReq_miss_latency::cpu1.inst 288737750 # number of ReadReq miss cycles
763 system.l2c.ReadReq_miss_latency::cpu1.data 148289750 # number of ReadReq miss cycles
764 system.l2c.ReadReq_miss_latency::total 1664495497 # number of ReadReq miss cycles
765 system.l2c.UpgradeReq_miss_latency::cpu0.data 11403008 # number of UpgradeReq miss cycles
766 system.l2c.UpgradeReq_miss_latency::cpu1.data 12327473 # number of UpgradeReq miss cycles
767 system.l2c.UpgradeReq_miss_latency::total 23730481 # number of UpgradeReq miss cycles
768 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1953416 # number of SCUpgradeReq miss cycles
769 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1118452 # number of SCUpgradeReq miss cycles
770 system.l2c.SCUpgradeReq_miss_latency::total 3071868 # number of SCUpgradeReq miss cycles
771 system.l2c.ReadExReq_miss_latency::cpu0.data 6560641426 # number of ReadExReq miss cycles
772 system.l2c.ReadExReq_miss_latency::cpu1.data 3440385640 # number of ReadExReq miss cycles
773 system.l2c.ReadExReq_miss_latency::total 10001027066 # number of ReadExReq miss cycles
774 system.l2c.demand_miss_latency::cpu0.dtb.walker 303000 # number of demand (read+write) miss cycles
775 system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
776 system.l2c.demand_miss_latency::cpu0.inst 496292750 # number of demand (read+write) miss cycles
777 system.l2c.demand_miss_latency::cpu0.data 7291289673 # number of demand (read+write) miss cycles
778 system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles
779 system.l2c.demand_miss_latency::cpu1.inst 288737750 # number of demand (read+write) miss cycles
780 system.l2c.demand_miss_latency::cpu1.data 3588675390 # number of demand (read+write) miss cycles
781 system.l2c.demand_miss_latency::total 11665522563 # number of demand (read+write) miss cycles
782 system.l2c.overall_miss_latency::cpu0.dtb.walker 303000 # number of overall miss cycles
783 system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
784 system.l2c.overall_miss_latency::cpu0.inst 496292750 # number of overall miss cycles
785 system.l2c.overall_miss_latency::cpu0.data 7291289673 # number of overall miss cycles
786 system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles
787 system.l2c.overall_miss_latency::cpu1.inst 288737750 # number of overall miss cycles
788 system.l2c.overall_miss_latency::cpu1.data 3588675390 # number of overall miss cycles
789 system.l2c.overall_miss_latency::total 11665522563 # number of overall miss cycles
790 system.l2c.ReadReq_accesses::cpu0.dtb.walker 4530 # number of ReadReq accesses(hits+misses)
791 system.l2c.ReadReq_accesses::cpu0.itb.walker 1445 # number of ReadReq accesses(hits+misses)
792 system.l2c.ReadReq_accesses::cpu0.inst 489976 # number of ReadReq accesses(hits+misses)
793 system.l2c.ReadReq_accesses::cpu0.data 251688 # number of ReadReq accesses(hits+misses)
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1020 system.l2c.overall_mshr_miss_rate::cpu1.data 0.229605 # mshr miss rate for overall accesses
1021 system.l2c.overall_mshr_miss_rate::total 0.108628 # mshr miss rate for overall accesses
1022 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average ReadReq mshr miss latency
1023 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
1024 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average ReadReq mshr miss latency
1025 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62750.797509 # average ReadReq mshr miss latency
1026 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
1027 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average ReadReq mshr miss latency
1028 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66057.804233 # average ReadReq mshr miss latency
1029 system.l2c.ReadReq_avg_mshr_miss_latency::total 61604.186027 # average ReadReq mshr miss latency
1030 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.547900 # average UpgradeReq mshr miss latency
1031 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.172281 # average UpgradeReq mshr miss latency
1032 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.948784 # average UpgradeReq mshr miss latency
1033 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.574742 # average SCUpgradeReq mshr miss latency
1034 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.874739 # average SCUpgradeReq mshr miss latency
1035 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.685121 # average SCUpgradeReq mshr miss latency
1036 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56045.714220 # average ReadExReq mshr miss latency
1037 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64546.202494 # average ReadExReq mshr miss latency
1038 system.l2c.ReadExReq_avg_mshr_miss_latency::total 58758.594590 # average ReadExReq mshr miss latency
1039 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency
1040 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
1041 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency
1042 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency
1043 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
1044 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency
1045 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency
1046 system.l2c.demand_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency
1047 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency
1048 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
1049 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency
1050 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency
1051 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
1052 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency
1053 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency
1054 system.l2c.overall_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency
1055 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1056 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1057 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1058 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1059 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1060 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1061 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1062 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1063 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1064 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1065 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1066 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1067 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1068 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1069 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1070 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1071 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1072 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
1073 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
1074 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
1075 system.toL2Bus.throughput 118330469 # Throughput (bytes/s)
1076 system.toL2Bus.trans_dist::ReadReq 2505274 # Transaction distribution
1077 system.toL2Bus.trans_dist::ReadResp 2505274 # Transaction distribution
1078 system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution
1079 system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution
1080 system.toL2Bus.trans_dist::Writeback 576138 # Transaction distribution
1081 system.toL2Bus.trans_dist::UpgradeReq 27005 # Transaction distribution
1082 system.toL2Bus.trans_dist::SCUpgradeReq 16807 # Transaction distribution
1083 system.toL2Bus.trans_dist::UpgradeResp 43812 # Transaction distribution
1084 system.toL2Bus.trans_dist::ReadExReq 262415 # Transaction distribution
1085 system.toL2Bus.trans_dist::ReadExResp 262415 # Transaction distribution
1086 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993978 # Packet count per connected master and slave (bytes)
1087 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951141 # Packet count per connected master and slave (bytes)
1088 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5841 # Packet count per connected master and slave (bytes)
1089 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14926 # Packet count per connected master and slave (bytes)
1090 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753985 # Packet count per connected master and slave (bytes)
1091 system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879812 # Packet count per connected master and slave (bytes)
1092 system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6193 # Packet count per connected master and slave (bytes)
1093 system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 12022 # Packet count per connected master and slave (bytes)
1094 system.toL2Bus.pkt_count::total 7617898 # Packet count per connected master and slave (bytes)
1095 system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31385016 # Cumulative packet size per connected master and slave (bytes)
1096 system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53721240 # Cumulative packet size per connected master and slave (bytes)
1097 system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5780 # Cumulative packet size per connected master and slave (bytes)
1098 system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18120 # Cumulative packet size per connected master and slave (bytes)
1099 system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24096780 # Cumulative packet size per connected master and slave (bytes)
1100 system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27936146 # Cumulative packet size per connected master and slave (bytes)
1101 system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7468 # Cumulative packet size per connected master and slave (bytes)
1102 system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15168 # Cumulative packet size per connected master and slave (bytes)
1103 system.toL2Bus.tot_pkt_size::total 137185718 # Cumulative packet size per connected master and slave (bytes)
1104 system.toL2Bus.data_through_bus 137185718 # Total data (bytes)
1105 system.toL2Bus.snoop_data_through_bus 4312904 # Total snoop data (bytes)
1106 system.toL2Bus.reqLayer0.occupancy 4765712727 # Layer occupancy (ticks)
1107 system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
1108 system.toL2Bus.respLayer0.occupancy 2217854478 # Layer occupancy (ticks)
1109 system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1110 system.toL2Bus.respLayer1.occupancy 2469983321 # Layer occupancy (ticks)
1111 system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
1112 system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks)
1113 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1114 system.toL2Bus.respLayer3.occupancy 10396000 # Layer occupancy (ticks)
1115 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1116 system.toL2Bus.respLayer4.occupancy 1698669462 # Layer occupancy (ticks)
1117 system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
1118 system.toL2Bus.respLayer5.occupancy 2208533441 # Layer occupancy (ticks)
1119 system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
1120 system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks)
1121 system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
1122 system.toL2Bus.respLayer7.occupancy 8230499 # Layer occupancy (ticks)
1123 system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
1124 system.iobus.throughput 45404559 # Throughput (bytes/s)
1125 system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution
1126 system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution
1127 system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
1128 system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
1129 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
1130 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes)
1131 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1132 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes)
1133 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
1134 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1135 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
1136 system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
1137 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
1138 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1139 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1140 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1141 system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
1142 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
1143 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1144 system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
1145 system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
1146 system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
1147 system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
1148 system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
1149 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1150 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1151 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1152 system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes)
1153 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
1154 system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
1155 system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes)
1156 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
1157 system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes)
1158 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1159 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes)
1160 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
1161 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1162 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
1163 system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
1164 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1165 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1166 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1167 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1168 system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1169 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
1170 system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1171 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1172 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1173 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1174 system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1175 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1176 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1177 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1178 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1179 system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes)
1180 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
1181 system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
1182 system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes)
1183 system.iobus.data_through_bus 54294406 # Total data (bytes)
1184 system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
1185 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1186 system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks)
1187 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1188 system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
1189 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1190 system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks)
1191 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1192 system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
1193 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1194 system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
1195 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1196 system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
1197 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1198 system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
1199 system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
1200 system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
1201 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1202 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1203 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1204 system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
1205 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1206 system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
1207 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1208 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1209 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1210 system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1211 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1212 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1213 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1214 system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
1215 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1216 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1217 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1218 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
1219 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1220 system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
1221 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1222 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
1223 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1224 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
1225 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1226 system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
1227 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1228 system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
1229 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1230 system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
1231 system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
1232 system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks)
1233 system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
1234 system.iobus.respLayer1.occupancy 17777853001 # Layer occupancy (ticks)
1235 system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
1236 system.cpu0.dtb.inst_hits 0 # ITB inst hits
1237 system.cpu0.dtb.inst_misses 0 # ITB inst misses
1238 system.cpu0.dtb.read_hits 9652640 # DTB read hits
1239 system.cpu0.dtb.read_misses 3742 # DTB read misses
1240 system.cpu0.dtb.write_hits 7596858 # DTB write hits
1241 system.cpu0.dtb.write_misses 1582 # DTB write misses
1242 system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1243 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1244 system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1245 system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1246 system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB
1247 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1248 system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
1249 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1250 system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
1251 system.cpu0.dtb.read_accesses 9656382 # DTB read accesses
1252 system.cpu0.dtb.write_accesses 7598440 # DTB write accesses
1253 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1254 system.cpu0.dtb.hits 17249498 # DTB hits
1255 system.cpu0.dtb.misses 5324 # DTB misses
1256 system.cpu0.dtb.accesses 17254822 # DTB accesses
1257 system.cpu0.itb.inst_hits 43298691 # ITB inst hits
1258 system.cpu0.itb.inst_misses 2205 # ITB inst misses
1259 system.cpu0.itb.read_hits 0 # DTB read hits
1260 system.cpu0.itb.read_misses 0 # DTB read misses
1261 system.cpu0.itb.write_hits 0 # DTB write hits
1262 system.cpu0.itb.write_misses 0 # DTB write misses
1263 system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
1264 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1265 system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1266 system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1267 system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
1268 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1269 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1270 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1271 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1272 system.cpu0.itb.read_accesses 0 # DTB read accesses
1273 system.cpu0.itb.write_accesses 0 # DTB write accesses
1274 system.cpu0.itb.inst_accesses 43300896 # ITB inst accesses
1275 system.cpu0.itb.hits 43298691 # DTB hits
1276 system.cpu0.itb.misses 2205 # DTB misses
1277 system.cpu0.itb.accesses 43300896 # DTB accesses
1278 system.cpu0.numCycles 2391583901 # number of cpu cycles simulated
1279 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1280 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1281 system.cpu0.committedInsts 42571767 # Number of instructions committed
1282 system.cpu0.committedOps 53302041 # Number of ops (including micro ops) committed
1283 system.cpu0.num_int_alu_accesses 48059042 # Number of integer alu accesses
1284 system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
1285 system.cpu0.num_func_calls 1403630 # number of times a function call or return occured
1286 system.cpu0.num_conditional_control_insts 5582817 # number of instructions that are conditional controls
1287 system.cpu0.num_int_insts 48059042 # number of integer instructions
1288 system.cpu0.num_fp_insts 3860 # number of float instructions
1289 system.cpu0.num_int_register_reads 272441604 # number of times the integer registers were read
1290 system.cpu0.num_int_register_writes 52270515 # number of times the integer registers were written
1291 system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
1292 system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
1293 system.cpu0.num_mem_refs 18019009 # number of memory refs
1294 system.cpu0.num_load_insts 10036503 # Number of load instructions
1295 system.cpu0.num_store_insts 7982506 # Number of store instructions
1296 system.cpu0.num_idle_cycles 2151142905.888201 # Number of idle cycles
1297 system.cpu0.num_busy_cycles 240440995.111799 # Number of busy cycles
1298 system.cpu0.not_idle_fraction 0.100536 # Percentage of non-idle cycles
1299 system.cpu0.idle_fraction 0.899464 # Percentage of idle cycles
1300 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1301 system.cpu0.kern.inst.quiesce 51319 # number of quiesce instructions executed
1302 system.cpu0.icache.tags.replacements 490213 # number of replacements
1303 system.cpu0.icache.tags.tagsinuse 509.358566 # Cycle average of tags in use
1304 system.cpu0.icache.tags.total_refs 42807948 # Total number of references to valid blocks.
1305 system.cpu0.icache.tags.sampled_refs 490725 # Sample count of references to valid blocks.
1306 system.cpu0.icache.tags.avg_refs 87.234088 # Average number of references to valid blocks.
1307 system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit.
1308 system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.358566 # Average occupied blocks per requestor
1309 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994841 # Average percentage of cache occupancy
1310 system.cpu0.icache.tags.occ_percent::total 0.994841 # Average percentage of cache occupancy
1311 system.cpu0.icache.ReadReq_hits::cpu0.inst 42807948 # number of ReadReq hits
1312 system.cpu0.icache.ReadReq_hits::total 42807948 # number of ReadReq hits
1313 system.cpu0.icache.demand_hits::cpu0.inst 42807948 # number of demand (read+write) hits
1314 system.cpu0.icache.demand_hits::total 42807948 # number of demand (read+write) hits
1315 system.cpu0.icache.overall_hits::cpu0.inst 42807948 # number of overall hits
1316 system.cpu0.icache.overall_hits::total 42807948 # number of overall hits
1317 system.cpu0.icache.ReadReq_misses::cpu0.inst 490726 # number of ReadReq misses
1318 system.cpu0.icache.ReadReq_misses::total 490726 # number of ReadReq misses
1319 system.cpu0.icache.demand_misses::cpu0.inst 490726 # number of demand (read+write) misses
1320 system.cpu0.icache.demand_misses::total 490726 # number of demand (read+write) misses
1321 system.cpu0.icache.overall_misses::cpu0.inst 490726 # number of overall misses
1322 system.cpu0.icache.overall_misses::total 490726 # number of overall misses
1323 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6824885728 # number of ReadReq miss cycles
1324 system.cpu0.icache.ReadReq_miss_latency::total 6824885728 # number of ReadReq miss cycles
1325 system.cpu0.icache.demand_miss_latency::cpu0.inst 6824885728 # number of demand (read+write) miss cycles
1326 system.cpu0.icache.demand_miss_latency::total 6824885728 # number of demand (read+write) miss cycles
1327 system.cpu0.icache.overall_miss_latency::cpu0.inst 6824885728 # number of overall miss cycles
1328 system.cpu0.icache.overall_miss_latency::total 6824885728 # number of overall miss cycles
1329 system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298674 # number of ReadReq accesses(hits+misses)
1330 system.cpu0.icache.ReadReq_accesses::total 43298674 # number of ReadReq accesses(hits+misses)
1331 system.cpu0.icache.demand_accesses::cpu0.inst 43298674 # number of demand (read+write) accesses
1332 system.cpu0.icache.demand_accesses::total 43298674 # number of demand (read+write) accesses
1333 system.cpu0.icache.overall_accesses::cpu0.inst 43298674 # number of overall (read+write) accesses
1334 system.cpu0.icache.overall_accesses::total 43298674 # number of overall (read+write) accesses
1335 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011334 # miss rate for ReadReq accesses
1336 system.cpu0.icache.ReadReq_miss_rate::total 0.011334 # miss rate for ReadReq accesses
1337 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011334 # miss rate for demand accesses
1338 system.cpu0.icache.demand_miss_rate::total 0.011334 # miss rate for demand accesses
1339 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011334 # miss rate for overall accesses
1340 system.cpu0.icache.overall_miss_rate::total 0.011334 # miss rate for overall accesses
1341 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13907.732070 # average ReadReq miss latency
1342 system.cpu0.icache.ReadReq_avg_miss_latency::total 13907.732070 # average ReadReq miss latency
1343 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13907.732070 # average overall miss latency
1344 system.cpu0.icache.demand_avg_miss_latency::total 13907.732070 # average overall miss latency
1345 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13907.732070 # average overall miss latency
1346 system.cpu0.icache.overall_avg_miss_latency::total 13907.732070 # average overall miss latency
1347 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1348 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1349 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1350 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1351 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1352 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1353 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1354 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1355 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490726 # number of ReadReq MSHR misses
1356 system.cpu0.icache.ReadReq_mshr_misses::total 490726 # number of ReadReq MSHR misses
1357 system.cpu0.icache.demand_mshr_misses::cpu0.inst 490726 # number of demand (read+write) MSHR misses
1358 system.cpu0.icache.demand_mshr_misses::total 490726 # number of demand (read+write) MSHR misses
1359 system.cpu0.icache.overall_mshr_misses::cpu0.inst 490726 # number of overall MSHR misses
1360 system.cpu0.icache.overall_mshr_misses::total 490726 # number of overall MSHR misses
1361 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5840816272 # number of ReadReq MSHR miss cycles
1362 system.cpu0.icache.ReadReq_mshr_miss_latency::total 5840816272 # number of ReadReq MSHR miss cycles
1363 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5840816272 # number of demand (read+write) MSHR miss cycles
1364 system.cpu0.icache.demand_mshr_miss_latency::total 5840816272 # number of demand (read+write) MSHR miss cycles
1365 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5840816272 # number of overall MSHR miss cycles
1366 system.cpu0.icache.overall_mshr_miss_latency::total 5840816272 # number of overall MSHR miss cycles
1367 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393750 # number of ReadReq MSHR uncacheable cycles
1368 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles
1369 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393750 # number of overall MSHR uncacheable cycles
1370 system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles
1371 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011334 # mshr miss rate for ReadReq accesses
1372 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011334 # mshr miss rate for ReadReq accesses
1373 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011334 # mshr miss rate for demand accesses
1374 system.cpu0.icache.demand_mshr_miss_rate::total 0.011334 # mshr miss rate for demand accesses
1375 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011334 # mshr miss rate for overall accesses
1376 system.cpu0.icache.overall_mshr_miss_rate::total 0.011334 # mshr miss rate for overall accesses
1377 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average ReadReq mshr miss latency
1378 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11902.398226 # average ReadReq mshr miss latency
1379 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency
1380 system.cpu0.icache.demand_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency
1381 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency
1382 system.cpu0.icache.overall_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency
1383 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1384 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1385 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1386 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1387 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1388 system.cpu0.dcache.tags.replacements 406717 # number of replacements
1389 system.cpu0.dcache.tags.tagsinuse 471.656866 # Cycle average of tags in use
1390 system.cpu0.dcache.tags.total_refs 15966646 # Total number of references to valid blocks.
1391 system.cpu0.dcache.tags.sampled_refs 407229 # Sample count of references to valid blocks.
1392 system.cpu0.dcache.tags.avg_refs 39.208028 # Average number of references to valid blocks.
1393 system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit.
1394 system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.656866 # Average occupied blocks per requestor
1395 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921205 # Average percentage of cache occupancy
1396 system.cpu0.dcache.tags.occ_percent::total 0.921205 # Average percentage of cache occupancy
1397 system.cpu0.dcache.ReadReq_hits::cpu0.data 9136610 # number of ReadReq hits
1398 system.cpu0.dcache.ReadReq_hits::total 9136610 # number of ReadReq hits
1399 system.cpu0.dcache.WriteReq_hits::cpu0.data 6494353 # number of WriteReq hits
1400 system.cpu0.dcache.WriteReq_hits::total 6494353 # number of WriteReq hits
1401 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156522 # number of LoadLockedReq hits
1402 system.cpu0.dcache.LoadLockedReq_hits::total 156522 # number of LoadLockedReq hits
1403 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158977 # number of StoreCondReq hits
1404 system.cpu0.dcache.StoreCondReq_hits::total 158977 # number of StoreCondReq hits
1405 system.cpu0.dcache.demand_hits::cpu0.data 15630963 # number of demand (read+write) hits
1406 system.cpu0.dcache.demand_hits::total 15630963 # number of demand (read+write) hits
1407 system.cpu0.dcache.overall_hits::cpu0.data 15630963 # number of overall hits
1408 system.cpu0.dcache.overall_hits::total 15630963 # number of overall hits
1409 system.cpu0.dcache.ReadReq_misses::cpu0.data 263803 # number of ReadReq misses
1410 system.cpu0.dcache.ReadReq_misses::total 263803 # number of ReadReq misses
1411 system.cpu0.dcache.WriteReq_misses::cpu0.data 176623 # number of WriteReq misses
1412 system.cpu0.dcache.WriteReq_misses::total 176623 # number of WriteReq misses
1413 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9911 # number of LoadLockedReq misses
1414 system.cpu0.dcache.LoadLockedReq_misses::total 9911 # number of LoadLockedReq misses
1415 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7399 # number of StoreCondReq misses
1416 system.cpu0.dcache.StoreCondReq_misses::total 7399 # number of StoreCondReq misses
1417 system.cpu0.dcache.demand_misses::cpu0.data 440426 # number of demand (read+write) misses
1418 system.cpu0.dcache.demand_misses::total 440426 # number of demand (read+write) misses
1419 system.cpu0.dcache.overall_misses::cpu0.data 440426 # number of overall misses
1420 system.cpu0.dcache.overall_misses::total 440426 # number of overall misses
1421 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3917573248 # number of ReadReq miss cycles
1422 system.cpu0.dcache.ReadReq_miss_latency::total 3917573248 # number of ReadReq miss cycles
1423 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7906184046 # number of WriteReq miss cycles
1424 system.cpu0.dcache.WriteReq_miss_latency::total 7906184046 # number of WriteReq miss cycles
1425 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99581999 # number of LoadLockedReq miss cycles
1426 system.cpu0.dcache.LoadLockedReq_miss_latency::total 99581999 # number of LoadLockedReq miss cycles
1427 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40689888 # number of StoreCondReq miss cycles
1428 system.cpu0.dcache.StoreCondReq_miss_latency::total 40689888 # number of StoreCondReq miss cycles
1429 system.cpu0.dcache.demand_miss_latency::cpu0.data 11823757294 # number of demand (read+write) miss cycles
1430 system.cpu0.dcache.demand_miss_latency::total 11823757294 # number of demand (read+write) miss cycles
1431 system.cpu0.dcache.overall_miss_latency::cpu0.data 11823757294 # number of overall miss cycles
1432 system.cpu0.dcache.overall_miss_latency::total 11823757294 # number of overall miss cycles
1433 system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400413 # number of ReadReq accesses(hits+misses)
1434 system.cpu0.dcache.ReadReq_accesses::total 9400413 # number of ReadReq accesses(hits+misses)
1435 system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670976 # number of WriteReq accesses(hits+misses)
1436 system.cpu0.dcache.WriteReq_accesses::total 6670976 # number of WriteReq accesses(hits+misses)
1437 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166433 # number of LoadLockedReq accesses(hits+misses)
1438 system.cpu0.dcache.LoadLockedReq_accesses::total 166433 # number of LoadLockedReq accesses(hits+misses)
1439 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166376 # number of StoreCondReq accesses(hits+misses)
1440 system.cpu0.dcache.StoreCondReq_accesses::total 166376 # number of StoreCondReq accesses(hits+misses)
1441 system.cpu0.dcache.demand_accesses::cpu0.data 16071389 # number of demand (read+write) accesses
1442 system.cpu0.dcache.demand_accesses::total 16071389 # number of demand (read+write) accesses
1443 system.cpu0.dcache.overall_accesses::cpu0.data 16071389 # number of overall (read+write) accesses
1444 system.cpu0.dcache.overall_accesses::total 16071389 # number of overall (read+write) accesses
1445 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028063 # miss rate for ReadReq accesses
1446 system.cpu0.dcache.ReadReq_miss_rate::total 0.028063 # miss rate for ReadReq accesses
1447 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026476 # miss rate for WriteReq accesses
1448 system.cpu0.dcache.WriteReq_miss_rate::total 0.026476 # miss rate for WriteReq accesses
1449 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059549 # miss rate for LoadLockedReq accesses
1450 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059549 # miss rate for LoadLockedReq accesses
1451 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044472 # miss rate for StoreCondReq accesses
1452 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044472 # miss rate for StoreCondReq accesses
1453 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027404 # miss rate for demand accesses
1454 system.cpu0.dcache.demand_miss_rate::total 0.027404 # miss rate for demand accesses
1455 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027404 # miss rate for overall accesses
1456 system.cpu0.dcache.overall_miss_rate::total 0.027404 # miss rate for overall accesses
1457 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14850.374135 # average ReadReq miss latency
1458 system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.374135 # average ReadReq miss latency
1459 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44763.049240 # average WriteReq miss latency
1460 system.cpu0.dcache.WriteReq_avg_miss_latency::total 44763.049240 # average WriteReq miss latency
1461 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10047.623751 # average LoadLockedReq miss latency
1462 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10047.623751 # average LoadLockedReq miss latency
1463 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5499.376673 # average StoreCondReq miss latency
1464 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5499.376673 # average StoreCondReq miss latency
1465 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency
1466 system.cpu0.dcache.demand_avg_miss_latency::total 26846.183681 # average overall miss latency
1467 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency
1468 system.cpu0.dcache.overall_avg_miss_latency::total 26846.183681 # average overall miss latency
1469 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1470 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1471 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1472 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1473 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1474 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1475 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1476 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1477 system.cpu0.dcache.writebacks::writebacks 376546 # number of writebacks
1478 system.cpu0.dcache.writebacks::total 376546 # number of writebacks
1479 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263803 # number of ReadReq MSHR misses
1480 system.cpu0.dcache.ReadReq_mshr_misses::total 263803 # number of ReadReq MSHR misses
1481 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176623 # number of WriteReq MSHR misses
1482 system.cpu0.dcache.WriteReq_mshr_misses::total 176623 # number of WriteReq MSHR misses
1483 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9911 # number of LoadLockedReq MSHR misses
1484 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9911 # number of LoadLockedReq MSHR misses
1485 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7395 # number of StoreCondReq MSHR misses
1486 system.cpu0.dcache.StoreCondReq_mshr_misses::total 7395 # number of StoreCondReq MSHR misses
1487 system.cpu0.dcache.demand_mshr_misses::cpu0.data 440426 # number of demand (read+write) MSHR misses
1488 system.cpu0.dcache.demand_mshr_misses::total 440426 # number of demand (read+write) MSHR misses
1489 system.cpu0.dcache.overall_mshr_misses::cpu0.data 440426 # number of overall MSHR misses
1490 system.cpu0.dcache.overall_mshr_misses::total 440426 # number of overall MSHR misses
1491 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3387671752 # number of ReadReq MSHR miss cycles
1492 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3387671752 # number of ReadReq MSHR miss cycles
1493 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7508595954 # number of WriteReq MSHR miss cycles
1494 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7508595954 # number of WriteReq MSHR miss cycles
1495 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79710001 # number of LoadLockedReq MSHR miss cycles
1496 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79710001 # number of LoadLockedReq MSHR miss cycles
1497 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25901112 # number of StoreCondReq MSHR miss cycles
1498 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25901112 # number of StoreCondReq MSHR miss cycles
1499 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
1500 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
1501 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10896267706 # number of demand (read+write) MSHR miss cycles
1502 system.cpu0.dcache.demand_mshr_miss_latency::total 10896267706 # number of demand (read+write) MSHR miss cycles
1503 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10896267706 # number of overall MSHR miss cycles
1504 system.cpu0.dcache.overall_mshr_miss_latency::total 10896267706 # number of overall MSHR miss cycles
1505 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765830000 # number of ReadReq MSHR uncacheable cycles
1506 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765830000 # number of ReadReq MSHR uncacheable cycles
1507 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807312360 # number of WriteReq MSHR uncacheable cycles
1508 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807312360 # number of WriteReq MSHR uncacheable cycles
1509 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39573142360 # number of overall MSHR uncacheable cycles
1510 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39573142360 # number of overall MSHR uncacheable cycles
1511 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028063 # mshr miss rate for ReadReq accesses
1512 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028063 # mshr miss rate for ReadReq accesses
1513 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026476 # mshr miss rate for WriteReq accesses
1514 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026476 # mshr miss rate for WriteReq accesses
1515 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059549 # mshr miss rate for LoadLockedReq accesses
1516 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059549 # mshr miss rate for LoadLockedReq accesses
1517 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044448 # mshr miss rate for StoreCondReq accesses
1518 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044448 # mshr miss rate for StoreCondReq accesses
1519 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for demand accesses
1520 system.cpu0.dcache.demand_mshr_miss_rate::total 0.027404 # mshr miss rate for demand accesses
1521 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses
1522 system.cpu0.dcache.overall_mshr_miss_rate::total 0.027404 # mshr miss rate for overall accesses
1523 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.672581 # average ReadReq mshr miss latency
1524 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.672581 # average ReadReq mshr miss latency
1525 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42511.994214 # average WriteReq mshr miss latency
1526 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42511.994214 # average WriteReq mshr miss latency
1527 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8042.579054 # average LoadLockedReq mshr miss latency
1528 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8042.579054 # average LoadLockedReq mshr miss latency
1529 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.516836 # average StoreCondReq mshr miss latency
1530 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.516836 # average StoreCondReq mshr miss latency
1531 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1532 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1533 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency
1534 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency
1535 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency
1536 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency
1537 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1538 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1539 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1540 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1541 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1542 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1543 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1544 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1545 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1546 system.cpu1.dtb.read_hits 5706417 # DTB read hits
1547 system.cpu1.dtb.read_misses 3586 # DTB read misses
1548 system.cpu1.dtb.write_hits 3873093 # DTB write hits
1549 system.cpu1.dtb.write_misses 644 # DTB write misses
1550 system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1551 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1552 system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1553 system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1554 system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
1555 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1556 system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch
1557 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1558 system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
1559 system.cpu1.dtb.read_accesses 5710003 # DTB read accesses
1560 system.cpu1.dtb.write_accesses 3873737 # DTB write accesses
1561 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1562 system.cpu1.dtb.hits 9579510 # DTB hits
1563 system.cpu1.dtb.misses 4230 # DTB misses
1564 system.cpu1.dtb.accesses 9583740 # DTB accesses
1565 system.cpu1.itb.inst_hits 19379017 # ITB inst hits
1566 system.cpu1.itb.inst_misses 2171 # ITB inst misses
1567 system.cpu1.itb.read_hits 0 # DTB read hits
1568 system.cpu1.itb.read_misses 0 # DTB read misses
1569 system.cpu1.itb.write_hits 0 # DTB write hits
1570 system.cpu1.itb.write_misses 0 # DTB write misses
1571 system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1572 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1573 system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1574 system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1575 system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
1576 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1577 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1578 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1579 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1580 system.cpu1.itb.read_accesses 0 # DTB read accesses
1581 system.cpu1.itb.write_accesses 0 # DTB write accesses
1582 system.cpu1.itb.inst_accesses 19381188 # ITB inst accesses
1583 system.cpu1.itb.hits 19379017 # DTB hits
1584 system.cpu1.itb.misses 2171 # DTB misses
1585 system.cpu1.itb.accesses 19381188 # DTB accesses
1586 system.cpu1.numCycles 2390136116 # number of cpu cycles simulated
1587 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1588 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1589 system.cpu1.committedInsts 18798461 # Number of instructions committed
1590 system.cpu1.committedOps 24902767 # Number of ops (including micro ops) committed
1591 system.cpu1.num_int_alu_accesses 22266699 # Number of integer alu accesses
1592 system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
1593 system.cpu1.num_func_calls 796691 # number of times a function call or return occured
1594 system.cpu1.num_conditional_control_insts 2514546 # number of instructions that are conditional controls
1595 system.cpu1.num_int_insts 22266699 # number of integer instructions
1596 system.cpu1.num_fp_insts 6793 # number of float instructions
1597 system.cpu1.num_int_register_reads 130767489 # number of times the integer registers were read
1598 system.cpu1.num_int_register_writes 23318960 # number of times the integer registers were written
1599 system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
1600 system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
1601 system.cpu1.num_mem_refs 10014870 # number of memory refs
1602 system.cpu1.num_load_insts 5983067 # Number of load instructions
1603 system.cpu1.num_store_insts 4031803 # Number of store instructions
1604 system.cpu1.num_idle_cycles 1969216562.004314 # Number of idle cycles
1605 system.cpu1.num_busy_cycles 420919553.995686 # Number of busy cycles
1606 system.cpu1.not_idle_fraction 0.176107 # Percentage of non-idle cycles
1607 system.cpu1.idle_fraction 0.823893 # Percentage of idle cycles
1608 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1609 system.cpu1.kern.inst.quiesce 39069 # number of quiesce instructions executed
1610 system.cpu1.icache.tags.replacements 376769 # number of replacements
1611 system.cpu1.icache.tags.tagsinuse 474.890792 # Cycle average of tags in use
1612 system.cpu1.icache.tags.total_refs 19001732 # Total number of references to valid blocks.
1613 system.cpu1.icache.tags.sampled_refs 377281 # Sample count of references to valid blocks.
1614 system.cpu1.icache.tags.avg_refs 50.364932 # Average number of references to valid blocks.
1615 system.cpu1.icache.tags.warmup_cycle 327211938000 # Cycle when the warmup percentage was hit.
1616 system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.890792 # Average occupied blocks per requestor
1617 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927521 # Average percentage of cache occupancy
1618 system.cpu1.icache.tags.occ_percent::total 0.927521 # Average percentage of cache occupancy
1619 system.cpu1.icache.ReadReq_hits::cpu1.inst 19001732 # number of ReadReq hits
1620 system.cpu1.icache.ReadReq_hits::total 19001732 # number of ReadReq hits
1621 system.cpu1.icache.demand_hits::cpu1.inst 19001732 # number of demand (read+write) hits
1622 system.cpu1.icache.demand_hits::total 19001732 # number of demand (read+write) hits
1623 system.cpu1.icache.overall_hits::cpu1.inst 19001732 # number of overall hits
1624 system.cpu1.icache.overall_hits::total 19001732 # number of overall hits
1625 system.cpu1.icache.ReadReq_misses::cpu1.inst 377281 # number of ReadReq misses
1626 system.cpu1.icache.ReadReq_misses::total 377281 # number of ReadReq misses
1627 system.cpu1.icache.demand_misses::cpu1.inst 377281 # number of demand (read+write) misses
1628 system.cpu1.icache.demand_misses::total 377281 # number of demand (read+write) misses
1629 system.cpu1.icache.overall_misses::cpu1.inst 377281 # number of overall misses
1630 system.cpu1.icache.overall_misses::total 377281 # number of overall misses
1631 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5163865212 # number of ReadReq miss cycles
1632 system.cpu1.icache.ReadReq_miss_latency::total 5163865212 # number of ReadReq miss cycles
1633 system.cpu1.icache.demand_miss_latency::cpu1.inst 5163865212 # number of demand (read+write) miss cycles
1634 system.cpu1.icache.demand_miss_latency::total 5163865212 # number of demand (read+write) miss cycles
1635 system.cpu1.icache.overall_miss_latency::cpu1.inst 5163865212 # number of overall miss cycles
1636 system.cpu1.icache.overall_miss_latency::total 5163865212 # number of overall miss cycles
1637 system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379013 # number of ReadReq accesses(hits+misses)
1638 system.cpu1.icache.ReadReq_accesses::total 19379013 # number of ReadReq accesses(hits+misses)
1639 system.cpu1.icache.demand_accesses::cpu1.inst 19379013 # number of demand (read+write) accesses
1640 system.cpu1.icache.demand_accesses::total 19379013 # number of demand (read+write) accesses
1641 system.cpu1.icache.overall_accesses::cpu1.inst 19379013 # number of overall (read+write) accesses
1642 system.cpu1.icache.overall_accesses::total 19379013 # number of overall (read+write) accesses
1643 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019469 # miss rate for ReadReq accesses
1644 system.cpu1.icache.ReadReq_miss_rate::total 0.019469 # miss rate for ReadReq accesses
1645 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019469 # miss rate for demand accesses
1646 system.cpu1.icache.demand_miss_rate::total 0.019469 # miss rate for demand accesses
1647 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019469 # miss rate for overall accesses
1648 system.cpu1.icache.overall_miss_rate::total 0.019469 # miss rate for overall accesses
1649 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13687.053448 # average ReadReq miss latency
1650 system.cpu1.icache.ReadReq_avg_miss_latency::total 13687.053448 # average ReadReq miss latency
1651 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency
1652 system.cpu1.icache.demand_avg_miss_latency::total 13687.053448 # average overall miss latency
1653 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency
1654 system.cpu1.icache.overall_avg_miss_latency::total 13687.053448 # average overall miss latency
1655 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1656 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1657 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1658 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1659 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1660 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1661 system.cpu1.icache.fast_writes 0 # number of fast writes performed
1662 system.cpu1.icache.cache_copies 0 # number of cache copies performed
1663 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377281 # number of ReadReq MSHR misses
1664 system.cpu1.icache.ReadReq_mshr_misses::total 377281 # number of ReadReq MSHR misses
1665 system.cpu1.icache.demand_mshr_misses::cpu1.inst 377281 # number of demand (read+write) MSHR misses
1666 system.cpu1.icache.demand_mshr_misses::total 377281 # number of demand (read+write) MSHR misses
1667 system.cpu1.icache.overall_mshr_misses::cpu1.inst 377281 # number of overall MSHR misses
1668 system.cpu1.icache.overall_mshr_misses::total 377281 # number of overall MSHR misses
1669 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4407732788 # number of ReadReq MSHR miss cycles
1670 system.cpu1.icache.ReadReq_mshr_miss_latency::total 4407732788 # number of ReadReq MSHR miss cycles
1671 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4407732788 # number of demand (read+write) MSHR miss cycles
1672 system.cpu1.icache.demand_mshr_miss_latency::total 4407732788 # number of demand (read+write) MSHR miss cycles
1673 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4407732788 # number of overall MSHR miss cycles
1674 system.cpu1.icache.overall_mshr_miss_latency::total 4407732788 # number of overall MSHR miss cycles
1675 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles
1676 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles
1677 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles
1678 system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles
1679 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for ReadReq accesses
1680 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019469 # mshr miss rate for ReadReq accesses
1681 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for demand accesses
1682 system.cpu1.icache.demand_mshr_miss_rate::total 0.019469 # mshr miss rate for demand accesses
1683 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for overall accesses
1684 system.cpu1.icache.overall_mshr_miss_rate::total 0.019469 # mshr miss rate for overall accesses
1685 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average ReadReq mshr miss latency
1686 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11682.890970 # average ReadReq mshr miss latency
1687 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency
1688 system.cpu1.icache.demand_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency
1689 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency
1690 system.cpu1.icache.overall_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency
1691 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1692 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1693 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1694 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1695 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1696 system.cpu1.dcache.tags.replacements 220436 # number of replacements
1697 system.cpu1.dcache.tags.tagsinuse 471.379597 # Cycle average of tags in use
1698 system.cpu1.dcache.tags.total_refs 8230755 # Total number of references to valid blocks.
1699 system.cpu1.dcache.tags.sampled_refs 220801 # Sample count of references to valid blocks.
1700 system.cpu1.dcache.tags.avg_refs 37.276801 # Average number of references to valid blocks.
1701 system.cpu1.dcache.tags.warmup_cycle 106418022500 # Cycle when the warmup percentage was hit.
1702 system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.379597 # Average occupied blocks per requestor
1703 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920663 # Average percentage of cache occupancy
1704 system.cpu1.dcache.tags.occ_percent::total 0.920663 # Average percentage of cache occupancy
1705 system.cpu1.dcache.ReadReq_hits::cpu1.data 4389351 # number of ReadReq hits
1706 system.cpu1.dcache.ReadReq_hits::total 4389351 # number of ReadReq hits
1707 system.cpu1.dcache.WriteReq_hits::cpu1.data 3673214 # number of WriteReq hits
1708 system.cpu1.dcache.WriteReq_hits::total 3673214 # number of WriteReq hits
1709 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73456 # number of LoadLockedReq hits
1710 system.cpu1.dcache.LoadLockedReq_hits::total 73456 # number of LoadLockedReq hits
1711 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73714 # number of StoreCondReq hits
1712 system.cpu1.dcache.StoreCondReq_hits::total 73714 # number of StoreCondReq hits
1713 system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits
1714 system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits
1715 system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits
1716 system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits
1717 system.cpu1.dcache.ReadReq_misses::cpu1.data 133803 # number of ReadReq misses
1718 system.cpu1.dcache.ReadReq_misses::total 133803 # number of ReadReq misses
1719 system.cpu1.dcache.WriteReq_misses::cpu1.data 112797 # number of WriteReq misses
1720 system.cpu1.dcache.WriteReq_misses::total 112797 # number of WriteReq misses
1721 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9752 # number of LoadLockedReq misses
1722 system.cpu1.dcache.LoadLockedReq_misses::total 9752 # number of LoadLockedReq misses
1723 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9418 # number of StoreCondReq misses
1724 system.cpu1.dcache.StoreCondReq_misses::total 9418 # number of StoreCondReq misses
1725 system.cpu1.dcache.demand_misses::cpu1.data 246600 # number of demand (read+write) misses
1726 system.cpu1.dcache.demand_misses::total 246600 # number of demand (read+write) misses
1727 system.cpu1.dcache.overall_misses::cpu1.data 246600 # number of overall misses
1728 system.cpu1.dcache.overall_misses::total 246600 # number of overall misses
1729 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1647983739 # number of ReadReq miss cycles
1730 system.cpu1.dcache.ReadReq_miss_latency::total 1647983739 # number of ReadReq miss cycles
1731 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4345457226 # number of WriteReq miss cycles
1732 system.cpu1.dcache.WriteReq_miss_latency::total 4345457226 # number of WriteReq miss cycles
1733 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77502998 # number of LoadLockedReq miss cycles
1734 system.cpu1.dcache.LoadLockedReq_miss_latency::total 77502998 # number of LoadLockedReq miss cycles
1735 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49351478 # number of StoreCondReq miss cycles
1736 system.cpu1.dcache.StoreCondReq_miss_latency::total 49351478 # number of StoreCondReq miss cycles
1737 system.cpu1.dcache.demand_miss_latency::cpu1.data 5993440965 # number of demand (read+write) miss cycles
1738 system.cpu1.dcache.demand_miss_latency::total 5993440965 # number of demand (read+write) miss cycles
1739 system.cpu1.dcache.overall_miss_latency::cpu1.data 5993440965 # number of overall miss cycles
1740 system.cpu1.dcache.overall_miss_latency::total 5993440965 # number of overall miss cycles
1741 system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523154 # number of ReadReq accesses(hits+misses)
1742 system.cpu1.dcache.ReadReq_accesses::total 4523154 # number of ReadReq accesses(hits+misses)
1743 system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786011 # number of WriteReq accesses(hits+misses)
1744 system.cpu1.dcache.WriteReq_accesses::total 3786011 # number of WriteReq accesses(hits+misses)
1745 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83208 # number of LoadLockedReq accesses(hits+misses)
1746 system.cpu1.dcache.LoadLockedReq_accesses::total 83208 # number of LoadLockedReq accesses(hits+misses)
1747 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83132 # number of StoreCondReq accesses(hits+misses)
1748 system.cpu1.dcache.StoreCondReq_accesses::total 83132 # number of StoreCondReq accesses(hits+misses)
1749 system.cpu1.dcache.demand_accesses::cpu1.data 8309165 # number of demand (read+write) accesses
1750 system.cpu1.dcache.demand_accesses::total 8309165 # number of demand (read+write) accesses
1751 system.cpu1.dcache.overall_accesses::cpu1.data 8309165 # number of overall (read+write) accesses
1752 system.cpu1.dcache.overall_accesses::total 8309165 # number of overall (read+write) accesses
1753 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029582 # miss rate for ReadReq accesses
1754 system.cpu1.dcache.ReadReq_miss_rate::total 0.029582 # miss rate for ReadReq accesses
1755 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029793 # miss rate for WriteReq accesses
1756 system.cpu1.dcache.WriteReq_miss_rate::total 0.029793 # miss rate for WriteReq accesses
1757 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117200 # miss rate for LoadLockedReq accesses
1758 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117200 # miss rate for LoadLockedReq accesses
1759 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113290 # miss rate for StoreCondReq accesses
1760 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113290 # miss rate for StoreCondReq accesses
1761 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029678 # miss rate for demand accesses
1762 system.cpu1.dcache.demand_miss_rate::total 0.029678 # miss rate for demand accesses
1763 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029678 # miss rate for overall accesses
1764 system.cpu1.dcache.overall_miss_rate::total 0.029678 # miss rate for overall accesses
1765 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12316.493195 # average ReadReq miss latency
1766 system.cpu1.dcache.ReadReq_avg_miss_latency::total 12316.493195 # average ReadReq miss latency
1767 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38524.581558 # average WriteReq miss latency
1768 system.cpu1.dcache.WriteReq_avg_miss_latency::total 38524.581558 # average WriteReq miss latency
1769 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7947.395201 # average LoadLockedReq miss latency
1770 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7947.395201 # average LoadLockedReq miss latency
1771 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5240.122956 # average StoreCondReq miss latency
1772 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5240.122956 # average StoreCondReq miss latency
1773 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency
1774 system.cpu1.dcache.demand_avg_miss_latency::total 24304.302372 # average overall miss latency
1775 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency
1776 system.cpu1.dcache.overall_avg_miss_latency::total 24304.302372 # average overall miss latency
1777 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1778 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1779 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1780 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1781 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1782 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1783 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1784 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1785 system.cpu1.dcache.writebacks::writebacks 199592 # number of writebacks
1786 system.cpu1.dcache.writebacks::total 199592 # number of writebacks
1787 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133803 # number of ReadReq MSHR misses
1788 system.cpu1.dcache.ReadReq_mshr_misses::total 133803 # number of ReadReq MSHR misses
1789 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112797 # number of WriteReq MSHR misses
1790 system.cpu1.dcache.WriteReq_mshr_misses::total 112797 # number of WriteReq MSHR misses
1791 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9752 # number of LoadLockedReq MSHR misses
1792 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9752 # number of LoadLockedReq MSHR misses
1793 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9415 # number of StoreCondReq MSHR misses
1794 system.cpu1.dcache.StoreCondReq_mshr_misses::total 9415 # number of StoreCondReq MSHR misses
1795 system.cpu1.dcache.demand_mshr_misses::cpu1.data 246600 # number of demand (read+write) MSHR misses
1796 system.cpu1.dcache.demand_mshr_misses::total 246600 # number of demand (read+write) MSHR misses
1797 system.cpu1.dcache.overall_mshr_misses::cpu1.data 246600 # number of overall MSHR misses
1798 system.cpu1.dcache.overall_mshr_misses::total 246600 # number of overall MSHR misses
1799 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1380025261 # number of ReadReq MSHR miss cycles
1800 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1380025261 # number of ReadReq MSHR miss cycles
1801 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4109897774 # number of WriteReq MSHR miss cycles
1802 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4109897774 # number of WriteReq MSHR miss cycles
1803 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 57992002 # number of LoadLockedReq MSHR miss cycles
1804 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 57992002 # number of LoadLockedReq MSHR miss cycles
1805 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30524522 # number of StoreCondReq MSHR miss cycles
1806 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30524522 # number of StoreCondReq MSHR miss cycles
1807 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles
1808 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
1809 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5489923035 # number of demand (read+write) MSHR miss cycles
1810 system.cpu1.dcache.demand_mshr_miss_latency::total 5489923035 # number of demand (read+write) MSHR miss cycles
1811 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5489923035 # number of overall MSHR miss cycles
1812 system.cpu1.dcache.overall_mshr_miss_latency::total 5489923035 # number of overall MSHR miss cycles
1813 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387761500 # number of ReadReq MSHR uncacheable cycles
1814 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387761500 # number of ReadReq MSHR uncacheable cycles
1815 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531061000 # number of WriteReq MSHR uncacheable cycles
1816 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531061000 # number of WriteReq MSHR uncacheable cycles
1817 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918822500 # number of overall MSHR uncacheable cycles
1818 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918822500 # number of overall MSHR uncacheable cycles
1819 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029582 # mshr miss rate for ReadReq accesses
1820 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029582 # mshr miss rate for ReadReq accesses
1821 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029793 # mshr miss rate for WriteReq accesses
1822 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029793 # mshr miss rate for WriteReq accesses
1823 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117200 # mshr miss rate for LoadLockedReq accesses
1824 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117200 # mshr miss rate for LoadLockedReq accesses
1825 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113254 # mshr miss rate for StoreCondReq accesses
1826 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113254 # mshr miss rate for StoreCondReq accesses
1827 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for demand accesses
1828 system.cpu1.dcache.demand_mshr_miss_rate::total 0.029678 # mshr miss rate for demand accesses
1829 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for overall accesses
1830 system.cpu1.dcache.overall_mshr_miss_rate::total 0.029678 # mshr miss rate for overall accesses
1831 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10313.858890 # average ReadReq mshr miss latency
1832 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10313.858890 # average ReadReq mshr miss latency
1833 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36436.233003 # average WriteReq mshr miss latency
1834 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36436.233003 # average WriteReq mshr miss latency
1835 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5946.677810 # average LoadLockedReq mshr miss latency
1836 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5946.677810 # average LoadLockedReq mshr miss latency
1837 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3242.115985 # average StoreCondReq mshr miss latency
1838 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3242.115985 # average StoreCondReq mshr miss latency
1839 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1840 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1841 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency
1842 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency
1843 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency
1844 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency
1845 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1846 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1847 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1848 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1849 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1850 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1851 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1852 system.iocache.tags.replacements 0 # number of replacements
1853 system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
1854 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1855 system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
1856 system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
1857 system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1858 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1859 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1860 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1861 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1862 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1863 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1864 system.iocache.fast_writes 0 # number of fast writes performed
1865 system.iocache.cache_copies 0 # number of cache copies performed
1866 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651879453001 # number of ReadReq MSHR uncacheable cycles
1867 system.iocache.ReadReq_mshr_uncacheable_latency::total 651879453001 # number of ReadReq MSHR uncacheable cycles
1868 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651879453001 # number of overall MSHR uncacheable cycles
1869 system.iocache.overall_mshr_uncacheable_latency::total 651879453001 # number of overall MSHR uncacheable cycles
1870 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1871 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1872 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1873 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1874 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1876 ---------- End Simulation Statistics ----------
projects / gem5.git / blob