8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
17 boot_release_addr=65528
19 clk_domain=system.clk_domain
21 early_kernel_symbols=false
22 enable_context_switch_stats_dump=false
25 gic_cpu_addr=520093952
26 have_generic_timer=false
27 have_large_asid_64=false
30 have_virtualization=false
31 highest_el_is_64=false
33 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
34 kernel_addr_check=true
35 load_addr_mask=268435455
37 machine_type=RealView_PBX
39 mem_ranges=0:134217727
40 memories=system.realview.nvmem system.physmem
46 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
49 work_begin_ckpt_count=0
50 work_begin_cpu_id_exit=-1
51 work_begin_exit_count=0
52 work_cpus_ckpt_count=0
56 system_port=system.membus.slave[0]
60 clk_domain=system.clk_domain
63 ranges=268435456:520093695 1073741824:1610612735
66 master=system.iobus.slave[0]
67 slave=system.membus.master[0]
75 image=system.cf0.image
80 child=system.cf0.image.child
86 [system.cf0.image.child]
89 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
98 voltage_domain=system.voltage_domain
102 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
105 clk_domain=system.cpu_clk_domain
107 do_checkpoint_insts=true
109 do_statistics_insts=true
110 dstage2_mmu=system.cpu0.dstage2_mmu
115 function_trace_start=0
116 interrupts=system.cpu0.interrupts
118 istage2_mmu=system.cpu0.istage2_mmu
120 max_insts_all_threads=0
121 max_insts_any_thread=0
122 max_loads_all_threads=0
123 max_loads_any_thread=0
127 simpoint_start_insts=
128 simulate_data_stalls=false
129 simulate_inst_stalls=false
133 tracer=system.cpu0.tracer
136 dcache_port=system.cpu0.dcache.cpu_side
137 icache_port=system.cpu0.icache.cpu_side
142 addr_ranges=0:18446744073709551615
144 clk_domain=system.cpu_clk_domain
151 prefetch_on_access=false
154 sequential_access=false
157 tags=system.cpu0.dcache.tags
161 cpu_side=system.cpu0.dcache_port
162 mem_side=system.toL2Bus.slave[1]
164 [system.cpu0.dcache.tags]
168 clk_domain=system.cpu_clk_domain
171 sequential_access=false
174 [system.cpu0.dstage2_mmu]
178 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
181 [system.cpu0.dstage2_mmu.stage2_tlb]
187 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
189 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
191 clk_domain=system.cpu_clk_domain
194 num_squash_per_cycle=2
196 port=system.toL2Bus.slave[5]
204 walker=system.cpu0.dtb.walker
206 [system.cpu0.dtb.walker]
208 clk_domain=system.cpu_clk_domain
211 num_squash_per_cycle=2
213 port=system.toL2Bus.slave[3]
218 addr_ranges=0:18446744073709551615
220 clk_domain=system.cpu_clk_domain
227 prefetch_on_access=false
230 sequential_access=false
233 tags=system.cpu0.icache.tags
237 cpu_side=system.cpu0.icache_port
238 mem_side=system.toL2Bus.slave[0]
240 [system.cpu0.icache.tags]
244 clk_domain=system.cpu_clk_domain
247 sequential_access=false
250 [system.cpu0.interrupts]
260 id_aa64dfr0_el1=1052678
264 id_aa64mmfr0_el1=15728642
283 [system.cpu0.istage2_mmu]
287 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
290 [system.cpu0.istage2_mmu.stage2_tlb]
296 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
298 [system.cpu0.istage2_mmu.stage2_tlb.walker]
300 clk_domain=system.cpu_clk_domain
303 num_squash_per_cycle=2
305 port=system.toL2Bus.slave[4]
313 walker=system.cpu0.itb.walker
315 [system.cpu0.itb.walker]
317 clk_domain=system.cpu_clk_domain
320 num_squash_per_cycle=2
322 port=system.toL2Bus.slave[2]
330 children=dstage2_mmu dtb isa istage2_mmu itb tracer
333 clk_domain=system.cpu_clk_domain
335 do_checkpoint_insts=true
337 do_statistics_insts=true
338 dstage2_mmu=system.cpu1.dstage2_mmu
343 function_trace_start=0
346 istage2_mmu=system.cpu1.istage2_mmu
348 max_insts_all_threads=0
349 max_insts_any_thread=0
350 max_loads_all_threads=0
351 max_loads_any_thread=0
355 simpoint_start_insts=
356 simulate_data_stalls=false
357 simulate_inst_stalls=false
361 tracer=system.cpu1.tracer
365 [system.cpu1.dstage2_mmu]
369 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
372 [system.cpu1.dstage2_mmu.stage2_tlb]
378 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
380 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
382 clk_domain=system.cpu_clk_domain
385 num_squash_per_cycle=2
394 walker=system.cpu1.dtb.walker
396 [system.cpu1.dtb.walker]
398 clk_domain=system.cpu_clk_domain
401 num_squash_per_cycle=2
410 id_aa64dfr0_el1=1052678
414 id_aa64mmfr0_el1=15728642
433 [system.cpu1.istage2_mmu]
437 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
440 [system.cpu1.istage2_mmu.stage2_tlb]
446 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
448 [system.cpu1.istage2_mmu.stage2_tlb.walker]
450 clk_domain=system.cpu_clk_domain
453 num_squash_per_cycle=2
462 walker=system.cpu1.itb.walker
464 [system.cpu1.itb.walker]
466 clk_domain=system.cpu_clk_domain
469 num_squash_per_cycle=2
476 [system.cpu_clk_domain]
482 voltage_domain=system.voltage_domain
484 [system.dvfs_handler]
489 sys_clk_domain=system.clk_domain
490 transition_latency=100000000
499 clk_domain=system.clk_domain
502 use_default_range=false
504 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
505 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
510 addr_ranges=0:134217727
512 clk_domain=system.clk_domain
519 prefetch_on_access=false
522 sequential_access=false
525 tags=system.iocache.tags
529 cpu_side=system.iobus.master[26]
530 mem_side=system.membus.slave[2]
532 [system.iocache.tags]
536 clk_domain=system.clk_domain
539 sequential_access=false
545 addr_ranges=0:18446744073709551615
547 clk_domain=system.cpu_clk_domain
554 prefetch_on_access=false
557 sequential_access=false
564 cpu_side=system.toL2Bus.master[0]
565 mem_side=system.membus.slave[1]
571 clk_domain=system.cpu_clk_domain
574 sequential_access=false
579 children=badaddr_responder
580 clk_domain=system.clk_domain
585 use_default_range=false
587 default=system.membus.badaddr_responder.pio
588 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
589 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
591 [system.membus.badaddr_responder]
593 clk_domain=system.clk_domain
601 ret_data32=4294967295
602 ret_data64=18446744073709551615
607 pio=system.membus.default
612 clk_domain=system.clk_domain
613 conf_table_reported=true
620 port=system.membus.master[6]
624 children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
626 intrctrl=system.intrctrl
628 pci_cfg_gen_offsets=false
632 [system.realview.a9scu]
634 clk_domain=system.clk_domain
639 pio=system.membus.master[4]
641 [system.realview.aaci_fake]
644 clk_domain=system.clk_domain
650 pio=system.iobus.master[21]
652 [system.realview.cf_ctrl]
692 MSICAPNextCapability=0
696 MSIXCAPNextCapability=0
706 PMCAPNextCapability=0
711 PXCAPDevCapabilities=0
718 PXCAPNextCapability=0
726 clk_domain=system.clk_domain
736 platform=system.realview
738 config=system.iobus.master[8]
739 dma=system.iobus.slave[2]
740 pio=system.iobus.master[7]
742 [system.realview.clcd]
745 clk_domain=system.clk_domain
748 gic=system.realview.gic
755 dma=system.iobus.slave[1]
756 pio=system.iobus.master[4]
758 [system.realview.dmac_fake]
761 clk_domain=system.clk_domain
767 pio=system.iobus.master[9]
769 [system.realview.energy_ctrl]
771 clk_domain=system.clk_domain
772 dvfs_handler=system.dvfs_handler
777 pio=system.iobus.master[25]
779 [system.realview.flash_fake]
781 clk_domain=system.clk_domain
789 ret_data32=4294967295
790 ret_data64=18446744073709551615
795 pio=system.iobus.master[24]
797 [system.realview.gic]
799 clk_domain=system.clk_domain
808 platform=system.realview
810 pio=system.membus.master[2]
812 [system.realview.gpio0_fake]
815 clk_domain=system.clk_domain
821 pio=system.iobus.master[16]
823 [system.realview.gpio1_fake]
826 clk_domain=system.clk_domain
832 pio=system.iobus.master[17]
834 [system.realview.gpio2_fake]
837 clk_domain=system.clk_domain
843 pio=system.iobus.master[18]
845 [system.realview.kmi0]
848 clk_domain=system.clk_domain
850 gic=system.realview.gic
858 pio=system.iobus.master[5]
860 [system.realview.kmi1]
863 clk_domain=system.clk_domain
865 gic=system.realview.gic
873 pio=system.iobus.master[6]
875 [system.realview.l2x0_fake]
877 clk_domain=system.clk_domain
885 ret_data32=4294967295
886 ret_data64=18446744073709551615
891 pio=system.membus.master[3]
893 [system.realview.local_cpu_timer]
895 clk_domain=system.clk_domain
897 gic=system.realview.gic
903 pio=system.membus.master[5]
905 [system.realview.mmc_fake]
908 clk_domain=system.clk_domain
914 pio=system.iobus.master[22]
916 [system.realview.nvmem]
919 clk_domain=system.clk_domain
920 conf_table_reported=false
926 range=2147483648:2214592511
927 port=system.membus.master[1]
929 [system.realview.realview_io]
931 clk_domain=system.clk_domain
939 pio=system.iobus.master[1]
941 [system.realview.rtc]
944 clk_domain=system.clk_domain
946 gic=system.realview.gic
952 time=Thu Jan 1 00:00:00 2009
953 pio=system.iobus.master[23]
955 [system.realview.sci_fake]
958 clk_domain=system.clk_domain
964 pio=system.iobus.master[20]
966 [system.realview.smc_fake]
969 clk_domain=system.clk_domain
975 pio=system.iobus.master[13]
977 [system.realview.sp810_fake]
980 clk_domain=system.clk_domain
986 pio=system.iobus.master[14]
988 [system.realview.ssp_fake]
991 clk_domain=system.clk_domain
997 pio=system.iobus.master[19]
999 [system.realview.timer0]
1002 clk_domain=system.clk_domain
1006 gic=system.realview.gic
1012 pio=system.iobus.master[2]
1014 [system.realview.timer1]
1017 clk_domain=system.clk_domain
1021 gic=system.realview.gic
1027 pio=system.iobus.master[3]
1029 [system.realview.uart]
1031 clk_domain=system.clk_domain
1034 gic=system.realview.gic
1039 platform=system.realview
1041 terminal=system.terminal
1042 pio=system.iobus.master[0]
1044 [system.realview.uart1_fake]
1047 clk_domain=system.clk_domain
1053 pio=system.iobus.master[10]
1055 [system.realview.uart2_fake]
1058 clk_domain=system.clk_domain
1064 pio=system.iobus.master[11]
1066 [system.realview.uart3_fake]
1069 clk_domain=system.clk_domain
1075 pio=system.iobus.master[12]
1077 [system.realview.watchdog_fake]
1080 clk_domain=system.clk_domain
1086 pio=system.iobus.master[15]
1091 intr_control=system.intrctrl
1098 clk_domain=system.cpu_clk_domain
1103 use_default_range=false
1105 master=system.l2c.cpu_side
1106 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
1115 [system.voltage_domain]