a17b68bb893cf27962a9eaa21e5014ff1ba403fa
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
17 boot_release_addr=65528
19 clk_domain=system.clk_domain
21 early_kernel_symbols=false
22 enable_context_switch_stats_dump=false
25 gic_cpu_addr=520093952
26 have_generic_timer=false
27 have_large_asid_64=false
30 have_virtualization=false
31 highest_el_is_64=false
33 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
34 kernel_addr_check=true
35 load_addr_mask=268435455
37 machine_type=RealView_PBX
39 mem_ranges=0:134217727
40 memories=system.physmem system.realview.nvmem
46 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
49 work_begin_ckpt_count=0
50 work_begin_cpu_id_exit=-1
51 work_begin_exit_count=0
52 work_cpus_ckpt_count=0
56 system_port=system.membus.slave[0]
60 clk_domain=system.clk_domain
63 ranges=268435456:520093695 1073741824:1610612735
66 master=system.iobus.slave[0]
67 slave=system.membus.master[0]
75 image=system.cf0.image
80 child=system.cf0.image.child
86 [system.cf0.image.child]
89 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
98 voltage_domain=system.voltage_domain
102 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
105 clk_domain=system.cpu_clk_domain
107 do_checkpoint_insts=true
109 do_statistics_insts=true
110 dstage2_mmu=system.cpu0.dstage2_mmu
115 function_trace_start=0
116 interrupts=system.cpu0.interrupts
118 istage2_mmu=system.cpu0.istage2_mmu
120 max_insts_all_threads=0
121 max_insts_any_thread=0
122 max_loads_all_threads=0
123 max_loads_any_thread=0
127 simpoint_interval=100000000
128 simpoint_profile=false
129 simpoint_profile_file=simpoint.bb.gz
130 simpoint_start_insts=
131 simulate_data_stalls=false
132 simulate_inst_stalls=false
136 tracer=system.cpu0.tracer
139 dcache_port=system.cpu0.dcache.cpu_side
140 icache_port=system.cpu0.icache.cpu_side
145 addr_ranges=0:18446744073709551615
147 clk_domain=system.cpu_clk_domain
154 prefetch_on_access=false
157 sequential_access=false
160 tags=system.cpu0.dcache.tags
164 cpu_side=system.cpu0.dcache_port
165 mem_side=system.toL2Bus.slave[1]
167 [system.cpu0.dcache.tags]
171 clk_domain=system.cpu_clk_domain
174 sequential_access=false
177 [system.cpu0.dstage2_mmu]
181 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
184 [system.cpu0.dstage2_mmu.stage2_tlb]
190 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
192 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
194 clk_domain=system.cpu_clk_domain
197 num_squash_per_cycle=2
199 port=system.toL2Bus.slave[5]
207 walker=system.cpu0.dtb.walker
209 [system.cpu0.dtb.walker]
211 clk_domain=system.cpu_clk_domain
214 num_squash_per_cycle=2
216 port=system.toL2Bus.slave[3]
221 addr_ranges=0:18446744073709551615
223 clk_domain=system.cpu_clk_domain
230 prefetch_on_access=false
233 sequential_access=false
236 tags=system.cpu0.icache.tags
240 cpu_side=system.cpu0.icache_port
241 mem_side=system.toL2Bus.slave[0]
243 [system.cpu0.icache.tags]
247 clk_domain=system.cpu_clk_domain
250 sequential_access=false
253 [system.cpu0.interrupts]
263 id_aa64dfr0_el1=1052678
267 id_aa64mmfr0_el1=15728642
286 [system.cpu0.istage2_mmu]
290 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
293 [system.cpu0.istage2_mmu.stage2_tlb]
299 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
301 [system.cpu0.istage2_mmu.stage2_tlb.walker]
303 clk_domain=system.cpu_clk_domain
306 num_squash_per_cycle=2
308 port=system.toL2Bus.slave[4]
316 walker=system.cpu0.itb.walker
318 [system.cpu0.itb.walker]
320 clk_domain=system.cpu_clk_domain
323 num_squash_per_cycle=2
325 port=system.toL2Bus.slave[2]
333 children=dstage2_mmu dtb isa istage2_mmu itb tracer
336 clk_domain=system.cpu_clk_domain
338 do_checkpoint_insts=true
340 do_statistics_insts=true
341 dstage2_mmu=system.cpu1.dstage2_mmu
346 function_trace_start=0
349 istage2_mmu=system.cpu1.istage2_mmu
351 max_insts_all_threads=0
352 max_insts_any_thread=0
353 max_loads_all_threads=0
354 max_loads_any_thread=0
358 simpoint_interval=100000000
359 simpoint_profile=false
360 simpoint_profile_file=simpoint.bb.gz
361 simpoint_start_insts=
362 simulate_data_stalls=false
363 simulate_inst_stalls=false
367 tracer=system.cpu1.tracer
371 [system.cpu1.dstage2_mmu]
375 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
378 [system.cpu1.dstage2_mmu.stage2_tlb]
384 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
386 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
388 clk_domain=system.cpu_clk_domain
391 num_squash_per_cycle=2
400 walker=system.cpu1.dtb.walker
402 [system.cpu1.dtb.walker]
404 clk_domain=system.cpu_clk_domain
407 num_squash_per_cycle=2
416 id_aa64dfr0_el1=1052678
420 id_aa64mmfr0_el1=15728642
439 [system.cpu1.istage2_mmu]
443 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
446 [system.cpu1.istage2_mmu.stage2_tlb]
452 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
454 [system.cpu1.istage2_mmu.stage2_tlb.walker]
456 clk_domain=system.cpu_clk_domain
459 num_squash_per_cycle=2
468 walker=system.cpu1.itb.walker
470 [system.cpu1.itb.walker]
472 clk_domain=system.cpu_clk_domain
475 num_squash_per_cycle=2
482 [system.cpu_clk_domain]
488 voltage_domain=system.voltage_domain
490 [system.dvfs_handler]
495 sys_clk_domain=system.clk_domain
496 transition_latency=100000000
505 clk_domain=system.clk_domain
508 use_default_range=false
510 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
511 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
516 addr_ranges=0:134217727
518 clk_domain=system.clk_domain
525 prefetch_on_access=false
528 sequential_access=false
531 tags=system.iocache.tags
535 cpu_side=system.iobus.master[25]
536 mem_side=system.membus.slave[2]
538 [system.iocache.tags]
542 clk_domain=system.clk_domain
545 sequential_access=false
551 addr_ranges=0:18446744073709551615
553 clk_domain=system.cpu_clk_domain
560 prefetch_on_access=false
563 sequential_access=false
570 cpu_side=system.toL2Bus.master[0]
571 mem_side=system.membus.slave[1]
577 clk_domain=system.cpu_clk_domain
580 sequential_access=false
585 children=badaddr_responder
586 clk_domain=system.clk_domain
590 use_default_range=false
592 default=system.membus.badaddr_responder.pio
593 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
594 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
596 [system.membus.badaddr_responder]
598 clk_domain=system.clk_domain
606 ret_data32=4294967295
607 ret_data64=18446744073709551615
612 pio=system.membus.default
617 clk_domain=system.clk_domain
618 conf_table_reported=true
625 port=system.membus.master[6]
629 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
631 intrctrl=system.intrctrl
632 max_mem_size=268435456
637 [system.realview.a9scu]
639 clk_domain=system.clk_domain
644 pio=system.membus.master[4]
646 [system.realview.aaci_fake]
649 clk_domain=system.clk_domain
655 pio=system.iobus.master[21]
657 [system.realview.cf_ctrl]
696 MSICAPNextCapability=0
700 MSIXCAPNextCapability=0
710 PMCAPNextCapability=0
715 PXCAPDevCapabilities=0
722 PXCAPNextCapability=0
730 clk_domain=system.clk_domain
740 platform=system.realview
742 config=system.iobus.master[8]
743 dma=system.iobus.slave[2]
744 pio=system.iobus.master[7]
746 [system.realview.clcd]
749 clk_domain=system.clk_domain
752 gic=system.realview.gic
759 dma=system.iobus.slave[1]
760 pio=system.iobus.master[4]
762 [system.realview.dmac_fake]
765 clk_domain=system.clk_domain
771 pio=system.iobus.master[9]
773 [system.realview.flash_fake]
775 clk_domain=system.clk_domain
783 ret_data32=4294967295
784 ret_data64=18446744073709551615
789 pio=system.iobus.master[24]
791 [system.realview.gic]
793 clk_domain=system.clk_domain
802 platform=system.realview
804 pio=system.membus.master[2]
806 [system.realview.gpio0_fake]
809 clk_domain=system.clk_domain
815 pio=system.iobus.master[16]
817 [system.realview.gpio1_fake]
820 clk_domain=system.clk_domain
826 pio=system.iobus.master[17]
828 [system.realview.gpio2_fake]
831 clk_domain=system.clk_domain
837 pio=system.iobus.master[18]
839 [system.realview.kmi0]
842 clk_domain=system.clk_domain
844 gic=system.realview.gic
852 pio=system.iobus.master[5]
854 [system.realview.kmi1]
857 clk_domain=system.clk_domain
859 gic=system.realview.gic
867 pio=system.iobus.master[6]
869 [system.realview.l2x0_fake]
871 clk_domain=system.clk_domain
879 ret_data32=4294967295
880 ret_data64=18446744073709551615
885 pio=system.membus.master[3]
887 [system.realview.local_cpu_timer]
889 clk_domain=system.clk_domain
891 gic=system.realview.gic
897 pio=system.membus.master[5]
899 [system.realview.mmc_fake]
902 clk_domain=system.clk_domain
908 pio=system.iobus.master[22]
910 [system.realview.nvmem]
913 clk_domain=system.clk_domain
914 conf_table_reported=false
920 range=2147483648:2214592511
921 port=system.membus.master[1]
923 [system.realview.realview_io]
925 clk_domain=system.clk_domain
933 pio=system.iobus.master[1]
935 [system.realview.rtc]
938 clk_domain=system.clk_domain
940 gic=system.realview.gic
946 time=Thu Jan 1 00:00:00 2009
947 pio=system.iobus.master[23]
949 [system.realview.sci_fake]
952 clk_domain=system.clk_domain
958 pio=system.iobus.master[20]
960 [system.realview.smc_fake]
963 clk_domain=system.clk_domain
969 pio=system.iobus.master[13]
971 [system.realview.sp810_fake]
974 clk_domain=system.clk_domain
980 pio=system.iobus.master[14]
982 [system.realview.ssp_fake]
985 clk_domain=system.clk_domain
991 pio=system.iobus.master[19]
993 [system.realview.timer0]
996 clk_domain=system.clk_domain
1000 gic=system.realview.gic
1006 pio=system.iobus.master[2]
1008 [system.realview.timer1]
1011 clk_domain=system.clk_domain
1015 gic=system.realview.gic
1021 pio=system.iobus.master[3]
1023 [system.realview.uart]
1025 clk_domain=system.clk_domain
1028 gic=system.realview.gic
1033 platform=system.realview
1035 terminal=system.terminal
1036 pio=system.iobus.master[0]
1038 [system.realview.uart1_fake]
1041 clk_domain=system.clk_domain
1047 pio=system.iobus.master[10]
1049 [system.realview.uart2_fake]
1052 clk_domain=system.clk_domain
1058 pio=system.iobus.master[11]
1060 [system.realview.uart3_fake]
1063 clk_domain=system.clk_domain
1069 pio=system.iobus.master[12]
1071 [system.realview.watchdog_fake]
1074 clk_domain=system.clk_domain
1080 pio=system.iobus.master[15]
1085 intr_control=system.intrctrl
1092 clk_domain=system.cpu_clk_domain
1096 use_default_range=false
1098 master=system.l2c.cpu_side
1099 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
1108 [system.voltage_domain]