2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.332810 # Number of seconds simulated
4 sim_ticks 2332810264000 # Number of ticks simulated
5 final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1307768 # Simulator instruction rate (inst/s)
8 host_op_rate 1681709 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 50502250863 # Simulator tick rate (ticks/s)
10 host_mem_usage 395644 # Number of bytes of host memory used
11 host_seconds 46.19 # Real time elapsed on the host
12 sim_insts 60408639 # Number of instructions simulated
13 sim_ops 77681819 # Number of ops (including micro ops) simulated
14 system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
15 system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
16 system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
17 system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
18 system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
19 system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
20 system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
21 system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
22 system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
23 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
24 system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
25 system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
26 system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
27 system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
28 system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
29 system.physmem.bytes_read::cpu0.inst 492704 # Number of bytes read from this memory
30 system.physmem.bytes_read::cpu0.data 6494800 # Number of bytes read from this memory
31 system.physmem.bytes_read::cpu1.inst 212416 # Number of bytes read from this memory
32 system.physmem.bytes_read::cpu1.data 2577132 # Number of bytes read from this memory
33 system.physmem.bytes_read::total 121450716 # Number of bytes read from this memory
34 system.physmem.bytes_inst_read::cpu0.inst 492704 # Number of instructions bytes read from this memory
35 system.physmem.bytes_inst_read::cpu1.inst 212416 # Number of instructions bytes read from this memory
36 system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
37 system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory
38 system.physmem.bytes_written::cpu0.data 1405784 # Number of bytes written to this memory
39 system.physmem.bytes_written::cpu1.data 1610060 # Number of bytes written to this memory
40 system.physmem.bytes_written::total 6718884 # Number of bytes written to this memory
41 system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu0.inst 13901 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu0.data 101515 # Number of read requests responded to by this memory
46 system.physmem.num_reads::cpu1.inst 3319 # Number of read requests responded to by this memory
47 system.physmem.num_reads::cpu1.data 40278 # Number of read requests responded to by this memory
48 system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory
49 system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory
50 system.physmem.num_writes::cpu0.data 351446 # Number of write requests responded to by this memory
51 system.physmem.num_writes::cpu1.data 402515 # Number of write requests responded to by this memory
52 system.physmem.num_writes::total 811821 # Number of write requests responded to by this memory
53 system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.inst 211206 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu0.data 2784110 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.inst 91056 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.data 1104733 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::total 52061978 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_inst_read::cpu0.inst 211206 # Instruction read bandwidth from this memory (bytes/s)
62 system.physmem.bw_inst_read::cpu1.inst 91056 # Instruction read bandwidth from this memory (bytes/s)
63 system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
64 system.physmem.bw_write::writebacks 1587373 # Write bandwidth from this memory (bytes/s)
65 system.physmem.bw_write::cpu0.data 602614 # Write bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::cpu1.data 690180 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::total 2880167 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_total::writebacks 1587373 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.inst 211206 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.data 3386724 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.readReqs 0 # Total number of read requests seen
78 system.physmem.writeReqs 0 # Total number of write requests seen
79 system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
80 system.physmem.bytesRead 0 # Total number of bytes read from memory
81 system.physmem.bytesWritten 0 # Total number of bytes written to memory
82 system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
83 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
84 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
85 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
86 system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
87 system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
88 system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
89 system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
90 system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
91 system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
92 system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
93 system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
94 system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
95 system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
96 system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
97 system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
98 system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
99 system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
100 system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
101 system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
102 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
103 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
104 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
105 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
106 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
107 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
108 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
109 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
110 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
111 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
112 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
113 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
114 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
115 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
116 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
117 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
118 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
119 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
120 system.physmem.totGap 0 # Total gap between requests
121 system.physmem.readPktSize::0 0 # Categorize read packet sizes
122 system.physmem.readPktSize::1 0 # Categorize read packet sizes
123 system.physmem.readPktSize::2 0 # Categorize read packet sizes
124 system.physmem.readPktSize::3 0 # Categorize read packet sizes
125 system.physmem.readPktSize::4 0 # Categorize read packet sizes
126 system.physmem.readPktSize::5 0 # Categorize read packet sizes
127 system.physmem.readPktSize::6 0 # Categorize read packet sizes
128 system.physmem.writePktSize::0 0 # Categorize write packet sizes
129 system.physmem.writePktSize::1 0 # Categorize write packet sizes
130 system.physmem.writePktSize::2 0 # Categorize write packet sizes
131 system.physmem.writePktSize::3 0 # Categorize write packet sizes
132 system.physmem.writePktSize::4 0 # Categorize write packet sizes
133 system.physmem.writePktSize::5 0 # Categorize write packet sizes
134 system.physmem.writePktSize::6 0 # Categorize write packet sizes
135 system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
167 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
199 system.physmem.totQLat 0 # Total cycles spent in queuing delays
200 system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
201 system.physmem.totBusLat 0 # Total cycles spent in databus access
202 system.physmem.totBankLat 0 # Total cycles spent in bank access
203 system.physmem.avgQLat nan # Average queueing delay per request
204 system.physmem.avgBankLat nan # Average bank access latency per request
205 system.physmem.avgBusLat nan # Average bus latency per request
206 system.physmem.avgMemAccLat nan # Average memory access latency
207 system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
208 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
209 system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
210 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
211 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
212 system.physmem.busUtil 0.00 # Data bus utilization in percentage
213 system.physmem.avgRdQLen 0.00 # Average read queue length over time
214 system.physmem.avgWrQLen 0.00 # Average write queue length over time
215 system.physmem.readRowHits 0 # Number of row buffer hits during reads
216 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217 system.physmem.readRowHitRate nan # Row buffer hit rate for reads
218 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219 system.physmem.avgGap nan # Average gap between requests
220 system.l2c.replacements 62242 # number of replacements
221 system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use
222 system.l2c.total_refs 1678485 # Total number of references to valid blocks.
223 system.l2c.sampled_refs 127627 # Sample count of references to valid blocks.
224 system.l2c.avg_refs 13.151488 # Average number of references to valid blocks.
225 system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
226 system.l2c.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
227 system.l2c.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
228 system.l2c.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
229 system.l2c.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
230 system.l2c.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
231 system.l2c.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
232 system.l2c.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
233 system.l2c.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
234 system.l2c.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
235 system.l2c.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
236 system.l2c.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy
237 system.l2c.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy
238 system.l2c.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy
239 system.l2c.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy
240 system.l2c.occ_percent::total 0.763036 # Average percentage of cache occupancy
241 system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits
242 system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits
243 system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits
244 system.l2c.ReadReq_hits::cpu0.data 196972 # number of ReadReq hits
245 system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits
246 system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits
247 system.l2c.ReadReq_hits::cpu1.inst 365737 # number of ReadReq hits
248 system.l2c.ReadReq_hits::cpu1.data 169792 # number of ReadReq hits
249 system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits
250 system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits
251 system.l2c.Writeback_hits::total 592682 # number of Writeback hits
252 system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
253 system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits
254 system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
255 system.l2c.ReadExReq_hits::cpu0.data 63335 # number of ReadExReq hits
256 system.l2c.ReadExReq_hits::cpu1.data 50403 # number of ReadExReq hits
257 system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits
258 system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits
259 system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits
260 system.l2c.demand_hits::cpu0.inst 473134 # number of demand (read+write) hits
261 system.l2c.demand_hits::cpu0.data 260307 # number of demand (read+write) hits
262 system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits
263 system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits
264 system.l2c.demand_hits::cpu1.inst 365737 # number of demand (read+write) hits
265 system.l2c.demand_hits::cpu1.data 220195 # number of demand (read+write) hits
266 system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits
267 system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits
268 system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits
269 system.l2c.overall_hits::cpu0.inst 473134 # number of overall hits
270 system.l2c.overall_hits::cpu0.data 260307 # number of overall hits
271 system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits
272 system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits
273 system.l2c.overall_hits::cpu1.inst 365737 # number of overall hits
274 system.l2c.overall_hits::cpu1.data 220195 # number of overall hits
275 system.l2c.overall_hits::total 1338580 # number of overall hits
276 system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses
277 system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
278 system.l2c.ReadReq_misses::cpu0.inst 7285 # number of ReadReq misses
279 system.l2c.ReadReq_misses::cpu0.data 5807 # number of ReadReq misses
280 system.l2c.ReadReq_misses::cpu1.inst 3319 # number of ReadReq misses
281 system.l2c.ReadReq_misses::cpu1.data 4065 # number of ReadReq misses
282 system.l2c.ReadReq_misses::total 20481 # number of ReadReq misses
283 system.l2c.UpgradeReq_misses::cpu0.data 1520 # number of UpgradeReq misses
284 system.l2c.UpgradeReq_misses::cpu1.data 1399 # number of UpgradeReq misses
285 system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
286 system.l2c.ReadExReq_misses::cpu0.data 96488 # number of ReadExReq misses
287 system.l2c.ReadExReq_misses::cpu1.data 36984 # number of ReadExReq misses
288 system.l2c.ReadExReq_misses::total 133472 # number of ReadExReq misses
289 system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses
290 system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
291 system.l2c.demand_misses::cpu0.inst 7285 # number of demand (read+write) misses
292 system.l2c.demand_misses::cpu0.data 102295 # number of demand (read+write) misses
293 system.l2c.demand_misses::cpu1.inst 3319 # number of demand (read+write) misses
294 system.l2c.demand_misses::cpu1.data 41049 # number of demand (read+write) misses
295 system.l2c.demand_misses::total 153953 # number of demand (read+write) misses
296 system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses
297 system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
298 system.l2c.overall_misses::cpu0.inst 7285 # number of overall misses
299 system.l2c.overall_misses::cpu0.data 102295 # number of overall misses
300 system.l2c.overall_misses::cpu1.inst 3319 # number of overall misses
301 system.l2c.overall_misses::cpu1.data 41049 # number of overall misses
302 system.l2c.overall_misses::total 153953 # number of overall misses
303 system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses)
304 system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses)
305 system.l2c.ReadReq_accesses::cpu0.inst 480419 # number of ReadReq accesses(hits+misses)
306 system.l2c.ReadReq_accesses::cpu0.data 202779 # number of ReadReq accesses(hits+misses)
307 system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses)
308 system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses)
309 system.l2c.ReadReq_accesses::cpu1.inst 369056 # number of ReadReq accesses(hits+misses)
310 system.l2c.ReadReq_accesses::cpu1.data 173857 # number of ReadReq accesses(hits+misses)
311 system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses)
312 system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses)
313 system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses)
314 system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses)
315 system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses)
316 system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
317 system.l2c.ReadExReq_accesses::cpu0.data 159823 # number of ReadExReq accesses(hits+misses)
318 system.l2c.ReadExReq_accesses::cpu1.data 87387 # number of ReadExReq accesses(hits+misses)
319 system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses)
320 system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses
321 system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses
322 system.l2c.demand_accesses::cpu0.inst 480419 # number of demand (read+write) accesses
323 system.l2c.demand_accesses::cpu0.data 362602 # number of demand (read+write) accesses
324 system.l2c.demand_accesses::cpu1.dtb.walker 4875 # number of demand (read+write) accesses
325 system.l2c.demand_accesses::cpu1.itb.walker 2050 # number of demand (read+write) accesses
326 system.l2c.demand_accesses::cpu1.inst 369056 # number of demand (read+write) accesses
327 system.l2c.demand_accesses::cpu1.data 261244 # number of demand (read+write) accesses
328 system.l2c.demand_accesses::total 1492533 # number of demand (read+write) accesses
329 system.l2c.overall_accesses::cpu0.dtb.walker 9007 # number of overall (read+write) accesses
330 system.l2c.overall_accesses::cpu0.itb.walker 3280 # number of overall (read+write) accesses
331 system.l2c.overall_accesses::cpu0.inst 480419 # number of overall (read+write) accesses
332 system.l2c.overall_accesses::cpu0.data 362602 # number of overall (read+write) accesses
333 system.l2c.overall_accesses::cpu1.dtb.walker 4875 # number of overall (read+write) accesses
334 system.l2c.overall_accesses::cpu1.itb.walker 2050 # number of overall (read+write) accesses
335 system.l2c.overall_accesses::cpu1.inst 369056 # number of overall (read+write) accesses
336 system.l2c.overall_accesses::cpu1.data 261244 # number of overall (read+write) accesses
337 system.l2c.overall_accesses::total 1492533 # number of overall (read+write) accesses
338 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses
339 system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses
340 system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses
341 system.l2c.ReadReq_miss_rate::cpu0.data 0.028637 # miss rate for ReadReq accesses
342 system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses
343 system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses
344 system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses
345 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992167 # miss rate for UpgradeReq accesses
346 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990092 # miss rate for UpgradeReq accesses
347 system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
348 system.l2c.ReadExReq_miss_rate::cpu0.data 0.603718 # miss rate for ReadExReq accesses
349 system.l2c.ReadExReq_miss_rate::cpu1.data 0.423221 # miss rate for ReadExReq accesses
350 system.l2c.ReadExReq_miss_rate::total 0.539913 # miss rate for ReadExReq accesses
351 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses
352 system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses
353 system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses
354 system.l2c.demand_miss_rate::cpu0.data 0.282114 # miss rate for demand accesses
355 system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses
356 system.l2c.demand_miss_rate::cpu1.data 0.157129 # miss rate for demand accesses
357 system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses
358 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses
359 system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses
360 system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses
361 system.l2c.overall_miss_rate::cpu0.data 0.282114 # miss rate for overall accesses
362 system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses
363 system.l2c.overall_miss_rate::cpu1.data 0.157129 # miss rate for overall accesses
364 system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses
365 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
366 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
367 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
368 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
369 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
370 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
371 system.l2c.fast_writes 0 # number of fast writes performed
372 system.l2c.cache_copies 0 # number of cache copies performed
373 system.l2c.writebacks::writebacks 57860 # number of writebacks
374 system.l2c.writebacks::total 57860 # number of writebacks
375 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
376 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
377 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
378 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
379 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
380 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
381 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
382 system.cpu0.dtb.inst_hits 0 # ITB inst hits
383 system.cpu0.dtb.inst_misses 0 # ITB inst misses
384 system.cpu0.dtb.read_hits 7929205 # DTB read hits
385 system.cpu0.dtb.read_misses 6441 # DTB read misses
386 system.cpu0.dtb.write_hits 6437098 # DTB write hits
387 system.cpu0.dtb.write_misses 1932 # DTB write misses
388 system.cpu0.dtb.flush_tlb 1168 # Number of times complete TLB was flushed
389 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
390 system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
391 system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
392 system.cpu0.dtb.flush_entries 5576 # Number of entries that have been flushed from TLB
393 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
394 system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
395 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
396 system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions
397 system.cpu0.dtb.read_accesses 7935646 # DTB read accesses
398 system.cpu0.dtb.write_accesses 6439030 # DTB write accesses
399 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
400 system.cpu0.dtb.hits 14366303 # DTB hits
401 system.cpu0.dtb.misses 8373 # DTB misses
402 system.cpu0.dtb.accesses 14374676 # DTB accesses
403 system.cpu0.itb.inst_hits 32543253 # ITB inst hits
404 system.cpu0.itb.inst_misses 3703 # ITB inst misses
405 system.cpu0.itb.read_hits 0 # DTB read hits
406 system.cpu0.itb.read_misses 0 # DTB read misses
407 system.cpu0.itb.write_hits 0 # DTB write hits
408 system.cpu0.itb.write_misses 0 # DTB write misses
409 system.cpu0.itb.flush_tlb 1168 # Number of times complete TLB was flushed
410 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
411 system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
412 system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
413 system.cpu0.itb.flush_entries 2636 # Number of entries that have been flushed from TLB
414 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
415 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
416 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
417 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
418 system.cpu0.itb.read_accesses 0 # DTB read accesses
419 system.cpu0.itb.write_accesses 0 # DTB write accesses
420 system.cpu0.itb.inst_accesses 32546956 # ITB inst accesses
421 system.cpu0.itb.hits 32543253 # DTB hits
422 system.cpu0.itb.misses 3703 # DTB misses
423 system.cpu0.itb.accesses 32546956 # DTB accesses
424 system.cpu0.numCycles 4633589665 # number of cpu cycles simulated
425 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
426 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
427 system.cpu0.committedInsts 31998091 # Number of instructions committed
428 system.cpu0.committedOps 41901593 # Number of ops (including micro ops) committed
429 system.cpu0.num_int_alu_accesses 37065495 # Number of integer alu accesses
430 system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses
431 system.cpu0.num_func_calls 1207173 # number of times a function call or return occured
432 system.cpu0.num_conditional_control_insts 4285544 # number of instructions that are conditional controls
433 system.cpu0.num_int_insts 37065495 # number of integer instructions
434 system.cpu0.num_fp_insts 5364 # number of float instructions
435 system.cpu0.num_int_register_reads 188704279 # number of times the integer registers were read
436 system.cpu0.num_int_register_writes 39536975 # number of times the integer registers were written
437 system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read
438 system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written
439 system.cpu0.num_mem_refs 15013057 # number of memory refs
440 system.cpu0.num_load_insts 8304661 # Number of load instructions
441 system.cpu0.num_store_insts 6708396 # Number of store instructions
442 system.cpu0.num_idle_cycles 186586201.060505 # Number of idle cycles
443 system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles
444 system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles
445 system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles
446 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
447 system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
448 system.cpu0.icache.replacements 850590 # number of replacements
449 system.cpu0.icache.tagsinuse 511.678593 # Cycle average of tags in use
450 system.cpu0.icache.total_refs 60583498 # Total number of references to valid blocks.
451 system.cpu0.icache.sampled_refs 851102 # Sample count of references to valid blocks.
452 system.cpu0.icache.avg_refs 71.182418 # Average number of references to valid blocks.
453 system.cpu0.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
454 system.cpu0.icache.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor
455 system.cpu0.icache.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor
456 system.cpu0.icache.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy
457 system.cpu0.icache.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy
458 system.cpu0.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
459 system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits
460 system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits
461 system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
462 system.cpu0.icache.demand_hits::cpu0.inst 32064735 # number of demand (read+write) hits
463 system.cpu0.icache.demand_hits::cpu1.inst 28518763 # number of demand (read+write) hits
464 system.cpu0.icache.demand_hits::total 60583498 # number of demand (read+write) hits
465 system.cpu0.icache.overall_hits::cpu0.inst 32064735 # number of overall hits
466 system.cpu0.icache.overall_hits::cpu1.inst 28518763 # number of overall hits
467 system.cpu0.icache.overall_hits::total 60583498 # number of overall hits
468 system.cpu0.icache.ReadReq_misses::cpu0.inst 481297 # number of ReadReq misses
469 system.cpu0.icache.ReadReq_misses::cpu1.inst 369805 # number of ReadReq misses
470 system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses
471 system.cpu0.icache.demand_misses::cpu0.inst 481297 # number of demand (read+write) misses
472 system.cpu0.icache.demand_misses::cpu1.inst 369805 # number of demand (read+write) misses
473 system.cpu0.icache.demand_misses::total 851102 # number of demand (read+write) misses
474 system.cpu0.icache.overall_misses::cpu0.inst 481297 # number of overall misses
475 system.cpu0.icache.overall_misses::cpu1.inst 369805 # number of overall misses
476 system.cpu0.icache.overall_misses::total 851102 # number of overall misses
477 system.cpu0.icache.ReadReq_accesses::cpu0.inst 32546032 # number of ReadReq accesses(hits+misses)
478 system.cpu0.icache.ReadReq_accesses::cpu1.inst 28888568 # number of ReadReq accesses(hits+misses)
479 system.cpu0.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
480 system.cpu0.icache.demand_accesses::cpu0.inst 32546032 # number of demand (read+write) accesses
481 system.cpu0.icache.demand_accesses::cpu1.inst 28888568 # number of demand (read+write) accesses
482 system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
483 system.cpu0.icache.overall_accesses::cpu0.inst 32546032 # number of overall (read+write) accesses
484 system.cpu0.icache.overall_accesses::cpu1.inst 28888568 # number of overall (read+write) accesses
485 system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
486 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses
487 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses
488 system.cpu0.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
489 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014788 # miss rate for demand accesses
490 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012801 # miss rate for demand accesses
491 system.cpu0.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
492 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014788 # miss rate for overall accesses
493 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012801 # miss rate for overall accesses
494 system.cpu0.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
495 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
496 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
497 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
498 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
499 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
500 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
501 system.cpu0.icache.fast_writes 0 # number of fast writes performed
502 system.cpu0.icache.cache_copies 0 # number of cache copies performed
503 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
504 system.cpu0.dcache.replacements 623334 # number of replacements
505 system.cpu0.dcache.tagsinuse 511.997031 # Cycle average of tags in use
506 system.cpu0.dcache.total_refs 23628284 # Total number of references to valid blocks.
507 system.cpu0.dcache.sampled_refs 623846 # Sample count of references to valid blocks.
508 system.cpu0.dcache.avg_refs 37.875187 # Average number of references to valid blocks.
509 system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
510 system.cpu0.dcache.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor
511 system.cpu0.dcache.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor
512 system.cpu0.dcache.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy
513 system.cpu0.dcache.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy
514 system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
515 system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits
516 system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits
517 system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits
518 system.cpu0.dcache.WriteReq_hits::cpu0.data 5776861 # number of WriteReq hits
519 system.cpu0.dcache.WriteReq_hits::cpu1.data 4185204 # number of WriteReq hits
520 system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits
521 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139289 # number of LoadLockedReq hits
522 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96747 # number of LoadLockedReq hits
523 system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits
524 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145935 # number of StoreCondReq hits
525 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101283 # number of StoreCondReq hits
526 system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits
527 system.cpu0.dcache.demand_hits::cpu0.data 12772451 # number of demand (read+write) hits
528 system.cpu0.dcache.demand_hits::cpu1.data 10369634 # number of demand (read+write) hits
529 system.cpu0.dcache.demand_hits::total 23142085 # number of demand (read+write) hits
530 system.cpu0.dcache.overall_hits::cpu0.data 12772451 # number of overall hits
531 system.cpu0.dcache.overall_hits::cpu1.data 10369634 # number of overall hits
532 system.cpu0.dcache.overall_hits::total 23142085 # number of overall hits
533 system.cpu0.dcache.ReadReq_misses::cpu0.data 196132 # number of ReadReq misses
534 system.cpu0.dcache.ReadReq_misses::cpu1.data 169321 # number of ReadReq misses
535 system.cpu0.dcache.ReadReq_misses::total 365453 # number of ReadReq misses
536 system.cpu0.dcache.WriteReq_misses::cpu0.data 161355 # number of WriteReq misses
537 system.cpu0.dcache.WriteReq_misses::cpu1.data 88800 # number of WriteReq misses
538 system.cpu0.dcache.WriteReq_misses::total 250155 # number of WriteReq misses
539 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6647 # number of LoadLockedReq misses
540 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses
541 system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
542 system.cpu0.dcache.demand_misses::cpu0.data 357487 # number of demand (read+write) misses
543 system.cpu0.dcache.demand_misses::cpu1.data 258121 # number of demand (read+write) misses
544 system.cpu0.dcache.demand_misses::total 615608 # number of demand (read+write) misses
545 system.cpu0.dcache.overall_misses::cpu0.data 357487 # number of overall misses
546 system.cpu0.dcache.overall_misses::cpu1.data 258121 # number of overall misses
547 system.cpu0.dcache.overall_misses::total 615608 # number of overall misses
548 system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191722 # number of ReadReq accesses(hits+misses)
549 system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353751 # number of ReadReq accesses(hits+misses)
550 system.cpu0.dcache.ReadReq_accesses::total 13545473 # number of ReadReq accesses(hits+misses)
551 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938216 # number of WriteReq accesses(hits+misses)
552 system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274004 # number of WriteReq accesses(hits+misses)
553 system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses)
554 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145936 # number of LoadLockedReq accesses(hits+misses)
555 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101283 # number of LoadLockedReq accesses(hits+misses)
556 system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses)
557 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145935 # number of StoreCondReq accesses(hits+misses)
558 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101283 # number of StoreCondReq accesses(hits+misses)
559 system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses)
560 system.cpu0.dcache.demand_accesses::cpu0.data 13129938 # number of demand (read+write) accesses
561 system.cpu0.dcache.demand_accesses::cpu1.data 10627755 # number of demand (read+write) accesses
562 system.cpu0.dcache.demand_accesses::total 23757693 # number of demand (read+write) accesses
563 system.cpu0.dcache.overall_accesses::cpu0.data 13129938 # number of overall (read+write) accesses
564 system.cpu0.dcache.overall_accesses::cpu1.data 10627755 # number of overall (read+write) accesses
565 system.cpu0.dcache.overall_accesses::total 23757693 # number of overall (read+write) accesses
566 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027272 # miss rate for ReadReq accesses
567 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026649 # miss rate for ReadReq accesses
568 system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
569 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses
570 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses
571 system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses
572 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045547 # miss rate for LoadLockedReq accesses
573 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044785 # miss rate for LoadLockedReq accesses
574 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
575 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses
576 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024287 # miss rate for demand accesses
577 system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
578 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses
579 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024287 # miss rate for overall accesses
580 system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
581 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
582 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
583 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
584 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
585 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
586 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
587 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
588 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
589 system.cpu0.dcache.writebacks::writebacks 592682 # number of writebacks
590 system.cpu0.dcache.writebacks::total 592682 # number of writebacks
591 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
592 system.cpu1.dtb.inst_hits 0 # ITB inst hits
593 system.cpu1.dtb.inst_misses 0 # ITB inst misses
594 system.cpu1.dtb.read_hits 7038595 # DTB read hits
595 system.cpu1.dtb.read_misses 4223 # DTB read misses
596 system.cpu1.dtb.write_hits 4778906 # DTB write hits
597 system.cpu1.dtb.write_misses 1249 # DTB write misses
598 system.cpu1.dtb.flush_tlb 1166 # Number of times complete TLB was flushed
599 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
600 system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
601 system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
602 system.cpu1.dtb.flush_entries 2949 # Number of entries that have been flushed from TLB
603 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
604 system.cpu1.dtb.prefetch_faults 82 # Number of TLB faults due to prefetch
605 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
606 system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
607 system.cpu1.dtb.read_accesses 7042818 # DTB read accesses
608 system.cpu1.dtb.write_accesses 4780155 # DTB write accesses
609 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
610 system.cpu1.dtb.hits 11817501 # DTB hits
611 system.cpu1.dtb.misses 5472 # DTB misses
612 system.cpu1.dtb.accesses 11822973 # DTB accesses
613 system.cpu1.itb.inst_hits 28886892 # ITB inst hits
614 system.cpu1.itb.inst_misses 2463 # ITB inst misses
615 system.cpu1.itb.read_hits 0 # DTB read hits
616 system.cpu1.itb.read_misses 0 # DTB read misses
617 system.cpu1.itb.write_hits 0 # DTB write hits
618 system.cpu1.itb.write_misses 0 # DTB write misses
619 system.cpu1.itb.flush_tlb 1166 # Number of times complete TLB was flushed
620 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
621 system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
622 system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
623 system.cpu1.itb.flush_entries 1597 # Number of entries that have been flushed from TLB
624 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
625 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
626 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
627 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
628 system.cpu1.itb.read_accesses 0 # DTB read accesses
629 system.cpu1.itb.write_accesses 0 # DTB write accesses
630 system.cpu1.itb.inst_accesses 28889355 # ITB inst accesses
631 system.cpu1.itb.hits 28886892 # DTB hits
632 system.cpu1.itb.misses 2463 # DTB misses
633 system.cpu1.itb.accesses 28889355 # DTB accesses
634 system.cpu1.numCycles 4279954879 # number of cpu cycles simulated
635 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
636 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
637 system.cpu1.committedInsts 28410548 # Number of instructions committed
638 system.cpu1.committedOps 35780226 # Number of ops (including micro ops) committed
639 system.cpu1.num_int_alu_accesses 31730110 # Number of integer alu accesses
640 system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses
641 system.cpu1.num_func_calls 928835 # number of times a function call or return occured
642 system.cpu1.num_conditional_control_insts 3656569 # number of instructions that are conditional controls
643 system.cpu1.num_int_insts 31730110 # number of integer instructions
644 system.cpu1.num_fp_insts 4905 # number of float instructions
645 system.cpu1.num_int_register_reads 160619995 # number of times the integer registers were read
646 system.cpu1.num_int_register_writes 34566633 # number of times the integer registers were written
647 system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read
648 system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written
649 system.cpu1.num_mem_refs 12348580 # number of memory refs
650 system.cpu1.num_load_insts 7334866 # Number of load instructions
651 system.cpu1.num_store_insts 5013714 # Number of store instructions
652 system.cpu1.num_idle_cycles 8315278901.051629 # Number of idle cycles
653 system.cpu1.num_busy_cycles -4035324022.051629 # Number of busy cycles
654 system.cpu1.not_idle_fraction -0.942843 # Percentage of non-idle cycles
655 system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles
656 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
657 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
658 system.iocache.replacements 0 # number of replacements
659 system.iocache.tagsinuse 0 # Cycle average of tags in use
660 system.iocache.total_refs 0 # Total number of references to valid blocks.
661 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
662 system.iocache.avg_refs nan # Average number of references to valid blocks.
663 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
664 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
665 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
666 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
667 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
668 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
669 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
670 system.iocache.fast_writes 0 # number of fast writes performed
671 system.iocache.cache_copies 0 # number of cache copies performed
672 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
674 ---------- End Simulation Statistics ----------
projects / gem5.git / blob