8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/dist/m5/system/binaries/boot_emm.arm
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
23 exit_on_work_items=false
25 gic_cpu_addr=738205696
26 have_large_asid_64=false
29 have_virtualization=false
30 highest_el_is_64=false
32 kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
33 kernel_addr_check=true
34 load_addr_mask=268435455
35 load_offset=2147483648
36 machine_type=VExpress_EMM
38 mem_ranges=2147483648:2415919103
39 memories=system.physmem system.realview.nvmem system.realview.vram
40 mmap_using_noreserve=false
47 readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
50 work_begin_ckpt_count=0
51 work_begin_cpu_id_exit=-1
52 work_begin_exit_count=0
53 work_cpus_ckpt_count=0
57 system_port=system.membus.slave[1]
61 clk_domain=system.clk_domain
64 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
67 master=system.iobus.slave[0]
68 slave=system.membus.master[0]
76 image=system.cf0.image
81 child=system.cf0.image.child
87 [system.cf0.image.child]
90 image_file=/dist/m5/system/disks/linux-aarch32-ael.img
99 voltage_domain=system.voltage_domain
103 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
106 clk_domain=system.cpu_clk_domain
108 do_checkpoint_insts=true
110 do_statistics_insts=true
111 dstage2_mmu=system.cpu0.dstage2_mmu
115 function_trace_start=0
116 interrupts=system.cpu0.interrupts
118 istage2_mmu=system.cpu0.istage2_mmu
120 max_insts_all_threads=0
121 max_insts_any_thread=0
122 max_loads_all_threads=0
123 max_loads_any_thread=0
127 simpoint_start_insts=
131 tracer=system.cpu0.tracer
133 dcache_port=system.cpu0.dcache.cpu_side
134 icache_port=system.cpu0.icache.cpu_side
139 addr_ranges=0:18446744073709551615
141 clk_domain=system.cpu_clk_domain
142 clusivity=mostly_incl
143 demand_mshr_reserve=1
150 prefetch_on_access=false
153 sequential_access=false
156 tags=system.cpu0.dcache.tags
159 writeback_clean=false
160 cpu_side=system.cpu0.dcache_port
161 mem_side=system.toL2Bus.slave[1]
163 [system.cpu0.dcache.tags]
167 clk_domain=system.cpu_clk_domain
170 sequential_access=false
173 [system.cpu0.dstage2_mmu]
177 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
181 [system.cpu0.dstage2_mmu.stage2_tlb]
187 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
189 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
191 clk_domain=system.cpu_clk_domain
194 num_squash_per_cycle=2
203 walker=system.cpu0.dtb.walker
205 [system.cpu0.dtb.walker]
207 clk_domain=system.cpu_clk_domain
210 num_squash_per_cycle=2
212 port=system.toL2Bus.slave[3]
217 addr_ranges=0:18446744073709551615
219 clk_domain=system.cpu_clk_domain
220 clusivity=mostly_incl
221 demand_mshr_reserve=1
228 prefetch_on_access=false
231 sequential_access=false
234 tags=system.cpu0.icache.tags
238 cpu_side=system.cpu0.icache_port
239 mem_side=system.toL2Bus.slave[0]
241 [system.cpu0.icache.tags]
245 clk_domain=system.cpu_clk_domain
248 sequential_access=false
251 [system.cpu0.interrupts]
257 decoderFlavour=Generic
262 id_aa64dfr0_el1=1052678
266 id_aa64mmfr0_el1=15728642
286 [system.cpu0.istage2_mmu]
290 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
294 [system.cpu0.istage2_mmu.stage2_tlb]
300 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
302 [system.cpu0.istage2_mmu.stage2_tlb.walker]
304 clk_domain=system.cpu_clk_domain
307 num_squash_per_cycle=2
316 walker=system.cpu0.itb.walker
318 [system.cpu0.itb.walker]
320 clk_domain=system.cpu_clk_domain
323 num_squash_per_cycle=2
325 port=system.toL2Bus.slave[2]
333 children=dstage2_mmu dtb isa istage2_mmu itb tracer
336 clk_domain=system.cpu_clk_domain
338 do_checkpoint_insts=true
340 do_statistics_insts=true
341 dstage2_mmu=system.cpu1.dstage2_mmu
345 function_trace_start=0
348 istage2_mmu=system.cpu1.istage2_mmu
350 max_insts_all_threads=0
351 max_insts_any_thread=0
352 max_loads_all_threads=0
353 max_loads_any_thread=0
357 simpoint_start_insts=
361 tracer=system.cpu1.tracer
364 [system.cpu1.dstage2_mmu]
368 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
372 [system.cpu1.dstage2_mmu.stage2_tlb]
378 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
380 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
382 clk_domain=system.cpu_clk_domain
385 num_squash_per_cycle=2
394 walker=system.cpu1.dtb.walker
396 [system.cpu1.dtb.walker]
398 clk_domain=system.cpu_clk_domain
401 num_squash_per_cycle=2
406 decoderFlavour=Generic
411 id_aa64dfr0_el1=1052678
415 id_aa64mmfr0_el1=15728642
435 [system.cpu1.istage2_mmu]
439 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
443 [system.cpu1.istage2_mmu.stage2_tlb]
449 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
451 [system.cpu1.istage2_mmu.stage2_tlb.walker]
453 clk_domain=system.cpu_clk_domain
456 num_squash_per_cycle=2
465 walker=system.cpu1.itb.walker
467 [system.cpu1.itb.walker]
469 clk_domain=system.cpu_clk_domain
472 num_squash_per_cycle=2
479 [system.cpu_clk_domain]
485 voltage_domain=system.voltage_domain
487 [system.dvfs_handler]
492 sys_clk_domain=system.clk_domain
493 transition_latency=100000000
502 clk_domain=system.clk_domain
507 use_default_range=false
509 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
510 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
515 addr_ranges=2147483648:2415919103
517 clk_domain=system.clk_domain
518 clusivity=mostly_incl
519 demand_mshr_reserve=1
526 prefetch_on_access=false
529 sequential_access=false
532 tags=system.iocache.tags
535 writeback_clean=false
536 cpu_side=system.iobus.master[25]
537 mem_side=system.membus.slave[3]
539 [system.iocache.tags]
543 clk_domain=system.clk_domain
546 sequential_access=false
552 addr_ranges=0:18446744073709551615
554 clk_domain=system.cpu_clk_domain
555 clusivity=mostly_incl
556 demand_mshr_reserve=1
563 prefetch_on_access=false
566 sequential_access=false
572 writeback_clean=false
573 cpu_side=system.toL2Bus.master[0]
574 mem_side=system.membus.slave[2]
580 clk_domain=system.cpu_clk_domain
583 sequential_access=false
588 children=badaddr_responder
589 clk_domain=system.clk_domain
595 snoop_response_latency=4
597 use_default_range=false
599 default=system.membus.badaddr_responder.pio
600 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
601 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
603 [system.membus.badaddr_responder]
605 clk_domain=system.clk_domain
613 ret_data32=4294967295
614 ret_data64=18446744073709551615
619 pio=system.membus.default
648 addr_mapping=RoRaBaCoCh
649 bank_groups_per_rank=0
653 clk_domain=system.clk_domain
654 conf_table_reported=true
656 device_rowbuffer_size=1024
657 device_size=536870912
662 max_accesses_per_row=16
663 mem_sched_policy=frfcfs
664 min_writes_per_switch=16
666 page_policy=open_adaptive
667 range=2147483648:2415919103
670 static_backend_latency=10000
671 static_frontend_latency=10000
694 write_high_thresh_perc=85
695 write_low_thresh_perc=50
696 port=system.membus.master[5]
700 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
702 intrctrl=system.intrctrl
705 [system.realview.aaci_fake]
708 clk_domain=system.clk_domain
714 pio=system.iobus.master[18]
716 [system.realview.cf_ctrl]
756 MSICAPNextCapability=0
760 MSIXCAPNextCapability=0
770 PMCAPNextCapability=0
775 PXCAPDevCapabilities=0
782 PXCAPNextCapability=0
790 clk_domain=system.clk_domain
795 host=system.realview.pci_host
802 dma=system.iobus.slave[2]
803 pio=system.iobus.master[9]
805 [system.realview.clcd]
808 clk_domain=system.clk_domain
811 gic=system.realview.gic
818 dma=system.iobus.slave[1]
819 pio=system.iobus.master[5]
821 [system.realview.dcc]
823 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
826 [system.realview.dcc.osc_cpu]
832 parent=system.realview.realview_io
835 voltage_domain=system.voltage_domain
837 [system.realview.dcc.osc_ddr]
843 parent=system.realview.realview_io
846 voltage_domain=system.voltage_domain
848 [system.realview.dcc.osc_hsbm]
854 parent=system.realview.realview_io
857 voltage_domain=system.voltage_domain
859 [system.realview.dcc.osc_pxl]
865 parent=system.realview.realview_io
868 voltage_domain=system.voltage_domain
870 [system.realview.dcc.osc_smb]
876 parent=system.realview.realview_io
879 voltage_domain=system.voltage_domain
881 [system.realview.dcc.osc_sys]
887 parent=system.realview.realview_io
890 voltage_domain=system.voltage_domain
892 [system.realview.energy_ctrl]
894 clk_domain=system.clk_domain
895 dvfs_handler=system.dvfs_handler
900 pio=system.iobus.master[22]
902 [system.realview.ethernet]
942 MSICAPNextCapability=0
946 MSIXCAPNextCapability=0
956 PMCAPNextCapability=0
961 PXCAPDevCapabilities=0
968 PXCAPNextCapability=0
974 SubsystemVendorID=32902
976 clk_domain=system.clk_domain
979 fetch_comp_delay=10000
981 hardware_address=00:90:00:00:00:01
982 host=system.realview.pci_host
989 rx_desc_cache_size=64
993 tx_desc_cache_size=64
998 dma=system.iobus.slave[4]
999 pio=system.iobus.master[24]
1001 [system.realview.generic_timer]
1004 gic=system.realview.gic
1009 [system.realview.gic]
1011 clk_domain=system.clk_domain
1015 dist_pio_delay=10000
1019 platform=system.realview
1021 pio=system.membus.master[2]
1023 [system.realview.hdlcd]
1026 clk_domain=system.clk_domain
1029 gic=system.realview.gic
1033 pixel_buffer_size=2048
1035 pxl_clk=system.realview.dcc.osc_pxl
1037 vnc=system.vncserver
1038 workaround_dma_line_count=true
1039 workaround_swap_rb=true
1040 dma=system.membus.slave[0]
1041 pio=system.iobus.master[6]
1043 [system.realview.ide]
1082 MSICAPMsgUpperAddr=0
1083 MSICAPNextCapability=0
1087 MSIXCAPNextCapability=0
1097 PMCAPNextCapability=0
1102 PXCAPDevCapabilities=0
1109 PXCAPNextCapability=0
1117 clk_domain=system.clk_domain
1118 config_latency=20000
1122 host=system.realview.pci_host
1129 dma=system.iobus.slave[3]
1130 pio=system.iobus.master[23]
1132 [system.realview.kmi0]
1135 clk_domain=system.clk_domain
1137 gic=system.realview.gic
1144 vnc=system.vncserver
1145 pio=system.iobus.master[7]
1147 [system.realview.kmi1]
1150 clk_domain=system.clk_domain
1152 gic=system.realview.gic
1159 vnc=system.vncserver
1160 pio=system.iobus.master[8]
1162 [system.realview.l2x0_fake]
1164 clk_domain=system.clk_domain
1172 ret_data32=4294967295
1173 ret_data64=18446744073709551615
1178 pio=system.iobus.master[12]
1180 [system.realview.lan_fake]
1182 clk_domain=system.clk_domain
1190 ret_data32=4294967295
1191 ret_data64=18446744073709551615
1196 pio=system.iobus.master[19]
1198 [system.realview.local_cpu_timer]
1200 clk_domain=system.clk_domain
1202 gic=system.realview.gic
1208 pio=system.membus.master[4]
1210 [system.realview.mcc]
1212 children=osc_clcd osc_mcc osc_peripheral osc_system_bus
1215 [system.realview.mcc.osc_clcd]
1221 parent=system.realview.realview_io
1224 voltage_domain=system.voltage_domain
1226 [system.realview.mcc.osc_mcc]
1232 parent=system.realview.realview_io
1235 voltage_domain=system.voltage_domain
1237 [system.realview.mcc.osc_peripheral]
1243 parent=system.realview.realview_io
1246 voltage_domain=system.voltage_domain
1248 [system.realview.mcc.osc_system_bus]
1254 parent=system.realview.realview_io
1257 voltage_domain=system.voltage_domain
1259 [system.realview.mmc_fake]
1262 clk_domain=system.clk_domain
1268 pio=system.iobus.master[21]
1270 [system.realview.nvmem]
1273 clk_domain=system.clk_domain
1274 conf_table_reported=false
1281 port=system.membus.master[1]
1283 [system.realview.pci_host]
1285 clk_domain=system.clk_domain
1293 platform=system.realview
1295 pio=system.iobus.master[2]
1297 [system.realview.realview_io]
1299 clk_domain=system.clk_domain
1307 pio=system.iobus.master[1]
1309 [system.realview.rtc]
1312 clk_domain=system.clk_domain
1314 gic=system.realview.gic
1320 time=Thu Jan 1 00:00:00 2009
1321 pio=system.iobus.master[10]
1323 [system.realview.sp810_fake]
1326 clk_domain=system.clk_domain
1332 pio=system.iobus.master[16]
1334 [system.realview.timer0]
1337 clk_domain=system.clk_domain
1341 gic=system.realview.gic
1347 pio=system.iobus.master[3]
1349 [system.realview.timer1]
1352 clk_domain=system.clk_domain
1356 gic=system.realview.gic
1362 pio=system.iobus.master[4]
1364 [system.realview.uart]
1366 clk_domain=system.clk_domain
1369 gic=system.realview.gic
1374 platform=system.realview
1376 terminal=system.terminal
1377 pio=system.iobus.master[0]
1379 [system.realview.uart1_fake]
1382 clk_domain=system.clk_domain
1388 pio=system.iobus.master[13]
1390 [system.realview.uart2_fake]
1393 clk_domain=system.clk_domain
1399 pio=system.iobus.master[14]
1401 [system.realview.uart3_fake]
1404 clk_domain=system.clk_domain
1410 pio=system.iobus.master[15]
1412 [system.realview.usb_fake]
1414 clk_domain=system.clk_domain
1422 ret_data32=4294967295
1423 ret_data64=18446744073709551615
1428 pio=system.iobus.master[20]
1430 [system.realview.vgic]
1432 clk_domain=system.clk_domain
1434 gic=system.realview.gic
1437 platform=system.realview
1441 pio=system.membus.master[3]
1443 [system.realview.vram]
1446 clk_domain=system.clk_domain
1447 conf_table_reported=false
1453 range=402653184:436207615
1454 port=system.iobus.master[11]
1456 [system.realview.watchdog_fake]
1459 clk_domain=system.clk_domain
1465 pio=system.iobus.master[17]
1470 intr_control=system.intrctrl
1477 children=snoop_filter
1478 clk_domain=system.cpu_clk_domain
1483 snoop_filter=system.toL2Bus.snoop_filter
1484 snoop_response_latency=1
1486 use_default_range=false
1488 master=system.l2c.cpu_side
1489 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
1491 [system.toL2Bus.snoop_filter]
1495 max_capacity=8388608
1505 [system.voltage_domain]