2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.112043 # Number of seconds simulated
4 sim_ticks 5112043255000 # Number of ticks simulated
5 final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1996585 # Simulator instruction rate (inst/s)
8 host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 51080652430 # Simulator tick rate (ticks/s)
10 host_mem_usage 357308 # Number of bytes of host memory used
11 host_seconds 100.08 # Real time elapsed on the host
12 sim_insts 199813912 # Number of instructions simulated
13 sim_ops 409133288 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s)
49 system.l2c.replacements 106561 # number of replacements
50 system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use
51 system.l2c.total_refs 3457342 # Total number of references to valid blocks.
52 system.l2c.sampled_refs 170680 # Sample count of references to valid blocks.
53 system.l2c.avg_refs 20.256281 # Average number of references to valid blocks.
54 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
55 system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor
56 system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
57 system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor
58 system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor
59 system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor
60 system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
61 system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
62 system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
63 system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
64 system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
65 system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy
66 system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
67 system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
68 system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
69 system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
70 system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits
71 system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits
72 system.l2c.Writeback_hits::total 1538939 # number of Writeback hits
73 system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
74 system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
75 system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
76 system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits
77 system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
78 system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
79 system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits
80 system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits
81 system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits
82 system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits
83 system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits
84 system.l2c.overall_hits::cpu.inst 777957 # number of overall hits
85 system.l2c.overall_hits::cpu.data 1454603 # number of overall hits
86 system.l2c.overall_hits::total 2241838 # number of overall hits
87 system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
88 system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
89 system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
90 system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses
91 system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses
92 system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
93 system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
94 system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses
95 system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses
96 system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
97 system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
98 system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
99 system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses
100 system.l2c.demand_misses::total 179910 # number of demand (read+write) misses
101 system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses
102 system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
103 system.l2c.overall_misses::cpu.inst 13342 # number of overall misses
104 system.l2c.overall_misses::cpu.data 166561 # number of overall misses
105 system.l2c.overall_misses::total 179910 # number of overall misses
106 system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
107 system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
108 system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
109 system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
110 system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
111 system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses)
112 system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses)
113 system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
114 system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
115 system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
116 system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses)
117 system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
118 system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
119 system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses
120 system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses
121 system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses
122 system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
123 system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
124 system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses
125 system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses
126 system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses
127 system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
128 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
129 system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses
130 system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses
131 system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses
132 system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
133 system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
134 system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses
135 system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses
136 system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
137 system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
138 system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses
139 system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses
140 system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses
141 system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
142 system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
143 system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses
144 system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses
145 system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses
146 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
147 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
148 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
149 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
150 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
151 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
152 system.l2c.fast_writes 0 # number of fast writes performed
153 system.l2c.cache_copies 0 # number of cache copies performed
154 system.l2c.writebacks::writebacks 98533 # number of writebacks
155 system.l2c.writebacks::total 98533 # number of writebacks
156 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
157 system.iocache.replacements 47570 # number of replacements
158 system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
159 system.iocache.total_refs 0 # Total number of references to valid blocks.
160 system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
161 system.iocache.avg_refs 0 # Average number of references to valid blocks.
162 system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
163 system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
164 system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
165 system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
166 system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
167 system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
168 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
169 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
170 system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
171 system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
172 system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
173 system.iocache.overall_misses::total 47625 # number of overall misses
174 system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
175 system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
176 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
177 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
178 system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
179 system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
180 system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
181 system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
182 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
183 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
184 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
185 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
186 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
187 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
188 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
189 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
190 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
191 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
192 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
193 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
194 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
195 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
196 system.iocache.fast_writes 0 # number of fast writes performed
197 system.iocache.cache_copies 0 # number of cache copies performed
198 system.iocache.writebacks::writebacks 46667 # number of writebacks
199 system.iocache.writebacks::total 46667 # number of writebacks
200 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
201 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
202 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
203 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
204 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
205 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
206 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
207 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
208 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
209 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
210 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
211 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
212 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
213 system.cpu.numCycles 10224086531 # number of cpu cycles simulated
214 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
215 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
216 system.cpu.committedInsts 199813912 # Number of instructions committed
217 system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed
218 system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses
219 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
220 system.cpu.num_func_calls 0 # number of times a function call or return occured
221 system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls
222 system.cpu.num_int_insts 374297254 # number of integer instructions
223 system.cpu.num_fp_insts 0 # number of float instructions
224 system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read
225 system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written
226 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
227 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
228 system.cpu.num_mem_refs 35626517 # number of memory refs
229 system.cpu.num_load_insts 27217782 # Number of load instructions
230 system.cpu.num_store_insts 8408735 # Number of store instructions
231 system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles
232 system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles
233 system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
234 system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
235 system.cpu.kern.inst.arm 0 # number of arm instructions executed
236 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
237 system.cpu.icache.replacements 790793 # number of replacements
238 system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
239 system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
240 system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks.
241 system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks.
242 system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
243 system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
244 system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
245 system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
246 system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
247 system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
248 system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
249 system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
250 system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
251 system.cpu.icache.overall_hits::total 243365777 # number of overall hits
252 system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses
253 system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses
254 system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses
255 system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses
256 system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses
257 system.cpu.icache.overall_misses::total 791312 # number of overall misses
258 system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses)
259 system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses)
260 system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses
261 system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses
262 system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses
263 system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses
264 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
265 system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
266 system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
267 system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
268 system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
269 system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
270 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
271 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
272 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
273 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
274 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
275 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
276 system.cpu.icache.fast_writes 0 # number of fast writes performed
277 system.cpu.icache.cache_copies 0 # number of cache copies performed
278 system.cpu.icache.writebacks::writebacks 809 # number of writebacks
279 system.cpu.icache.writebacks::total 809 # number of writebacks
280 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
281 system.cpu.itb_walker_cache.replacements 3335 # number of replacements
282 system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use
283 system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
284 system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
285 system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
286 system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit.
287 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor
288 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
289 system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy
290 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits
291 system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits
292 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
293 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
294 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits
295 system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits
296 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits
297 system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits
298 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses
299 system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses
300 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses
301 system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses
302 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses
303 system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses
304 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
305 system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
306 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
307 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
308 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
309 system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
310 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
311 system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
312 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses
313 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses
314 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses
315 system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses
316 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses
317 system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses
318 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
319 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
320 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
321 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
322 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
323 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
324 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
325 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
326 system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks
327 system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks
328 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
329 system.cpu.dtb_walker_cache.replacements 7598 # number of replacements
330 system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use
331 system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks.
332 system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks.
333 system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks.
334 system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit.
335 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor
336 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy
337 system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy
338 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits
339 system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits
340 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits
341 system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits
342 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits
343 system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits
344 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses
345 system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses
346 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses
347 system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses
348 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses
349 system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses
350 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
351 system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
352 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
353 system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
354 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
355 system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
356 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses
357 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses
358 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses
359 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses
360 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses
361 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses
362 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
363 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
364 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
365 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
366 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
367 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
368 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
369 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
370 system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks
371 system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks
372 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
373 system.cpu.dcache.replacements 1621273 # number of replacements
374 system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
375 system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks.
376 system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks.
377 system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks.
378 system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
379 system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
380 system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
381 system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
382 system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
383 system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
384 system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits
385 system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits
386 system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits
387 system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits
388 system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits
389 system.cpu.dcache.overall_hits::total 20139960 # number of overall hits
390 system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses
391 system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses
392 system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses
393 system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses
394 system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
395 system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
396 system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
397 system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
398 system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses)
399 system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses)
400 system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
401 system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
402 system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses
403 system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses
404 system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses
405 system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses
406 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
407 system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
408 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
409 system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
410 system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
411 system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
412 system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
413 system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
414 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
415 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
416 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
417 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
418 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
419 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
420 system.cpu.dcache.fast_writes 0 # number of fast writes performed
421 system.cpu.dcache.cache_copies 0 # number of cache copies performed
422 system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks
423 system.cpu.dcache.writebacks::total 1534981 # number of writebacks
424 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
426 ---------- End Simulation Statistics ----------
projects / gem5.git / blob