2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.112155 # Number of seconds simulated
4 sim_ticks 5112155173500 # Number of ticks simulated
5 final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1971048 # Simulator instruction rate (inst/s)
8 host_op_rate 4035436 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 50372945560 # Simulator tick rate (ticks/s)
10 host_mem_usage 594916 # Number of bytes of host memory used
11 host_seconds 101.49 # Real time elapsed on the host
12 sim_insts 200033988 # Number of instructions simulated
13 sim_ops 409540726 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory
25 system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory
27 system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory
31 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory
34 system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s)
54 system.cpu_clk_domain.clock 500 # Clock period in ticks
55 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
56 system.cpu.numCycles 10224314318 # number of cpu cycles simulated
57 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
58 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
59 system.cpu.committedInsts 200033988 # Number of instructions committed
60 system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed
61 system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses
62 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
63 system.cpu.num_func_calls 2308777 # number of times a function call or return occured
64 system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls
65 system.cpu.num_int_insts 374550150 # number of integer instructions
66 system.cpu.num_fp_insts 0 # number of float instructions
67 system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read
68 system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written
69 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
70 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
71 system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read
72 system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written
73 system.cpu.num_mem_refs 35680563 # number of memory refs
74 system.cpu.num_load_insts 27249389 # Number of load instructions
75 system.cpu.num_store_insts 8431174 # Number of store instructions
76 system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles
77 system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles
78 system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles
79 system.cpu.idle_fraction 0.955601 # Percentage of idle cycles
80 system.cpu.Branches 43145769 # Number of branches fetched
81 system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction
82 system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction
83 system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction
84 system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction
85 system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
86 system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
87 system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
88 system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
89 system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
90 system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
91 system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
92 system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
93 system.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction
94 system.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction
95 system.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction
96 system.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction
97 system.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction
98 system.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction
99 system.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction
100 system.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction
101 system.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction
102 system.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction
103 system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
104 system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
105 system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
106 system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
107 system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
108 system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
109 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
110 system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
111 system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction
112 system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction
113 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
114 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
115 system.cpu.op_class::total 409541761 # Class of executed instruction
116 system.cpu.kern.inst.arm 0 # number of arm instructions executed
117 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
118 system.cpu.dcache.tags.replacements 1623441 # number of replacements
119 system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
120 system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks.
121 system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks.
122 system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks.
123 system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
124 system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
125 system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
126 system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
127 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
128 system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
129 system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
130 system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
131 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
132 system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses
133 system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses
134 system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits
135 system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits
136 system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits
137 system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits
138 system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits
139 system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits
140 system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits
141 system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits
142 system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits
143 system.cpu.dcache.overall_hits::total 20190999 # number of overall hits
144 system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses
145 system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses
146 system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses
147 system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses
148 system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses
149 system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses
150 system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses
151 system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses
152 system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses
153 system.cpu.dcache.overall_misses::total 1626230 # number of overall misses
154 system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses)
155 system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses)
156 system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses)
157 system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses)
158 system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses)
159 system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses)
160 system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses
161 system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses
162 system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses
163 system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses
164 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses
165 system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses
166 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses
167 system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses
168 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses
169 system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses
170 system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses
171 system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses
172 system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses
173 system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses
174 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
175 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
176 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
177 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
178 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
179 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
180 system.cpu.dcache.fast_writes 0 # number of fast writes performed
181 system.cpu.dcache.cache_copies 0 # number of cache copies performed
182 system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks
183 system.cpu.dcache.writebacks::total 1536849 # number of writebacks
184 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
185 system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements
186 system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use
187 system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks.
188 system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks.
189 system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks.
190 system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit.
191 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor
192 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
193 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
194 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
195 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
196 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
197 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
198 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
199 system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses
200 system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses
201 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits
202 system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits
203 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits
204 system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits
205 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits
206 system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits
207 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses
208 system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses
209 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses
210 system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses
211 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses
212 system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses
213 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses)
214 system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses)
215 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses
216 system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses
217 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses
218 system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses
219 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses
220 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses
221 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses
222 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses
223 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses
224 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses
225 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
226 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
227 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
228 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
229 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
230 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
231 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
232 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
233 system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks
234 system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks
235 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
236 system.cpu.icache.tags.replacements 791952 # number of replacements
237 system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use
238 system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks.
239 system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks.
240 system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks.
241 system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit.
242 system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor
243 system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
244 system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
245 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
246 system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
247 system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
248 system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
249 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
250 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
251 system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses
252 system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses
253 system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits
254 system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits
255 system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits
256 system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits
257 system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits
258 system.cpu.icache.overall_hits::total 243645979 # number of overall hits
259 system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses
260 system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses
261 system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses
262 system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses
263 system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses
264 system.cpu.icache.overall_misses::total 792471 # number of overall misses
265 system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses)
266 system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses)
267 system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses
268 system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses
269 system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses
270 system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses
271 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses
272 system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses
273 system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses
274 system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses
275 system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses
276 system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses
277 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
278 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
279 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
280 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
281 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
282 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
283 system.cpu.icache.fast_writes 0 # number of fast writes performed
284 system.cpu.icache.cache_copies 0 # number of cache copies performed
285 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
286 system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
287 system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use
288 system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
289 system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
290 system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
291 system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit.
292 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor
293 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
294 system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
295 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
296 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
297 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
298 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
299 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
300 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
301 system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses
302 system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses
303 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits
304 system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits
305 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
306 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
307 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits
308 system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits
309 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits
310 system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits
311 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses
312 system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses
313 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses
314 system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses
315 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses
316 system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses
317 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses)
318 system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses)
319 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
320 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
321 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses
322 system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses
323 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses
324 system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses
325 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses
326 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses
327 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses
328 system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses
329 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses
330 system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses
331 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
332 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
333 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
334 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
335 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
336 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
337 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
338 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
339 system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
340 system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
341 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
342 system.cpu.l2cache.tags.replacements 106197 # number of replacements
343 system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use
344 system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks.
345 system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks.
346 system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks.
347 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
348 system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor
349 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
350 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor
351 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor
352 system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor
353 system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy
354 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
355 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
356 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy
357 system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy
358 system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy
359 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id
360 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
361 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
362 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id
363 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
364 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
365 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
366 system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses
367 system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses
368 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits
369 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
370 system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits
371 system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits
372 system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits
373 system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits
374 system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits
375 system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
376 system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
377 system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits
378 system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits
379 system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits
380 system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
381 system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits
382 system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits
383 system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits
384 system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits
385 system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
386 system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits
387 system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits
388 system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits
389 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
390 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
391 system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses
392 system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses
393 system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses
394 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses
395 system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
396 system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses
397 system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses
398 system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
399 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
400 system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses
401 system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses
402 system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses
403 system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
404 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
405 system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses
406 system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses
407 system.cpu.l2cache.overall_misses::total 180453 # number of overall misses
408 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses)
409 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
410 system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses)
411 system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses)
412 system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses)
413 system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses)
414 system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses)
415 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses)
416 system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
417 system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses)
418 system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses)
419 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses
420 system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
421 system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses
422 system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses
423 system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses
424 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses
425 system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
426 system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses
427 system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses
428 system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses
429 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
430 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
431 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses
432 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses
433 system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses
434 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses
435 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses
436 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses
437 system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses
438 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
439 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
440 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses
441 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses
442 system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses
443 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
444 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
445 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses
446 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses
447 system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses
448 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
449 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
450 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
451 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
452 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
453 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
454 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
455 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
456 system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks
457 system.cpu.l2cache.writebacks::total 98349 # number of writebacks
458 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
459 system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution
460 system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution
461 system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution
462 system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution
463 system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution
464 system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution
465 system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution
466 system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution
467 system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution
468 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes)
469 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes)
470 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
471 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes)
472 system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes)
473 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes)
474 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes)
475 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
476 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes)
477 system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes)
478 system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
479 system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram
482 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
483 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
484 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
485 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
486 system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram
487 system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
488 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
489 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
490 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
491 system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram
492 system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution
493 system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution
494 system.iobus.trans_dist::WriteReq 57692 # Transaction distribution
495 system.iobus.trans_dist::WriteResp 10972 # Transaction distribution
496 system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
497 system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
498 system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
499 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
500 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
501 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
502 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
503 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
504 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
505 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
506 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
507 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes)
508 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
509 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
510 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
511 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes)
512 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
513 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
514 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
515 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
516 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
517 system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes)
518 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes)
519 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes)
520 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
521 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
522 system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes)
523 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
524 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
525 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
526 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
527 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
528 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
529 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
530 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
531 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes)
532 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
533 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
534 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
535 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes)
536 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
537 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
538 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
539 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
540 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
541 system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes)
542 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes)
543 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes)
544 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
545 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
546 system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes)
547 system.iocache.tags.replacements 47573 # number of replacements
548 system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
549 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
550 system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
551 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
552 system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit.
553 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
554 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
555 system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
556 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
557 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
558 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
559 system.iocache.tags.tag_accesses 428652 # Number of tag accesses
560 system.iocache.tags.data_accesses 428652 # Number of data accesses
561 system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
562 system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
563 system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
564 system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
565 system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
566 system.iocache.demand_misses::total 908 # number of demand (read+write) misses
567 system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
568 system.iocache.overall_misses::total 908 # number of overall misses
569 system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses)
570 system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
571 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
572 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
573 system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses
574 system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses
575 system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses
576 system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
577 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
578 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
579 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
580 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
581 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
582 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
583 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
584 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
585 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
586 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
587 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
588 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
589 system.iocache.fast_writes 46720 # number of fast writes performed
590 system.iocache.cache_copies 0 # number of cache copies performed
591 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
592 system.membus.trans_dist::ReadReq 13903768 # Transaction distribution
593 system.membus.trans_dist::ReadResp 13903768 # Transaction distribution
594 system.membus.trans_dist::WriteReq 13911 # Transaction distribution
595 system.membus.trans_dist::WriteResp 13911 # Transaction distribution
596 system.membus.trans_dist::Writeback 98349 # Transaction distribution
597 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
598 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
599 system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution
600 system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution
601 system.membus.trans_dist::ReadExReq 134620 # Transaction distribution
602 system.membus.trans_dist::ReadExResp 134615 # Transaction distribution
603 system.membus.trans_dist::MessageReq 1696 # Transaction distribution
604 system.membus.trans_dist::MessageResp 1696 # Transaction distribution
605 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
606 system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
607 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes)
608 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
609 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes)
610 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes)
611 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
612 system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
613 system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes)
614 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
615 system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
616 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes)
617 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
618 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes)
619 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes)
620 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
621 system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
622 system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes)
623 system.membus.snoops 0 # Total snoops (count)
624 system.membus.snoop_fanout::samples 328677 # Request fanout histogram
625 system.membus.snoop_fanout::mean 1 # Request fanout histogram
626 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
627 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
628 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
629 system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram
630 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
631 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
632 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
633 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
634 system.membus.snoop_fanout::total 328677 # Request fanout histogram
635 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
636 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
637 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
638 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
639 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
640 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
641 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
642 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
643 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
644 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
645 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
646 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
648 ---------- End Simulation Statistics ----------
projects / gem5.git / blob