2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.112043 # Number of seconds simulated
4 sim_ticks 5112043255000 # Number of ticks simulated
5 final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1772716 # Simulator instruction rate (inst/s)
8 host_op_rate 3629762 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 45353186641 # Simulator tick rate (ticks/s)
10 host_mem_usage 350348 # Number of bytes of host memory used
11 host_seconds 112.72 # Real time elapsed on the host
12 sim_insts 199813913 # Number of instructions simulated
13 sim_ops 409133277 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 15568704 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 12232896 # Number of bytes written to this memory
17 system.physmem.num_reads 243261 # Number of read requests responded to by this memory
18 system.physmem.num_writes 191139 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s)
24 system.l2c.replacements 164044 # number of replacements
25 system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
26 system.l2c.total_refs 3332458 # Total number of references to valid blocks.
27 system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
28 system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
29 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
30 system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
31 system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
32 system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
33 system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
34 system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
35 system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
36 system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
37 system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
38 system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
39 system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
40 system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
41 system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
42 system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
43 system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
44 system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
45 system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
46 system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
47 system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
48 system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
49 system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
50 system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
51 system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
52 system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
53 system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
54 system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
55 system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
56 system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
57 system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
58 system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
59 system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
60 system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
61 system.l2c.overall_hits::total 2221403 # number of overall hits
62 system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
63 system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
64 system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
65 system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
66 system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
67 system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
68 system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
69 system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
70 system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
71 system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
72 system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
73 system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
74 system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
75 system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
76 system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
77 system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
78 system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
79 system.l2c.overall_misses::cpu.data 185411 # number of overall misses
80 system.l2c.overall_misses::total 200638 # number of overall misses
81 system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
82 system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
83 system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
84 system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
85 system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
86 system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
87 system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
88 system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
89 system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
90 system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
91 system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
92 system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
93 system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
94 system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
95 system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
96 system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
97 system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
98 system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
99 system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
100 system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
101 system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
102 system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
103 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
104 system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
105 system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
106 system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
107 system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
108 system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
109 system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
110 system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
111 system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
112 system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
113 system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
114 system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
115 system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
116 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
117 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
118 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
119 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
120 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
121 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
122 system.l2c.fast_writes 0 # number of fast writes performed
123 system.l2c.cache_copies 0 # number of cache copies performed
124 system.l2c.writebacks::writebacks 144472 # number of writebacks
125 system.l2c.writebacks::total 144472 # number of writebacks
126 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
127 system.iocache.replacements 47570 # number of replacements
128 system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
129 system.iocache.total_refs 0 # Total number of references to valid blocks.
130 system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
131 system.iocache.avg_refs 0 # Average number of references to valid blocks.
132 system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
133 system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
134 system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
135 system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
136 system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
137 system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
138 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
139 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
140 system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
141 system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
142 system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
143 system.iocache.overall_misses::total 47625 # number of overall misses
144 system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
145 system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
146 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
147 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
148 system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
149 system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
150 system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
151 system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
152 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
153 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
154 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
155 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
156 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
157 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
158 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
159 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
160 system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
161 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
162 system.iocache.fast_writes 0 # number of fast writes performed
163 system.iocache.cache_copies 0 # number of cache copies performed
164 system.iocache.writebacks::writebacks 46667 # number of writebacks
165 system.iocache.writebacks::total 46667 # number of writebacks
166 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
167 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
168 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
169 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
170 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
171 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
172 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
173 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
174 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
175 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
176 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
177 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
178 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
179 system.cpu.numCycles 10224086531 # number of cpu cycles simulated
180 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
181 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
182 system.cpu.committedInsts 199813913 # Number of instructions committed
183 system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed
184 system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
185 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
186 system.cpu.num_func_calls 0 # number of times a function call or return occured
187 system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
188 system.cpu.num_int_insts 374297244 # number of integer instructions
189 system.cpu.num_fp_insts 0 # number of float instructions
190 system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
191 system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
192 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
193 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
194 system.cpu.num_mem_refs 35626519 # number of memory refs
195 system.cpu.num_load_insts 27217784 # Number of load instructions
196 system.cpu.num_store_insts 8408735 # Number of store instructions
197 system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
198 system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
199 system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
200 system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
201 system.cpu.kern.inst.arm 0 # number of arm instructions executed
202 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
203 system.cpu.icache.replacements 790795 # number of replacements
204 system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
205 system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
206 system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
207 system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
208 system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
209 system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
210 system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
211 system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
212 system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
213 system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
214 system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
215 system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
216 system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
217 system.cpu.icache.overall_hits::total 243365777 # number of overall hits
218 system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses
219 system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
220 system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses
221 system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
222 system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses
223 system.cpu.icache.overall_misses::total 791314 # number of overall misses
224 system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
225 system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
226 system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
227 system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
228 system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
229 system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
230 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
231 system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
232 system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
233 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
234 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
235 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
236 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
237 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
238 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
239 system.cpu.icache.fast_writes 0 # number of fast writes performed
240 system.cpu.icache.cache_copies 0 # number of cache copies performed
241 system.cpu.icache.writebacks::writebacks 809 # number of writebacks
242 system.cpu.icache.writebacks::total 809 # number of writebacks
243 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
244 system.cpu.itb_walker_cache.replacements 3435 # number of replacements
245 system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
246 system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
247 system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
248 system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
249 system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
250 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor
251 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy
252 system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy
253 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits
254 system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
255 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
256 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
257 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits
258 system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
259 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits
260 system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
261 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses
262 system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
263 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses
264 system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
265 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses
266 system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
267 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
268 system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
269 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
270 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
271 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
272 system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
273 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
274 system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
275 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses
276 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses
277 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses
278 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
279 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
280 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
281 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
282 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
283 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
284 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
285 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
286 system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks
287 system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks
288 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
289 system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
290 system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
291 system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
292 system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
293 system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
294 system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
295 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
296 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
297 system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
298 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
299 system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
300 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
301 system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
302 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
303 system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
304 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
305 system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
306 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
307 system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
308 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
309 system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
310 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
311 system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
312 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
313 system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
314 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
315 system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
316 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
317 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
318 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
319 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
320 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
321 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
322 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
323 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
324 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
325 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
326 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
327 system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
328 system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
329 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
330 system.cpu.dcache.replacements 1621277 # number of replacements
331 system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
332 system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
333 system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
334 system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
335 system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
336 system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
337 system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
338 system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
339 system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
340 system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
341 system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
342 system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
343 system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
344 system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
345 system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
346 system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
347 system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
348 system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
349 system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
350 system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
351 system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
352 system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
353 system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
354 system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
355 system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
356 system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
357 system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
358 system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
359 system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
360 system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
361 system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
362 system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
363 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
364 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
365 system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
366 system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
367 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
368 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
369 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
370 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
371 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
372 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
373 system.cpu.dcache.fast_writes 0 # number of fast writes performed
374 system.cpu.dcache.cache_copies 0 # number of cache copies performed
375 system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
376 system.cpu.dcache.writebacks::total 1525559 # number of writebacks
377 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
379 ---------- End Simulation Statistics ----------
projects / gem5.git / blob