2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.195162 # Number of seconds simulated
4 sim_ticks 5195162021000 # Number of ticks simulated
5 final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 434432 # Simulator instruction rate (inst/s)
8 host_op_rate 837466 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 17594801878 # Simulator tick rate (ticks/s)
10 host_mem_usage 611684 # Number of bytes of host memory used
11 host_seconds 295.27 # Real time elapsed on the host
12 sim_insts 128273373 # Number of instructions simulated
13 sim_ops 247275988 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.readReqs 198400 # Total number of read requests seen
50 system.physmem.writeReqs 126924 # Total number of write requests seen
51 system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady
52 system.physmem.bytesRead 12697600 # Total number of bytes read from memory
53 system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
54 system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
55 system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
56 system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
57 system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
58 system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis
74 system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
90 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
91 system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
92 system.physmem.totGap 5195161957500 # Total gap between requests
93 system.physmem.readPktSize::0 0 # Categorize read packet sizes
94 system.physmem.readPktSize::1 0 # Categorize read packet sizes
95 system.physmem.readPktSize::2 0 # Categorize read packet sizes
96 system.physmem.readPktSize::3 0 # Categorize read packet sizes
97 system.physmem.readPktSize::4 0 # Categorize read packet sizes
98 system.physmem.readPktSize::5 0 # Categorize read packet sizes
99 system.physmem.readPktSize::6 198400 # Categorize read packet sizes
100 system.physmem.writePktSize::0 0 # Categorize write packet sizes
101 system.physmem.writePktSize::1 0 # Categorize write packet sizes
102 system.physmem.writePktSize::2 0 # Categorize write packet sizes
103 system.physmem.writePktSize::3 0 # Categorize write packet sizes
104 system.physmem.writePktSize::4 0 # Categorize write packet sizes
105 system.physmem.writePktSize::5 0 # Categorize write packet sizes
106 system.physmem.writePktSize::6 126924 # Categorize write packet sizes
107 system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
139 system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
171 system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays
172 system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests
173 system.physmem.totBusLat 991715000 # Total cycles spent in databus access
174 system.physmem.totBankLat 2804628750 # Total cycles spent in bank access
175 system.physmem.avgQLat 20766.54 # Average queueing delay per request
176 system.physmem.avgBankLat 14140.30 # Average bank access latency per request
177 system.physmem.avgBusLat 5000.00 # Average bus latency per request
178 system.physmem.avgMemAccLat 39906.83 # Average memory access latency
179 system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
180 system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
181 system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
182 system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
183 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
184 system.physmem.busUtil 0.03 # Data bus utilization in percentage
185 system.physmem.avgRdQLen 0.00 # Average read queue length over time
186 system.physmem.avgWrQLen 12.66 # Average write queue length over time
187 system.physmem.readRowHits 175593 # Number of row buffer hits during reads
188 system.physmem.writeRowHits 94810 # Number of row buffer hits during writes
189 system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
190 system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
191 system.physmem.avgGap 15969193.66 # Average gap between requests
192 system.iocache.replacements 47509 # number of replacements
193 system.iocache.tagsinuse 0.124742 # Cycle average of tags in use
194 system.iocache.total_refs 0 # Total number of references to valid blocks.
195 system.iocache.sampled_refs 47525 # Sample count of references to valid blocks.
196 system.iocache.avg_refs 0 # Average number of references to valid blocks.
197 system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit.
198 system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor
199 system.iocache.occ_percent::pc.south_bridge.ide 0.007796 # Average percentage of cache occupancy
200 system.iocache.occ_percent::total 0.007796 # Average percentage of cache occupancy
201 system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
202 system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
203 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
204 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
205 system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses
206 system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
207 system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
208 system.iocache.overall_misses::total 47564 # number of overall misses
209 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles
210 system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles
211 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732360679 # number of WriteReq miss cycles
212 system.iocache.WriteReq_miss_latency::total 10732360679 # number of WriteReq miss cycles
213 system.iocache.demand_miss_latency::pc.south_bridge.ide 10870347076 # number of demand (read+write) miss cycles
214 system.iocache.demand_miss_latency::total 10870347076 # number of demand (read+write) miss cycles
215 system.iocache.overall_miss_latency::pc.south_bridge.ide 10870347076 # number of overall miss cycles
216 system.iocache.overall_miss_latency::total 10870347076 # number of overall miss cycles
217 system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
218 system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
219 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
220 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
221 system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
222 system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
223 system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses
224 system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
225 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
226 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
227 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
228 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
229 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
230 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
231 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
232 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
233 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency
234 system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency
235 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.624122 # average WriteReq miss latency
236 system.iocache.WriteReq_avg_miss_latency::total 229716.624122 # average WriteReq miss latency
237 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency
238 system.iocache.demand_avg_miss_latency::total 228541.482550 # average overall miss latency
239 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency
240 system.iocache.overall_avg_miss_latency::total 228541.482550 # average overall miss latency
241 system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked
242 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
243 system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked
244 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
245 system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked
246 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
247 system.iocache.fast_writes 0 # number of fast writes performed
248 system.iocache.cache_copies 0 # number of cache copies performed
249 system.iocache.writebacks::writebacks 46667 # number of writebacks
250 system.iocache.writebacks::total 46667 # number of writebacks
251 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
252 system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
253 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
254 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
255 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses
256 system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
257 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
258 system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
259 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles
260 system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles
261 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301562585 # number of WriteReq MSHR miss cycles
262 system.iocache.WriteReq_mshr_miss_latency::total 8301562585 # number of WriteReq MSHR miss cycles
263 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of demand (read+write) MSHR miss cycles
264 system.iocache.demand_mshr_miss_latency::total 8395640012 # number of demand (read+write) MSHR miss cycles
265 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of overall MSHR miss cycles
266 system.iocache.overall_mshr_miss_latency::total 8395640012 # number of overall MSHR miss cycles
267 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
268 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
269 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
270 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
271 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
272 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
273 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
274 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
275 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency
276 system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency
277 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.555330 # average WriteReq mshr miss latency
278 system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.555330 # average WriteReq mshr miss latency
279 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency
280 system.iocache.demand_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency
281 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency
282 system.iocache.overall_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency
283 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
284 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
285 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
286 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
287 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
288 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
289 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
290 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
291 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
292 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
293 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
294 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
295 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
296 system.cpu.numCycles 10390324042 # number of cpu cycles simulated
297 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
298 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
299 system.cpu.committedInsts 128273373 # Number of instructions committed
300 system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed
301 system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses
302 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
303 system.cpu.num_func_calls 0 # number of times a function call or return occured
304 system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls
305 system.cpu.num_int_insts 232011695 # number of integer instructions
306 system.cpu.num_fp_insts 0 # number of float instructions
307 system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read
308 system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written
309 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
310 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
311 system.cpu.num_mem_refs 22232145 # number of memory refs
312 system.cpu.num_load_insts 13871789 # Number of load instructions
313 system.cpu.num_store_insts 8360356 # Number of store instructions
314 system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles
315 system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles
316 system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles
317 system.cpu.idle_fraction 0.942190 # Percentage of idle cycles
318 system.cpu.kern.inst.arm 0 # number of arm instructions executed
319 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
320 system.cpu.icache.replacements 791527 # number of replacements
321 system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use
322 system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks.
323 system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks.
324 system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks.
325 system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit.
326 system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor
327 system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
328 system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
329 system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits
330 system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits
331 system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits
332 system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits
333 system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits
334 system.cpu.icache.overall_hits::total 144497724 # number of overall hits
335 system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses
336 system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses
337 system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses
338 system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses
339 system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses
340 system.cpu.icache.overall_misses::total 792046 # number of overall misses
341 system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles
342 system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles
343 system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles
344 system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles
345 system.cpu.icache.overall_miss_latency::cpu.inst 10958971500 # number of overall miss cycles
346 system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles
347 system.cpu.icache.ReadReq_accesses::cpu.inst 145289770 # number of ReadReq accesses(hits+misses)
348 system.cpu.icache.ReadReq_accesses::total 145289770 # number of ReadReq accesses(hits+misses)
349 system.cpu.icache.demand_accesses::cpu.inst 145289770 # number of demand (read+write) accesses
350 system.cpu.icache.demand_accesses::total 145289770 # number of demand (read+write) accesses
351 system.cpu.icache.overall_accesses::cpu.inst 145289770 # number of overall (read+write) accesses
352 system.cpu.icache.overall_accesses::total 145289770 # number of overall (read+write) accesses
353 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses
354 system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses
355 system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses
356 system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses
357 system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses
358 system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses
359 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency
360 system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency
361 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
362 system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency
363 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
364 system.cpu.icache.overall_avg_miss_latency::total 13836.281605 # average overall miss latency
365 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
366 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
367 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
368 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
369 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
370 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
371 system.cpu.icache.fast_writes 0 # number of fast writes performed
372 system.cpu.icache.cache_copies 0 # number of cache copies performed
373 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792046 # number of ReadReq MSHR misses
374 system.cpu.icache.ReadReq_mshr_misses::total 792046 # number of ReadReq MSHR misses
375 system.cpu.icache.demand_mshr_misses::cpu.inst 792046 # number of demand (read+write) MSHR misses
376 system.cpu.icache.demand_mshr_misses::total 792046 # number of demand (read+write) MSHR misses
377 system.cpu.icache.overall_mshr_misses::cpu.inst 792046 # number of overall MSHR misses
378 system.cpu.icache.overall_mshr_misses::total 792046 # number of overall MSHR misses
379 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9374879500 # number of ReadReq MSHR miss cycles
380 system.cpu.icache.ReadReq_mshr_miss_latency::total 9374879500 # number of ReadReq MSHR miss cycles
381 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9374879500 # number of demand (read+write) MSHR miss cycles
382 system.cpu.icache.demand_mshr_miss_latency::total 9374879500 # number of demand (read+write) MSHR miss cycles
383 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9374879500 # number of overall MSHR miss cycles
384 system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles
385 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses
386 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses
387 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses
388 system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses
389 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses
390 system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses
391 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11836.281605 # average ReadReq mshr miss latency
392 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11836.281605 # average ReadReq mshr miss latency
393 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
394 system.cpu.icache.demand_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
395 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
396 system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
397 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
398 system.cpu.itb_walker_cache.replacements 3425 # number of replacements
399 system.cpu.itb_walker_cache.tagsinuse 3.077880 # Cycle average of tags in use
400 system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks.
401 system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks.
402 system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks.
403 system.cpu.itb_walker_cache.warmup_cycle 5164120857000 # Cycle when the warmup percentage was hit.
404 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077880 # Average occupied blocks per requestor
405 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192367 # Average percentage of cache occupancy
406 system.cpu.itb_walker_cache.occ_percent::total 0.192367 # Average percentage of cache occupancy
407 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits
408 system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits
409 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
410 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
411 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8006 # number of demand (read+write) hits
412 system.cpu.itb_walker_cache.demand_hits::total 8006 # number of demand (read+write) hits
413 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8006 # number of overall hits
414 system.cpu.itb_walker_cache.overall_hits::total 8006 # number of overall hits
415 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4287 # number of ReadReq misses
416 system.cpu.itb_walker_cache.ReadReq_misses::total 4287 # number of ReadReq misses
417 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4287 # number of demand (read+write) misses
418 system.cpu.itb_walker_cache.demand_misses::total 4287 # number of demand (read+write) misses
419 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4287 # number of overall misses
420 system.cpu.itb_walker_cache.overall_misses::total 4287 # number of overall misses
421 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42274000 # number of ReadReq miss cycles
422 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42274000 # number of ReadReq miss cycles
423 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42274000 # number of demand (read+write) miss cycles
424 system.cpu.itb_walker_cache.demand_miss_latency::total 42274000 # number of demand (read+write) miss cycles
425 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42274000 # number of overall miss cycles
426 system.cpu.itb_walker_cache.overall_miss_latency::total 42274000 # number of overall miss cycles
427 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12291 # number of ReadReq accesses(hits+misses)
428 system.cpu.itb_walker_cache.ReadReq_accesses::total 12291 # number of ReadReq accesses(hits+misses)
429 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
430 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
431 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12293 # number of demand (read+write) accesses
432 system.cpu.itb_walker_cache.demand_accesses::total 12293 # number of demand (read+write) accesses
433 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12293 # number of overall (read+write) accesses
434 system.cpu.itb_walker_cache.overall_accesses::total 12293 # number of overall (read+write) accesses
435 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.348792 # miss rate for ReadReq accesses
436 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.348792 # miss rate for ReadReq accesses
437 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.348735 # miss rate for demand accesses
438 system.cpu.itb_walker_cache.demand_miss_rate::total 0.348735 # miss rate for demand accesses
439 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.348735 # miss rate for overall accesses
440 system.cpu.itb_walker_cache.overall_miss_rate::total 0.348735 # miss rate for overall accesses
441 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9860.975041 # average ReadReq miss latency
442 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9860.975041 # average ReadReq miss latency
443 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency
444 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9860.975041 # average overall miss latency
445 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency
446 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9860.975041 # average overall miss latency
447 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
448 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
449 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
450 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
451 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
452 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
453 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
454 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
455 system.cpu.itb_walker_cache.writebacks::writebacks 641 # number of writebacks
456 system.cpu.itb_walker_cache.writebacks::total 641 # number of writebacks
457 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4287 # number of ReadReq MSHR misses
458 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4287 # number of ReadReq MSHR misses
459 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4287 # number of demand (read+write) MSHR misses
460 system.cpu.itb_walker_cache.demand_mshr_misses::total 4287 # number of demand (read+write) MSHR misses
461 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4287 # number of overall MSHR misses
462 system.cpu.itb_walker_cache.overall_mshr_misses::total 4287 # number of overall MSHR misses
463 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33700000 # number of ReadReq MSHR miss cycles
464 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33700000 # number of ReadReq MSHR miss cycles
465 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33700000 # number of demand (read+write) MSHR miss cycles
466 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33700000 # number of demand (read+write) MSHR miss cycles
467 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33700000 # number of overall MSHR miss cycles
468 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33700000 # number of overall MSHR miss cycles
469 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.348792 # mshr miss rate for ReadReq accesses
470 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.348792 # mshr miss rate for ReadReq accesses
471 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for demand accesses
472 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.348735 # mshr miss rate for demand accesses
473 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for overall accesses
474 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses
475 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency
476 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency
477 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
478 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
479 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
480 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
481 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
482 system.cpu.dtb_walker_cache.replacements 7539 # number of replacements
483 system.cpu.dtb_walker_cache.tagsinuse 5.062514 # Cycle average of tags in use
484 system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks.
485 system.cpu.dtb_walker_cache.sampled_refs 7553 # Sample count of references to valid blocks.
486 system.cpu.dtb_walker_cache.avg_refs 1.744737 # Average number of references to valid blocks.
487 system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit.
488 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062514 # Average occupied blocks per requestor
489 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy
490 system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy
491 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits
492 system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits
493 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13180 # number of demand (read+write) hits
494 system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits
495 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits
496 system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits
497 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8726 # number of ReadReq misses
498 system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses
499 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8726 # number of demand (read+write) misses
500 system.cpu.dtb_walker_cache.demand_misses::total 8726 # number of demand (read+write) misses
501 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8726 # number of overall misses
502 system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses
503 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92094500 # number of ReadReq miss cycles
504 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92094500 # number of ReadReq miss cycles
505 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92094500 # number of demand (read+write) miss cycles
506 system.cpu.dtb_walker_cache.demand_miss_latency::total 92094500 # number of demand (read+write) miss cycles
507 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92094500 # number of overall miss cycles
508 system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles
509 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses)
510 system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses)
511 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses
512 system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses
513 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses
514 system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses
515 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses
516 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398338 # miss rate for ReadReq accesses
517 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398338 # miss rate for demand accesses
518 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398338 # miss rate for demand accesses
519 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398338 # miss rate for overall accesses
520 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398338 # miss rate for overall accesses
521 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922 # average ReadReq miss latency
522 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency
523 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
524 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency
525 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
526 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency
527 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
528 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
529 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
530 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
531 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
532 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
533 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
534 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
535 system.cpu.dtb_walker_cache.writebacks::writebacks 2713 # number of writebacks
536 system.cpu.dtb_walker_cache.writebacks::total 2713 # number of writebacks
537 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8726 # number of ReadReq MSHR misses
538 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8726 # number of ReadReq MSHR misses
539 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8726 # number of demand (read+write) MSHR misses
540 system.cpu.dtb_walker_cache.demand_mshr_misses::total 8726 # number of demand (read+write) MSHR misses
541 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8726 # number of overall MSHR misses
542 system.cpu.dtb_walker_cache.overall_mshr_misses::total 8726 # number of overall MSHR misses
543 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74642500 # number of ReadReq MSHR miss cycles
544 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74642500 # number of ReadReq MSHR miss cycles
545 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74642500 # number of demand (read+write) MSHR miss cycles
546 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74642500 # number of demand (read+write) MSHR miss cycles
547 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles
548 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74642500 # number of overall MSHR miss cycles
549 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for ReadReq accesses
550 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398338 # mshr miss rate for ReadReq accesses
551 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for demand accesses
552 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398338 # mshr miss rate for demand accesses
553 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for overall accesses
554 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398338 # mshr miss rate for overall accesses
555 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average ReadReq mshr miss latency
556 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8554.033922 # average ReadReq mshr miss latency
557 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
558 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
559 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
560 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
561 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
562 system.cpu.dcache.replacements 1618797 # number of replacements
563 system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use
564 system.cpu.dcache.total_refs 20025896 # Total number of references to valid blocks.
565 system.cpu.dcache.sampled_refs 1619309 # Sample count of references to valid blocks.
566 system.cpu.dcache.avg_refs 12.366939 # Average number of references to valid blocks.
567 system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
568 system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor
569 system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
570 system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
571 system.cpu.dcache.ReadReq_hits::cpu.data 11988260 # number of ReadReq hits
572 system.cpu.dcache.ReadReq_hits::total 11988260 # number of ReadReq hits
573 system.cpu.dcache.WriteReq_hits::cpu.data 8035474 # number of WriteReq hits
574 system.cpu.dcache.WriteReq_hits::total 8035474 # number of WriteReq hits
575 system.cpu.dcache.demand_hits::cpu.data 20023734 # number of demand (read+write) hits
576 system.cpu.dcache.demand_hits::total 20023734 # number of demand (read+write) hits
577 system.cpu.dcache.overall_hits::cpu.data 20023734 # number of overall hits
578 system.cpu.dcache.overall_hits::total 20023734 # number of overall hits
579 system.cpu.dcache.ReadReq_misses::cpu.data 1306617 # number of ReadReq misses
580 system.cpu.dcache.ReadReq_misses::total 1306617 # number of ReadReq misses
581 system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses
582 system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses
583 system.cpu.dcache.demand_misses::cpu.data 1621505 # number of demand (read+write) misses
584 system.cpu.dcache.demand_misses::total 1621505 # number of demand (read+write) misses
585 system.cpu.dcache.overall_misses::cpu.data 1621505 # number of overall misses
586 system.cpu.dcache.overall_misses::total 1621505 # number of overall misses
587 system.cpu.dcache.ReadReq_miss_latency::cpu.data 18345510500 # number of ReadReq miss cycles
588 system.cpu.dcache.ReadReq_miss_latency::total 18345510500 # number of ReadReq miss cycles
589 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8557598000 # number of WriteReq miss cycles
590 system.cpu.dcache.WriteReq_miss_latency::total 8557598000 # number of WriteReq miss cycles
591 system.cpu.dcache.demand_miss_latency::cpu.data 26903108500 # number of demand (read+write) miss cycles
592 system.cpu.dcache.demand_miss_latency::total 26903108500 # number of demand (read+write) miss cycles
593 system.cpu.dcache.overall_miss_latency::cpu.data 26903108500 # number of overall miss cycles
594 system.cpu.dcache.overall_miss_latency::total 26903108500 # number of overall miss cycles
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596 system.cpu.dcache.ReadReq_accesses::total 13294877 # number of ReadReq accesses(hits+misses)
597 system.cpu.dcache.WriteReq_accesses::cpu.data 8350362 # number of WriteReq accesses(hits+misses)
598 system.cpu.dcache.WriteReq_accesses::total 8350362 # number of WriteReq accesses(hits+misses)
599 system.cpu.dcache.demand_accesses::cpu.data 21645239 # number of demand (read+write) accesses
600 system.cpu.dcache.demand_accesses::total 21645239 # number of demand (read+write) accesses
601 system.cpu.dcache.overall_accesses::cpu.data 21645239 # number of overall (read+write) accesses
602 system.cpu.dcache.overall_accesses::total 21645239 # number of overall (read+write) accesses
603 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098280 # miss rate for ReadReq accesses
604 system.cpu.dcache.ReadReq_miss_rate::total 0.098280 # miss rate for ReadReq accesses
605 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses
606 system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses
607 system.cpu.dcache.demand_miss_rate::cpu.data 0.074913 # miss rate for demand accesses
608 system.cpu.dcache.demand_miss_rate::total 0.074913 # miss rate for demand accesses
609 system.cpu.dcache.overall_miss_rate::cpu.data 0.074913 # miss rate for overall accesses
610 system.cpu.dcache.overall_miss_rate::total 0.074913 # miss rate for overall accesses
611 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14040.465186 # average ReadReq miss latency
612 system.cpu.dcache.ReadReq_avg_miss_latency::total 14040.465186 # average ReadReq miss latency
613 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27176.640583 # average WriteReq miss latency
614 system.cpu.dcache.WriteReq_avg_miss_latency::total 27176.640583 # average WriteReq miss latency
615 system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency
616 system.cpu.dcache.demand_avg_miss_latency::total 16591.443443 # average overall miss latency
617 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency
618 system.cpu.dcache.overall_avg_miss_latency::total 16591.443443 # average overall miss latency
619 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
620 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
621 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
622 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
623 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
624 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
625 system.cpu.dcache.fast_writes 0 # number of fast writes performed
626 system.cpu.dcache.cache_copies 0 # number of cache copies performed
627 system.cpu.dcache.writebacks::writebacks 1536058 # number of writebacks
628 system.cpu.dcache.writebacks::total 1536058 # number of writebacks
629 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306617 # number of ReadReq MSHR misses
630 system.cpu.dcache.ReadReq_mshr_misses::total 1306617 # number of ReadReq MSHR misses
631 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses
632 system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses
633 system.cpu.dcache.demand_mshr_misses::cpu.data 1621505 # number of demand (read+write) MSHR misses
634 system.cpu.dcache.demand_mshr_misses::total 1621505 # number of demand (read+write) MSHR misses
635 system.cpu.dcache.overall_mshr_misses::cpu.data 1621505 # number of overall MSHR misses
636 system.cpu.dcache.overall_mshr_misses::total 1621505 # number of overall MSHR misses
637 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15732276500 # number of ReadReq MSHR miss cycles
638 system.cpu.dcache.ReadReq_mshr_miss_latency::total 15732276500 # number of ReadReq MSHR miss cycles
639 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7927822000 # number of WriteReq MSHR miss cycles
640 system.cpu.dcache.WriteReq_mshr_miss_latency::total 7927822000 # number of WriteReq MSHR miss cycles
641 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23660098500 # number of demand (read+write) MSHR miss cycles
642 system.cpu.dcache.demand_mshr_miss_latency::total 23660098500 # number of demand (read+write) MSHR miss cycles
643 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23660098500 # number of overall MSHR miss cycles
644 system.cpu.dcache.overall_mshr_miss_latency::total 23660098500 # number of overall MSHR miss cycles
645 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles
646 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles
647 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467833000 # number of WriteReq MSHR uncacheable cycles
648 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467833000 # number of WriteReq MSHR uncacheable cycles
649 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613782000 # number of overall MSHR uncacheable cycles
650 system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613782000 # number of overall MSHR uncacheable cycles
651 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098280 # mshr miss rate for ReadReq accesses
652 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098280 # mshr miss rate for ReadReq accesses
653 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses
654 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses
655 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for demand accesses
656 system.cpu.dcache.demand_mshr_miss_rate::total 0.074913 # mshr miss rate for demand accesses
657 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for overall accesses
658 system.cpu.dcache.overall_mshr_miss_rate::total 0.074913 # mshr miss rate for overall accesses
659 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12040.465186 # average ReadReq mshr miss latency
660 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12040.465186 # average ReadReq mshr miss latency
661 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25176.640583 # average WriteReq mshr miss latency
662 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25176.640583 # average WriteReq mshr miss latency
663 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency
664 system.cpu.dcache.demand_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency
665 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency
666 system.cpu.dcache.overall_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency
667 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
668 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
669 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
670 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
671 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
672 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
673 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
674 system.cpu.l2cache.replacements 86864 # number of replacements
675 system.cpu.l2cache.tagsinuse 64770.428854 # Cycle average of tags in use
676 system.cpu.l2cache.total_refs 3484759 # Total number of references to valid blocks.
677 system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks.
678 system.cpu.l2cache.avg_refs 22.981837 # Average number of references to valid blocks.
679 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
680 system.cpu.l2cache.occ_blocks::writebacks 50336.272506 # Average occupied blocks per requestor
681 system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor
682 system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140365 # Average occupied blocks per requestor
683 system.cpu.l2cache.occ_blocks::cpu.inst 3358.130752 # Average occupied blocks per requestor
684 system.cpu.l2cache.occ_blocks::cpu.data 11075.878059 # Average occupied blocks per requestor
685 system.cpu.l2cache.occ_percent::writebacks 0.768071 # Average percentage of cache occupancy
686 system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
687 system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
688 system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy
689 system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Average percentage of cache occupancy
690 system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy
691 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits
692 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits
693 system.cpu.l2cache.ReadReq_hits::cpu.inst 779161 # number of ReadReq hits
694 system.cpu.l2cache.ReadReq_hits::cpu.data 1277476 # number of ReadReq hits
695 system.cpu.l2cache.ReadReq_hits::total 2065738 # number of ReadReq hits
696 system.cpu.l2cache.Writeback_hits::writebacks 1539412 # number of Writeback hits
697 system.cpu.l2cache.Writeback_hits::total 1539412 # number of Writeback hits
698 system.cpu.l2cache.UpgradeReq_hits::cpu.data 293 # number of UpgradeReq hits
699 system.cpu.l2cache.UpgradeReq_hits::total 293 # number of UpgradeReq hits
700 system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits
701 system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits
702 system.cpu.l2cache.demand_hits::cpu.dtb.walker 6347 # number of demand (read+write) hits
703 system.cpu.l2cache.demand_hits::cpu.itb.walker 2754 # number of demand (read+write) hits
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707 system.cpu.l2cache.overall_hits::cpu.dtb.walker 6347 # number of overall hits
708 system.cpu.l2cache.overall_hits::cpu.itb.walker 2754 # number of overall hits
709 system.cpu.l2cache.overall_hits::cpu.inst 779161 # number of overall hits
710 system.cpu.l2cache.overall_hits::cpu.data 1476840 # number of overall hits
711 system.cpu.l2cache.overall_hits::total 2265102 # number of overall hits
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713 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
714 system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses
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716 system.cpu.l2cache.ReadReq_misses::total 41263 # number of ReadReq misses
717 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1364 # number of UpgradeReq misses
718 system.cpu.l2cache.UpgradeReq_misses::total 1364 # number of UpgradeReq misses
719 system.cpu.l2cache.ReadExReq_misses::cpu.data 113358 # number of ReadExReq misses
720 system.cpu.l2cache.ReadExReq_misses::total 113358 # number of ReadExReq misses
721 system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
722 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
723 system.cpu.l2cache.demand_misses::cpu.inst 12872 # number of demand (read+write) misses
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725 system.cpu.l2cache.demand_misses::total 154621 # number of demand (read+write) misses
726 system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
727 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
728 system.cpu.l2cache.overall_misses::cpu.inst 12872 # number of overall misses
729 system.cpu.l2cache.overall_misses::cpu.data 141743 # number of overall misses
730 system.cpu.l2cache.overall_misses::total 154621 # number of overall misses
731 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 68500 # number of ReadReq miss cycles
732 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles
733 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 791210500 # number of ReadReq miss cycles
734 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1650142000 # number of ReadReq miss cycles
735 system.cpu.l2cache.ReadReq_miss_latency::total 2441766000 # number of ReadReq miss cycles
736 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16179000 # number of UpgradeReq miss cycles
737 system.cpu.l2cache.UpgradeReq_miss_latency::total 16179000 # number of UpgradeReq miss cycles
738 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5584232500 # number of ReadExReq miss cycles
739 system.cpu.l2cache.ReadExReq_miss_latency::total 5584232500 # number of ReadExReq miss cycles
740 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 68500 # number of demand (read+write) miss cycles
741 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles
742 system.cpu.l2cache.demand_miss_latency::cpu.inst 791210500 # number of demand (read+write) miss cycles
743 system.cpu.l2cache.demand_miss_latency::cpu.data 7234374500 # number of demand (read+write) miss cycles
744 system.cpu.l2cache.demand_miss_latency::total 8025998500 # number of demand (read+write) miss cycles
745 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 68500 # number of overall miss cycles
746 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles
747 system.cpu.l2cache.overall_miss_latency::cpu.inst 791210500 # number of overall miss cycles
748 system.cpu.l2cache.overall_miss_latency::cpu.data 7234374500 # number of overall miss cycles
749 system.cpu.l2cache.overall_miss_latency::total 8025998500 # number of overall miss cycles
750 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6348 # number of ReadReq accesses(hits+misses)
751 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2759 # number of ReadReq accesses(hits+misses)
752 system.cpu.l2cache.ReadReq_accesses::cpu.inst 792033 # number of ReadReq accesses(hits+misses)
753 system.cpu.l2cache.ReadReq_accesses::cpu.data 1305861 # number of ReadReq accesses(hits+misses)
754 system.cpu.l2cache.ReadReq_accesses::total 2107001 # number of ReadReq accesses(hits+misses)
755 system.cpu.l2cache.Writeback_accesses::writebacks 1539412 # number of Writeback accesses(hits+misses)
756 system.cpu.l2cache.Writeback_accesses::total 1539412 # number of Writeback accesses(hits+misses)
757 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses)
758 system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses)
759 system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses)
760 system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses)
761 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses
762 system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses
763 system.cpu.l2cache.demand_accesses::cpu.inst 792033 # number of demand (read+write) accesses
764 system.cpu.l2cache.demand_accesses::cpu.data 1618583 # number of demand (read+write) accesses
765 system.cpu.l2cache.demand_accesses::total 2419723 # number of demand (read+write) accesses
766 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses
767 system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses
768 system.cpu.l2cache.overall_accesses::cpu.inst 792033 # number of overall (read+write) accesses
769 system.cpu.l2cache.overall_accesses::cpu.data 1618583 # number of overall (read+write) accesses
770 system.cpu.l2cache.overall_accesses::total 2419723 # number of overall (read+write) accesses
771 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses
772 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses
773 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses
774 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737 # miss rate for ReadReq accesses
775 system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses
776 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses
777 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses
778 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses
779 system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses
780 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses
781 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses
782 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses
783 system.cpu.l2cache.demand_miss_rate::cpu.data 0.087572 # miss rate for demand accesses
784 system.cpu.l2cache.demand_miss_rate::total 0.063900 # miss rate for demand accesses
785 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000158 # miss rate for overall accesses
786 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001812 # miss rate for overall accesses
787 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016252 # miss rate for overall accesses
788 system.cpu.l2cache.overall_miss_rate::cpu.data 0.087572 # miss rate for overall accesses
789 system.cpu.l2cache.overall_miss_rate::total 0.063900 # miss rate for overall accesses
790 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency
791 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
792 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61467.565258 # average ReadReq miss latency
793 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58134.296283 # average ReadReq miss latency
794 system.cpu.l2cache.ReadReq_avg_miss_latency::total 59175.677968 # average ReadReq miss latency
795 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11861.436950 # average UpgradeReq miss latency
796 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11861.436950 # average UpgradeReq miss latency
797 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49261.917994 # average ReadExReq miss latency
798 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49261.917994 # average ReadExReq miss latency
799 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency
800 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
801 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency
802 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency
803 system.cpu.l2cache.demand_avg_miss_latency::total 51907.557835 # average overall miss latency
804 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency
805 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
806 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency
807 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency
808 system.cpu.l2cache.overall_avg_miss_latency::total 51907.557835 # average overall miss latency
809 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
810 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
811 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
812 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
813 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
814 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
815 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
816 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
817 system.cpu.l2cache.writebacks::writebacks 80257 # number of writebacks
818 system.cpu.l2cache.writebacks::total 80257 # number of writebacks
819 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
820 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
821 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses
822 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28385 # number of ReadReq MSHR misses
823 system.cpu.l2cache.ReadReq_mshr_misses::total 41263 # number of ReadReq MSHR misses
824 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1364 # number of UpgradeReq MSHR misses
825 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1364 # number of UpgradeReq MSHR misses
826 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113358 # number of ReadExReq MSHR misses
827 system.cpu.l2cache.ReadExReq_mshr_misses::total 113358 # number of ReadExReq MSHR misses
828 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
829 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
830 system.cpu.l2cache.demand_mshr_misses::cpu.inst 12872 # number of demand (read+write) MSHR misses
831 system.cpu.l2cache.demand_mshr_misses::cpu.data 141743 # number of demand (read+write) MSHR misses
832 system.cpu.l2cache.demand_mshr_misses::total 154621 # number of demand (read+write) MSHR misses
833 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
834 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
835 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses
836 system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses
837 system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses
838 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles
839 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles
840 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 631288357 # number of ReadReq MSHR miss cycles
841 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1297548953 # number of ReadReq MSHR miss cycles
842 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1929174816 # number of ReadReq MSHR miss cycles
843 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14616845 # number of UpgradeReq MSHR miss cycles
844 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14616845 # number of UpgradeReq MSHR miss cycles
845 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4191303025 # number of ReadExReq MSHR miss cycles
846 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4191303025 # number of ReadExReq MSHR miss cycles
847 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
848 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
849 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 631288357 # number of demand (read+write) MSHR miss cycles
850 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5488851978 # number of demand (read+write) MSHR miss cycles
851 system.cpu.l2cache.demand_mshr_miss_latency::total 6120477841 # number of demand (read+write) MSHR miss cycles
852 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles
853 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
854 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 631288357 # number of overall MSHR miss cycles
855 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5488851978 # number of overall MSHR miss cycles
856 system.cpu.l2cache.overall_mshr_miss_latency::total 6120477841 # number of overall MSHR miss cycles
857 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles
858 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles
859 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305022500 # number of WriteReq MSHR uncacheable cycles
860 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305022500 # number of WriteReq MSHR uncacheable cycles
861 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896198000 # number of overall MSHR uncacheable cycles
862 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896198000 # number of overall MSHR uncacheable cycles
863 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses
864 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses
865 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses
866 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 # mshr miss rate for ReadReq accesses
867 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses
868 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses
869 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses
870 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
871 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
872 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses
873 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses
874 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses
875 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for demand accesses
876 system.cpu.l2cache.demand_mshr_miss_rate::total 0.063900 # mshr miss rate for demand accesses
877 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses
878 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses
879 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses
880 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for overall accesses
881 system.cpu.l2cache.overall_mshr_miss_rate::total 0.063900 # mshr miss rate for overall accesses
882 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency
883 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
884 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency
885 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency
886 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency
887 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency
888 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency
889 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency
890 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency
891 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
892 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
893 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
894 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
895 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
896 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
897 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
898 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
899 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
900 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
901 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
902 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
903 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
904 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
905 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
906 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
907 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
909 ---------- End Simulation Statistics ----------
projects / gem5.git / blob