2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.196043 # Number of seconds simulated
4 sim_ticks 5196043137000 # Number of ticks simulated
5 final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1241473 # Simulator instruction rate (inst/s)
8 host_op_rate 2393258 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 50303585789 # Simulator tick rate (ticks/s)
10 host_mem_usage 354304 # Number of bytes of host memory used
11 host_seconds 103.29 # Real time elapsed on the host
12 sim_insts 128236332 # Number of instructions simulated
13 sim_ops 247208442 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.inst 824320 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 8950528 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 12656512 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 824320 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 824320 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 8081152 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 8081152 # Number of bytes written to this memory
23 system.physmem.num_reads::pc.south_bridge.ide 45021 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.inst 12880 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 139852 # Number of read requests responded to by this memory
27 system.physmem.num_reads::total 197758 # Number of read requests responded to by this memory
28 system.physmem.num_writes::writebacks 126268 # Number of write requests responded to by this memory
29 system.physmem.num_writes::total 126268 # Number of write requests responded to by this memory
30 system.physmem.bw_read::pc.south_bridge.ide 554527 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.inst 158644 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.data 1722566 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 2435798 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 158644 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 158644 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 1555251 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 1555251 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 1555251 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::pc.south_bridge.ide 554527 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::cpu.inst 158644 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::cpu.data 1722566 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::total 3991049 # Total bandwidth to/from this memory (bytes/s)
45 system.l2c.replacements 86291 # number of replacements
46 system.l2c.tagsinuse 64759.780052 # Cycle average of tags in use
47 system.l2c.total_refs 3494113 # Total number of references to valid blocks.
48 system.l2c.sampled_refs 150981 # Sample count of references to valid blocks.
49 system.l2c.avg_refs 23.142733 # Average number of references to valid blocks.
50 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
51 system.l2c.occ_blocks::writebacks 50071.847750 # Average occupied blocks per requestor
52 system.l2c.occ_blocks::cpu.itb.walker 0.141309 # Average occupied blocks per requestor
53 system.l2c.occ_blocks::cpu.inst 3396.359734 # Average occupied blocks per requestor
54 system.l2c.occ_blocks::cpu.data 11291.431260 # Average occupied blocks per requestor
55 system.l2c.occ_percent::writebacks 0.764036 # Average percentage of cache occupancy
56 system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
57 system.l2c.occ_percent::cpu.inst 0.051824 # Average percentage of cache occupancy
58 system.l2c.occ_percent::cpu.data 0.172294 # Average percentage of cache occupancy
59 system.l2c.occ_percent::total 0.988156 # Average percentage of cache occupancy
60 system.l2c.ReadReq_hits::cpu.dtb.walker 6458 # number of ReadReq hits
61 system.l2c.ReadReq_hits::cpu.itb.walker 2811 # number of ReadReq hits
62 system.l2c.ReadReq_hits::cpu.inst 779608 # number of ReadReq hits
63 system.l2c.ReadReq_hits::cpu.data 1280721 # number of ReadReq hits
64 system.l2c.ReadReq_hits::total 2069598 # number of ReadReq hits
65 system.l2c.Writeback_hits::writebacks 1543757 # number of Writeback hits
66 system.l2c.Writeback_hits::total 1543757 # number of Writeback hits
67 system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits
68 system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits
69 system.l2c.ReadExReq_hits::cpu.data 200867 # number of ReadExReq hits
70 system.l2c.ReadExReq_hits::total 200867 # number of ReadExReq hits
71 system.l2c.demand_hits::cpu.dtb.walker 6458 # number of demand (read+write) hits
72 system.l2c.demand_hits::cpu.itb.walker 2811 # number of demand (read+write) hits
73 system.l2c.demand_hits::cpu.inst 779608 # number of demand (read+write) hits
74 system.l2c.demand_hits::cpu.data 1481588 # number of demand (read+write) hits
75 system.l2c.demand_hits::total 2270465 # number of demand (read+write) hits
76 system.l2c.overall_hits::cpu.dtb.walker 6458 # number of overall hits
77 system.l2c.overall_hits::cpu.itb.walker 2811 # number of overall hits
78 system.l2c.overall_hits::cpu.inst 779608 # number of overall hits
79 system.l2c.overall_hits::cpu.data 1481588 # number of overall hits
80 system.l2c.overall_hits::total 2270465 # number of overall hits
81 system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
82 system.l2c.ReadReq_misses::cpu.inst 12881 # number of ReadReq misses
83 system.l2c.ReadReq_misses::cpu.data 28319 # number of ReadReq misses
84 system.l2c.ReadReq_misses::total 41205 # number of ReadReq misses
85 system.l2c.UpgradeReq_misses::cpu.data 1371 # number of UpgradeReq misses
86 system.l2c.UpgradeReq_misses::total 1371 # number of UpgradeReq misses
87 system.l2c.ReadExReq_misses::cpu.data 112462 # number of ReadExReq misses
88 system.l2c.ReadExReq_misses::total 112462 # number of ReadExReq misses
89 system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
90 system.l2c.demand_misses::cpu.inst 12881 # number of demand (read+write) misses
91 system.l2c.demand_misses::cpu.data 140781 # number of demand (read+write) misses
92 system.l2c.demand_misses::total 153667 # number of demand (read+write) misses
93 system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
94 system.l2c.overall_misses::cpu.inst 12881 # number of overall misses
95 system.l2c.overall_misses::cpu.data 140781 # number of overall misses
96 system.l2c.overall_misses::total 153667 # number of overall misses
97 system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
98 system.l2c.ReadReq_miss_latency::cpu.inst 670242000 # number of ReadReq miss cycles
99 system.l2c.ReadReq_miss_latency::cpu.data 1486972500 # number of ReadReq miss cycles
100 system.l2c.ReadReq_miss_latency::total 2157474500 # number of ReadReq miss cycles
101 system.l2c.UpgradeReq_miss_latency::cpu.data 34071000 # number of UpgradeReq miss cycles
102 system.l2c.UpgradeReq_miss_latency::total 34071000 # number of UpgradeReq miss cycles
103 system.l2c.ReadExReq_miss_latency::cpu.data 5850445000 # number of ReadExReq miss cycles
104 system.l2c.ReadExReq_miss_latency::total 5850445000 # number of ReadExReq miss cycles
105 system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
106 system.l2c.demand_miss_latency::cpu.inst 670242000 # number of demand (read+write) miss cycles
107 system.l2c.demand_miss_latency::cpu.data 7337417500 # number of demand (read+write) miss cycles
108 system.l2c.demand_miss_latency::total 8007919500 # number of demand (read+write) miss cycles
109 system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
110 system.l2c.overall_miss_latency::cpu.inst 670242000 # number of overall miss cycles
111 system.l2c.overall_miss_latency::cpu.data 7337417500 # number of overall miss cycles
112 system.l2c.overall_miss_latency::total 8007919500 # number of overall miss cycles
113 system.l2c.ReadReq_accesses::cpu.dtb.walker 6458 # number of ReadReq accesses(hits+misses)
114 system.l2c.ReadReq_accesses::cpu.itb.walker 2816 # number of ReadReq accesses(hits+misses)
115 system.l2c.ReadReq_accesses::cpu.inst 792489 # number of ReadReq accesses(hits+misses)
116 system.l2c.ReadReq_accesses::cpu.data 1309040 # number of ReadReq accesses(hits+misses)
117 system.l2c.ReadReq_accesses::total 2110803 # number of ReadReq accesses(hits+misses)
118 system.l2c.Writeback_accesses::writebacks 1543757 # number of Writeback accesses(hits+misses)
119 system.l2c.Writeback_accesses::total 1543757 # number of Writeback accesses(hits+misses)
120 system.l2c.UpgradeReq_accesses::cpu.data 1676 # number of UpgradeReq accesses(hits+misses)
121 system.l2c.UpgradeReq_accesses::total 1676 # number of UpgradeReq accesses(hits+misses)
122 system.l2c.ReadExReq_accesses::cpu.data 313329 # number of ReadExReq accesses(hits+misses)
123 system.l2c.ReadExReq_accesses::total 313329 # number of ReadExReq accesses(hits+misses)
124 system.l2c.demand_accesses::cpu.dtb.walker 6458 # number of demand (read+write) accesses
125 system.l2c.demand_accesses::cpu.itb.walker 2816 # number of demand (read+write) accesses
126 system.l2c.demand_accesses::cpu.inst 792489 # number of demand (read+write) accesses
127 system.l2c.demand_accesses::cpu.data 1622369 # number of demand (read+write) accesses
128 system.l2c.demand_accesses::total 2424132 # number of demand (read+write) accesses
129 system.l2c.overall_accesses::cpu.dtb.walker 6458 # number of overall (read+write) accesses
130 system.l2c.overall_accesses::cpu.itb.walker 2816 # number of overall (read+write) accesses
131 system.l2c.overall_accesses::cpu.inst 792489 # number of overall (read+write) accesses
132 system.l2c.overall_accesses::cpu.data 1622369 # number of overall (read+write) accesses
133 system.l2c.overall_accesses::total 2424132 # number of overall (read+write) accesses
134 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001776 # miss rate for ReadReq accesses
135 system.l2c.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses
136 system.l2c.ReadReq_miss_rate::cpu.data 0.021633 # miss rate for ReadReq accesses
137 system.l2c.ReadReq_miss_rate::total 0.019521 # miss rate for ReadReq accesses
138 system.l2c.UpgradeReq_miss_rate::cpu.data 0.818019 # miss rate for UpgradeReq accesses
139 system.l2c.UpgradeReq_miss_rate::total 0.818019 # miss rate for UpgradeReq accesses
140 system.l2c.ReadExReq_miss_rate::cpu.data 0.358926 # miss rate for ReadExReq accesses
141 system.l2c.ReadExReq_miss_rate::total 0.358926 # miss rate for ReadExReq accesses
142 system.l2c.demand_miss_rate::cpu.itb.walker 0.001776 # miss rate for demand accesses
143 system.l2c.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses
144 system.l2c.demand_miss_rate::cpu.data 0.086775 # miss rate for demand accesses
145 system.l2c.demand_miss_rate::total 0.063391 # miss rate for demand accesses
146 system.l2c.overall_miss_rate::cpu.itb.walker 0.001776 # miss rate for overall accesses
147 system.l2c.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses
148 system.l2c.overall_miss_rate::cpu.data 0.086775 # miss rate for overall accesses
149 system.l2c.overall_miss_rate::total 0.063391 # miss rate for overall accesses
150 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
151 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52033.382501 # average ReadReq miss latency
152 system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.945196 # average ReadReq miss latency
153 system.l2c.ReadReq_avg_miss_latency::total 52359.531610 # average ReadReq miss latency
154 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24851.203501 # average UpgradeReq miss latency
155 system.l2c.UpgradeReq_avg_miss_latency::total 24851.203501 # average UpgradeReq miss latency
156 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52021.527271 # average ReadExReq miss latency
157 system.l2c.ReadExReq_avg_miss_latency::total 52021.527271 # average ReadExReq miss latency
158 system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
159 system.l2c.demand_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency
160 system.l2c.demand_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency
161 system.l2c.demand_avg_miss_latency::total 52112.161362 # average overall miss latency
162 system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
163 system.l2c.overall_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency
164 system.l2c.overall_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency
165 system.l2c.overall_avg_miss_latency::total 52112.161362 # average overall miss latency
166 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
167 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
168 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
169 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
170 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
171 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
172 system.l2c.fast_writes 0 # number of fast writes performed
173 system.l2c.cache_copies 0 # number of cache copies performed
174 system.l2c.writebacks::writebacks 79601 # number of writebacks
175 system.l2c.writebacks::total 79601 # number of writebacks
176 system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
177 system.l2c.ReadReq_mshr_misses::cpu.inst 12881 # number of ReadReq MSHR misses
178 system.l2c.ReadReq_mshr_misses::cpu.data 28319 # number of ReadReq MSHR misses
179 system.l2c.ReadReq_mshr_misses::total 41205 # number of ReadReq MSHR misses
180 system.l2c.UpgradeReq_mshr_misses::cpu.data 1371 # number of UpgradeReq MSHR misses
181 system.l2c.UpgradeReq_mshr_misses::total 1371 # number of UpgradeReq MSHR misses
182 system.l2c.ReadExReq_mshr_misses::cpu.data 112462 # number of ReadExReq MSHR misses
183 system.l2c.ReadExReq_mshr_misses::total 112462 # number of ReadExReq MSHR misses
184 system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
185 system.l2c.demand_mshr_misses::cpu.inst 12881 # number of demand (read+write) MSHR misses
186 system.l2c.demand_mshr_misses::cpu.data 140781 # number of demand (read+write) MSHR misses
187 system.l2c.demand_mshr_misses::total 153667 # number of demand (read+write) MSHR misses
188 system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
189 system.l2c.overall_mshr_misses::cpu.inst 12881 # number of overall MSHR misses
190 system.l2c.overall_mshr_misses::cpu.data 140781 # number of overall MSHR misses
191 system.l2c.overall_mshr_misses::total 153667 # number of overall MSHR misses
192 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
193 system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515661000 # number of ReadReq MSHR miss cycles
194 system.l2c.ReadReq_mshr_miss_latency::cpu.data 1147140000 # number of ReadReq MSHR miss cycles
195 system.l2c.ReadReq_mshr_miss_latency::total 1663001000 # number of ReadReq MSHR miss cycles
196 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55229000 # number of UpgradeReq MSHR miss cycles
197 system.l2c.UpgradeReq_mshr_miss_latency::total 55229000 # number of UpgradeReq MSHR miss cycles
198 system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4500898000 # number of ReadExReq MSHR miss cycles
199 system.l2c.ReadExReq_mshr_miss_latency::total 4500898000 # number of ReadExReq MSHR miss cycles
200 system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
201 system.l2c.demand_mshr_miss_latency::cpu.inst 515661000 # number of demand (read+write) MSHR miss cycles
202 system.l2c.demand_mshr_miss_latency::cpu.data 5648038000 # number of demand (read+write) MSHR miss cycles
203 system.l2c.demand_mshr_miss_latency::total 6163899000 # number of demand (read+write) MSHR miss cycles
204 system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
205 system.l2c.overall_mshr_miss_latency::cpu.inst 515661000 # number of overall MSHR miss cycles
206 system.l2c.overall_mshr_miss_latency::cpu.data 5648038000 # number of overall MSHR miss cycles
207 system.l2c.overall_mshr_miss_latency::total 6163899000 # number of overall MSHR miss cycles
208 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles
209 system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles
210 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306140000 # number of WriteReq MSHR uncacheable cycles
211 system.l2c.WriteReq_mshr_uncacheable_latency::total 2306140000 # number of WriteReq MSHR uncacheable cycles
212 system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423590000 # number of overall MSHR uncacheable cycles
213 system.l2c.overall_mshr_uncacheable_latency::total 88423590000 # number of overall MSHR uncacheable cycles
214 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for ReadReq accesses
215 system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses
216 system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021633 # mshr miss rate for ReadReq accesses
217 system.l2c.ReadReq_mshr_miss_rate::total 0.019521 # mshr miss rate for ReadReq accesses
218 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818019 # mshr miss rate for UpgradeReq accesses
219 system.l2c.UpgradeReq_mshr_miss_rate::total 0.818019 # mshr miss rate for UpgradeReq accesses
220 system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358926 # mshr miss rate for ReadExReq accesses
221 system.l2c.ReadExReq_mshr_miss_rate::total 0.358926 # mshr miss rate for ReadExReq accesses
222 system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for demand accesses
223 system.l2c.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses
224 system.l2c.demand_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for demand accesses
225 system.l2c.demand_mshr_miss_rate::total 0.063391 # mshr miss rate for demand accesses
226 system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for overall accesses
227 system.l2c.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses
228 system.l2c.overall_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for overall accesses
229 system.l2c.overall_mshr_miss_rate::total 0.063391 # mshr miss rate for overall accesses
230 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
231 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798 # average ReadReq mshr miss latency
232 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292 # average ReadReq mshr miss latency
233 system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980 # average ReadReq mshr miss latency
234 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500 # average UpgradeReq mshr miss latency
235 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500 # average UpgradeReq mshr miss latency
236 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596 # average ReadExReq mshr miss latency
237 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596 # average ReadExReq mshr miss latency
238 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
239 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency
240 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency
241 system.l2c.demand_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency
242 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
243 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency
244 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency
245 system.l2c.overall_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency
246 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
247 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
248 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
249 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
250 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
251 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
252 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
253 system.iocache.replacements 47503 # number of replacements
254 system.iocache.tagsinuse 0.108785 # Cycle average of tags in use
255 system.iocache.total_refs 0 # Total number of references to valid blocks.
256 system.iocache.sampled_refs 47519 # Sample count of references to valid blocks.
257 system.iocache.avg_refs 0 # Average number of references to valid blocks.
258 system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit.
259 system.iocache.occ_blocks::pc.south_bridge.ide 0.108785 # Average occupied blocks per requestor
260 system.iocache.occ_percent::pc.south_bridge.ide 0.006799 # Average percentage of cache occupancy
261 system.iocache.occ_percent::total 0.006799 # Average percentage of cache occupancy
262 system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses
263 system.iocache.ReadReq_misses::total 838 # number of ReadReq misses
264 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
265 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
266 system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses
267 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
268 system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
269 system.iocache.overall_misses::total 47558 # number of overall misses
270 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128838932 # number of ReadReq miss cycles
271 system.iocache.ReadReq_miss_latency::total 128838932 # number of ReadReq miss cycles
272 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7147789160 # number of WriteReq miss cycles
273 system.iocache.WriteReq_miss_latency::total 7147789160 # number of WriteReq miss cycles
274 system.iocache.demand_miss_latency::pc.south_bridge.ide 7276628092 # number of demand (read+write) miss cycles
275 system.iocache.demand_miss_latency::total 7276628092 # number of demand (read+write) miss cycles
276 system.iocache.overall_miss_latency::pc.south_bridge.ide 7276628092 # number of overall miss cycles
277 system.iocache.overall_miss_latency::total 7276628092 # number of overall miss cycles
278 system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
279 system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
280 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
281 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
282 system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses
283 system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses
284 system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses
285 system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses
286 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
287 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
288 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
289 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
290 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
291 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
292 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
293 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
294 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243 # average ReadReq miss latency
295 system.iocache.ReadReq_avg_miss_latency::total 153745.742243 # average ReadReq miss latency
296 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500 # average WriteReq miss latency
297 system.iocache.WriteReq_avg_miss_latency::total 152992.062500 # average WriteReq miss latency
298 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency
299 system.iocache.demand_avg_miss_latency::total 153005.342781 # average overall miss latency
300 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency
301 system.iocache.overall_avg_miss_latency::total 153005.342781 # average overall miss latency
302 system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked
303 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
304 system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked
305 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
306 system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked
307 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
308 system.iocache.fast_writes 0 # number of fast writes performed
309 system.iocache.cache_copies 0 # number of cache copies performed
310 system.iocache.writebacks::writebacks 46667 # number of writebacks
311 system.iocache.writebacks::total 46667 # number of writebacks
312 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses
313 system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses
314 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
315 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
316 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses
317 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
318 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
319 system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses
320 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85232000 # number of ReadReq MSHR miss cycles
321 system.iocache.ReadReq_mshr_miss_latency::total 85232000 # number of ReadReq MSHR miss cycles
322 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4718093984 # number of WriteReq MSHR miss cycles
323 system.iocache.WriteReq_mshr_miss_latency::total 4718093984 # number of WriteReq MSHR miss cycles
324 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of demand (read+write) MSHR miss cycles
325 system.iocache.demand_mshr_miss_latency::total 4803325984 # number of demand (read+write) MSHR miss cycles
326 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of overall MSHR miss cycles
327 system.iocache.overall_mshr_miss_latency::total 4803325984 # number of overall MSHR miss cycles
328 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
329 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
330 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
331 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
332 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
333 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
334 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
335 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
336 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549 # average ReadReq mshr miss latency
337 system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549 # average ReadReq mshr miss latency
338 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685 # average WriteReq mshr miss latency
339 system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685 # average WriteReq mshr miss latency
340 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency
341 system.iocache.demand_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency
342 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency
343 system.iocache.overall_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency
344 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
345 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
346 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
347 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
348 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
349 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
350 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
351 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
352 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
353 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
354 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
355 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
356 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
357 system.cpu.numCycles 10392086274 # number of cpu cycles simulated
358 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
359 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
360 system.cpu.committedInsts 128236332 # Number of instructions committed
361 system.cpu.committedOps 247208442 # Number of ops (including micro ops) committed
362 system.cpu.num_int_alu_accesses 231946757 # Number of integer alu accesses
363 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
364 system.cpu.num_func_calls 0 # number of times a function call or return occured
365 system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls
366 system.cpu.num_int_insts 231946757 # number of integer instructions
367 system.cpu.num_fp_insts 0 # number of float instructions
368 system.cpu.num_int_register_reads 720715933 # number of times the integer registers were read
369 system.cpu.num_int_register_writes 387556667 # number of times the integer registers were written
370 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
371 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
372 system.cpu.num_mem_refs 22230275 # number of memory refs
373 system.cpu.num_load_insts 13869948 # Number of load instructions
374 system.cpu.num_store_insts 8360327 # Number of store instructions
375 system.cpu.num_idle_cycles 9776409858.670118 # Number of idle cycles
376 system.cpu.num_busy_cycles 615676415.329882 # Number of busy cycles
377 system.cpu.not_idle_fraction 0.059245 # Percentage of non-idle cycles
378 system.cpu.idle_fraction 0.940755 # Percentage of idle cycles
379 system.cpu.kern.inst.arm 0 # number of arm instructions executed
380 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
381 system.cpu.icache.replacements 791983 # number of replacements
382 system.cpu.icache.tagsinuse 510.339207 # Cycle average of tags in use
383 system.cpu.icache.total_refs 144447737 # Total number of references to valid blocks.
384 system.cpu.icache.sampled_refs 792495 # Sample count of references to valid blocks.
385 system.cpu.icache.avg_refs 182.269588 # Average number of references to valid blocks.
386 system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit.
387 system.cpu.icache.occ_blocks::cpu.inst 510.339207 # Average occupied blocks per requestor
388 system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy
389 system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy
390 system.cpu.icache.ReadReq_hits::cpu.inst 144447737 # number of ReadReq hits
391 system.cpu.icache.ReadReq_hits::total 144447737 # number of ReadReq hits
392 system.cpu.icache.demand_hits::cpu.inst 144447737 # number of demand (read+write) hits
393 system.cpu.icache.demand_hits::total 144447737 # number of demand (read+write) hits
394 system.cpu.icache.overall_hits::cpu.inst 144447737 # number of overall hits
395 system.cpu.icache.overall_hits::total 144447737 # number of overall hits
396 system.cpu.icache.ReadReq_misses::cpu.inst 792502 # number of ReadReq misses
397 system.cpu.icache.ReadReq_misses::total 792502 # number of ReadReq misses
398 system.cpu.icache.demand_misses::cpu.inst 792502 # number of demand (read+write) misses
399 system.cpu.icache.demand_misses::total 792502 # number of demand (read+write) misses
400 system.cpu.icache.overall_misses::cpu.inst 792502 # number of overall misses
401 system.cpu.icache.overall_misses::total 792502 # number of overall misses
402 system.cpu.icache.ReadReq_miss_latency::cpu.inst 11813272500 # number of ReadReq miss cycles
403 system.cpu.icache.ReadReq_miss_latency::total 11813272500 # number of ReadReq miss cycles
404 system.cpu.icache.demand_miss_latency::cpu.inst 11813272500 # number of demand (read+write) miss cycles
405 system.cpu.icache.demand_miss_latency::total 11813272500 # number of demand (read+write) miss cycles
406 system.cpu.icache.overall_miss_latency::cpu.inst 11813272500 # number of overall miss cycles
407 system.cpu.icache.overall_miss_latency::total 11813272500 # number of overall miss cycles
408 system.cpu.icache.ReadReq_accesses::cpu.inst 145240239 # number of ReadReq accesses(hits+misses)
409 system.cpu.icache.ReadReq_accesses::total 145240239 # number of ReadReq accesses(hits+misses)
410 system.cpu.icache.demand_accesses::cpu.inst 145240239 # number of demand (read+write) accesses
411 system.cpu.icache.demand_accesses::total 145240239 # number of demand (read+write) accesses
412 system.cpu.icache.overall_accesses::cpu.inst 145240239 # number of overall (read+write) accesses
413 system.cpu.icache.overall_accesses::total 145240239 # number of overall (read+write) accesses
414 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005456 # miss rate for ReadReq accesses
415 system.cpu.icache.ReadReq_miss_rate::total 0.005456 # miss rate for ReadReq accesses
416 system.cpu.icache.demand_miss_rate::cpu.inst 0.005456 # miss rate for demand accesses
417 system.cpu.icache.demand_miss_rate::total 0.005456 # miss rate for demand accesses
418 system.cpu.icache.overall_miss_rate::cpu.inst 0.005456 # miss rate for overall accesses
419 system.cpu.icache.overall_miss_rate::total 0.005456 # miss rate for overall accesses
420 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921 # average ReadReq miss latency
421 system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921 # average ReadReq miss latency
422 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency
423 system.cpu.icache.demand_avg_miss_latency::total 14906.299921 # average overall miss latency
424 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency
425 system.cpu.icache.overall_avg_miss_latency::total 14906.299921 # average overall miss latency
426 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
427 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
428 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
429 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
430 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
431 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
432 system.cpu.icache.fast_writes 0 # number of fast writes performed
433 system.cpu.icache.cache_copies 0 # number of cache copies performed
434 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792502 # number of ReadReq MSHR misses
435 system.cpu.icache.ReadReq_mshr_misses::total 792502 # number of ReadReq MSHR misses
436 system.cpu.icache.demand_mshr_misses::cpu.inst 792502 # number of demand (read+write) MSHR misses
437 system.cpu.icache.demand_mshr_misses::total 792502 # number of demand (read+write) MSHR misses
438 system.cpu.icache.overall_mshr_misses::cpu.inst 792502 # number of overall MSHR misses
439 system.cpu.icache.overall_mshr_misses::total 792502 # number of overall MSHR misses
440 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9434751000 # number of ReadReq MSHR miss cycles
441 system.cpu.icache.ReadReq_mshr_miss_latency::total 9434751000 # number of ReadReq MSHR miss cycles
442 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9434751000 # number of demand (read+write) MSHR miss cycles
443 system.cpu.icache.demand_mshr_miss_latency::total 9434751000 # number of demand (read+write) MSHR miss cycles
444 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9434751000 # number of overall MSHR miss cycles
445 system.cpu.icache.overall_mshr_miss_latency::total 9434751000 # number of overall MSHR miss cycles
446 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for ReadReq accesses
447 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005456 # mshr miss rate for ReadReq accesses
448 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for demand accesses
449 system.cpu.icache.demand_mshr_miss_rate::total 0.005456 # mshr miss rate for demand accesses
450 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for overall accesses
451 system.cpu.icache.overall_mshr_miss_rate::total 0.005456 # mshr miss rate for overall accesses
452 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536 # average ReadReq mshr miss latency
453 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536 # average ReadReq mshr miss latency
454 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency
455 system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency
456 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency
457 system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency
458 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
459 system.cpu.itb_walker_cache.replacements 3538 # number of replacements
460 system.cpu.itb_walker_cache.tagsinuse 3.068811 # Cycle average of tags in use
461 system.cpu.itb_walker_cache.total_refs 7893 # Total number of references to valid blocks.
462 system.cpu.itb_walker_cache.sampled_refs 3550 # Sample count of references to valid blocks.
463 system.cpu.itb_walker_cache.avg_refs 2.223380 # Average number of references to valid blocks.
464 system.cpu.itb_walker_cache.warmup_cycle 5169410055000 # Cycle when the warmup percentage was hit.
465 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.068811 # Average occupied blocks per requestor
466 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191801 # Average percentage of cache occupancy
467 system.cpu.itb_walker_cache.occ_percent::total 0.191801 # Average percentage of cache occupancy
468 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits
469 system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits
470 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
471 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
472 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits
473 system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits
474 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits
475 system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits
476 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4398 # number of ReadReq misses
477 system.cpu.itb_walker_cache.ReadReq_misses::total 4398 # number of ReadReq misses
478 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4398 # number of demand (read+write) misses
479 system.cpu.itb_walker_cache.demand_misses::total 4398 # number of demand (read+write) misses
480 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4398 # number of overall misses
481 system.cpu.itb_walker_cache.overall_misses::total 4398 # number of overall misses
482 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51351000 # number of ReadReq miss cycles
483 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51351000 # number of ReadReq miss cycles
484 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51351000 # number of demand (read+write) miss cycles
485 system.cpu.itb_walker_cache.demand_miss_latency::total 51351000 # number of demand (read+write) miss cycles
486 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51351000 # number of overall miss cycles
487 system.cpu.itb_walker_cache.overall_miss_latency::total 51351000 # number of overall miss cycles
488 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12314 # number of ReadReq accesses(hits+misses)
489 system.cpu.itb_walker_cache.ReadReq_accesses::total 12314 # number of ReadReq accesses(hits+misses)
490 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
491 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
492 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12316 # number of demand (read+write) accesses
493 system.cpu.itb_walker_cache.demand_accesses::total 12316 # number of demand (read+write) accesses
494 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12316 # number of overall (read+write) accesses
495 system.cpu.itb_walker_cache.overall_accesses::total 12316 # number of overall (read+write) accesses
496 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.357154 # miss rate for ReadReq accesses
497 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.357154 # miss rate for ReadReq accesses
498 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.357096 # miss rate for demand accesses
499 system.cpu.itb_walker_cache.demand_miss_rate::total 0.357096 # miss rate for demand accesses
500 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.357096 # miss rate for overall accesses
501 system.cpu.itb_walker_cache.overall_miss_rate::total 0.357096 # miss rate for overall accesses
502 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086 # average ReadReq miss latency
503 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086 # average ReadReq miss latency
504 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency
505 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086 # average overall miss latency
506 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency
507 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086 # average overall miss latency
508 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
509 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
510 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
511 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
512 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
513 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
514 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
515 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
516 system.cpu.itb_walker_cache.writebacks::writebacks 656 # number of writebacks
517 system.cpu.itb_walker_cache.writebacks::total 656 # number of writebacks
518 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4398 # number of ReadReq MSHR misses
519 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4398 # number of ReadReq MSHR misses
520 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4398 # number of demand (read+write) MSHR misses
521 system.cpu.itb_walker_cache.demand_mshr_misses::total 4398 # number of demand (read+write) MSHR misses
522 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4398 # number of overall MSHR misses
523 system.cpu.itb_walker_cache.overall_mshr_misses::total 4398 # number of overall MSHR misses
524 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38157000 # number of ReadReq MSHR miss cycles
525 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38157000 # number of ReadReq MSHR miss cycles
526 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38157000 # number of demand (read+write) MSHR miss cycles
527 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38157000 # number of demand (read+write) MSHR miss cycles
528 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38157000 # number of overall MSHR miss cycles
529 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38157000 # number of overall MSHR miss cycles
530 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.357154 # mshr miss rate for ReadReq accesses
531 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.357154 # mshr miss rate for ReadReq accesses
532 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for demand accesses
533 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.357096 # mshr miss rate for demand accesses
534 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for overall accesses
535 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.357096 # mshr miss rate for overall accesses
536 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average ReadReq mshr miss latency
537 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8675.989086 # average ReadReq mshr miss latency
538 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency
539 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency
540 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency
541 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency
542 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
543 system.cpu.dtb_walker_cache.replacements 7615 # number of replacements
544 system.cpu.dtb_walker_cache.tagsinuse 5.050606 # Cycle average of tags in use
545 system.cpu.dtb_walker_cache.total_refs 13416 # Total number of references to valid blocks.
546 system.cpu.dtb_walker_cache.sampled_refs 7630 # Sample count of references to valid blocks.
547 system.cpu.dtb_walker_cache.avg_refs 1.758322 # Average number of references to valid blocks.
548 system.cpu.dtb_walker_cache.warmup_cycle 5165509990000 # Cycle when the warmup percentage was hit.
549 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050606 # Average occupied blocks per requestor
550 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315663 # Average percentage of cache occupancy
551 system.cpu.dtb_walker_cache.occ_percent::total 0.315663 # Average percentage of cache occupancy
552 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13416 # number of ReadReq hits
553 system.cpu.dtb_walker_cache.ReadReq_hits::total 13416 # number of ReadReq hits
554 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13416 # number of demand (read+write) hits
555 system.cpu.dtb_walker_cache.demand_hits::total 13416 # number of demand (read+write) hits
556 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13416 # number of overall hits
557 system.cpu.dtb_walker_cache.overall_hits::total 13416 # number of overall hits
558 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8830 # number of ReadReq misses
559 system.cpu.dtb_walker_cache.ReadReq_misses::total 8830 # number of ReadReq misses
560 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8830 # number of demand (read+write) misses
561 system.cpu.dtb_walker_cache.demand_misses::total 8830 # number of demand (read+write) misses
562 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8830 # number of overall misses
563 system.cpu.dtb_walker_cache.overall_misses::total 8830 # number of overall misses
564 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 114790500 # number of ReadReq miss cycles
565 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 114790500 # number of ReadReq miss cycles
566 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 114790500 # number of demand (read+write) miss cycles
567 system.cpu.dtb_walker_cache.demand_miss_latency::total 114790500 # number of demand (read+write) miss cycles
568 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 114790500 # number of overall miss cycles
569 system.cpu.dtb_walker_cache.overall_miss_latency::total 114790500 # number of overall miss cycles
570 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22246 # number of ReadReq accesses(hits+misses)
571 system.cpu.dtb_walker_cache.ReadReq_accesses::total 22246 # number of ReadReq accesses(hits+misses)
572 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22246 # number of demand (read+write) accesses
573 system.cpu.dtb_walker_cache.demand_accesses::total 22246 # number of demand (read+write) accesses
574 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22246 # number of overall (read+write) accesses
575 system.cpu.dtb_walker_cache.overall_accesses::total 22246 # number of overall (read+write) accesses
576 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396925 # miss rate for ReadReq accesses
577 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396925 # miss rate for ReadReq accesses
578 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396925 # miss rate for demand accesses
579 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396925 # miss rate for demand accesses
580 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396925 # miss rate for overall accesses
581 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396925 # miss rate for overall accesses
582 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625 # average ReadReq miss latency
583 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625 # average ReadReq miss latency
584 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency
585 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625 # average overall miss latency
586 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency
587 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625 # average overall miss latency
588 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
589 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
591 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
592 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
593 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
594 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
595 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
596 system.cpu.dtb_walker_cache.writebacks::writebacks 3005 # number of writebacks
597 system.cpu.dtb_walker_cache.writebacks::total 3005 # number of writebacks
598 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8830 # number of ReadReq MSHR misses
599 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8830 # number of ReadReq MSHR misses
600 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8830 # number of demand (read+write) MSHR misses
601 system.cpu.dtb_walker_cache.demand_mshr_misses::total 8830 # number of demand (read+write) MSHR misses
602 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8830 # number of overall MSHR misses
603 system.cpu.dtb_walker_cache.overall_mshr_misses::total 8830 # number of overall MSHR misses
604 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88300000 # number of ReadReq MSHR miss cycles
605 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88300000 # number of ReadReq MSHR miss cycles
606 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88300000 # number of demand (read+write) MSHR miss cycles
607 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88300000 # number of demand (read+write) MSHR miss cycles
608 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88300000 # number of overall MSHR miss cycles
609 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88300000 # number of overall MSHR miss cycles
610 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for ReadReq accesses
611 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396925 # mshr miss rate for ReadReq accesses
612 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for demand accesses
613 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396925 # mshr miss rate for demand accesses
614 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for overall accesses
615 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396925 # mshr miss rate for overall accesses
616 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average ReadReq mshr miss latency
617 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10000 # average ReadReq mshr miss latency
618 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency
619 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency
620 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency
621 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency
622 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
623 system.cpu.dcache.replacements 1622589 # number of replacements
624 system.cpu.dcache.tagsinuse 511.997330 # Cycle average of tags in use
625 system.cpu.dcache.total_refs 20023565 # Total number of references to valid blocks.
626 system.cpu.dcache.sampled_refs 1623101 # Sample count of references to valid blocks.
627 system.cpu.dcache.avg_refs 12.336611 # Average number of references to valid blocks.
628 system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit.
629 system.cpu.dcache.occ_blocks::cpu.data 511.997330 # Average occupied blocks per requestor
630 system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
631 system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
632 system.cpu.dcache.ReadReq_hits::cpu.data 11986605 # number of ReadReq hits
633 system.cpu.dcache.ReadReq_hits::total 11986605 # number of ReadReq hits
634 system.cpu.dcache.WriteReq_hits::cpu.data 8034775 # number of WriteReq hits
635 system.cpu.dcache.WriteReq_hits::total 8034775 # number of WriteReq hits
636 system.cpu.dcache.demand_hits::cpu.data 20021380 # number of demand (read+write) hits
637 system.cpu.dcache.demand_hits::total 20021380 # number of demand (read+write) hits
638 system.cpu.dcache.overall_hits::cpu.data 20021380 # number of overall hits
639 system.cpu.dcache.overall_hits::total 20021380 # number of overall hits
640 system.cpu.dcache.ReadReq_misses::cpu.data 1309816 # number of ReadReq misses
641 system.cpu.dcache.ReadReq_misses::total 1309816 # number of ReadReq misses
642 system.cpu.dcache.WriteReq_misses::cpu.data 315519 # number of WriteReq misses
643 system.cpu.dcache.WriteReq_misses::total 315519 # number of WriteReq misses
644 system.cpu.dcache.demand_misses::cpu.data 1625335 # number of demand (read+write) misses
645 system.cpu.dcache.demand_misses::total 1625335 # number of demand (read+write) misses
646 system.cpu.dcache.overall_misses::cpu.data 1625335 # number of overall misses
647 system.cpu.dcache.overall_misses::total 1625335 # number of overall misses
648 system.cpu.dcache.ReadReq_miss_latency::cpu.data 19889195500 # number of ReadReq miss cycles
649 system.cpu.dcache.ReadReq_miss_latency::total 19889195500 # number of ReadReq miss cycles
650 system.cpu.dcache.WriteReq_miss_latency::cpu.data 9348149500 # number of WriteReq miss cycles
651 system.cpu.dcache.WriteReq_miss_latency::total 9348149500 # number of WriteReq miss cycles
652 system.cpu.dcache.demand_miss_latency::cpu.data 29237345000 # number of demand (read+write) miss cycles
653 system.cpu.dcache.demand_miss_latency::total 29237345000 # number of demand (read+write) miss cycles
654 system.cpu.dcache.overall_miss_latency::cpu.data 29237345000 # number of overall miss cycles
655 system.cpu.dcache.overall_miss_latency::total 29237345000 # number of overall miss cycles
656 system.cpu.dcache.ReadReq_accesses::cpu.data 13296421 # number of ReadReq accesses(hits+misses)
657 system.cpu.dcache.ReadReq_accesses::total 13296421 # number of ReadReq accesses(hits+misses)
658 system.cpu.dcache.WriteReq_accesses::cpu.data 8350294 # number of WriteReq accesses(hits+misses)
659 system.cpu.dcache.WriteReq_accesses::total 8350294 # number of WriteReq accesses(hits+misses)
660 system.cpu.dcache.demand_accesses::cpu.data 21646715 # number of demand (read+write) accesses
661 system.cpu.dcache.demand_accesses::total 21646715 # number of demand (read+write) accesses
662 system.cpu.dcache.overall_accesses::cpu.data 21646715 # number of overall (read+write) accesses
663 system.cpu.dcache.overall_accesses::total 21646715 # number of overall (read+write) accesses
664 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098509 # miss rate for ReadReq accesses
665 system.cpu.dcache.ReadReq_miss_rate::total 0.098509 # miss rate for ReadReq accesses
666 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037785 # miss rate for WriteReq accesses
667 system.cpu.dcache.WriteReq_miss_rate::total 0.037785 # miss rate for WriteReq accesses
668 system.cpu.dcache.demand_miss_rate::cpu.data 0.075085 # miss rate for demand accesses
669 system.cpu.dcache.demand_miss_rate::total 0.075085 # miss rate for demand accesses
670 system.cpu.dcache.overall_miss_rate::cpu.data 0.075085 # miss rate for overall accesses
671 system.cpu.dcache.overall_miss_rate::total 0.075085 # miss rate for overall accesses
672 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801 # average ReadReq miss latency
673 system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801 # average ReadReq miss latency
674 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670 # average WriteReq miss latency
675 system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670 # average WriteReq miss latency
676 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency
677 system.cpu.dcache.demand_avg_miss_latency::total 17988.503908 # average overall miss latency
678 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency
679 system.cpu.dcache.overall_avg_miss_latency::total 17988.503908 # average overall miss latency
680 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
683 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
684 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
685 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
686 system.cpu.dcache.fast_writes 0 # number of fast writes performed
687 system.cpu.dcache.cache_copies 0 # number of cache copies performed
688 system.cpu.dcache.writebacks::writebacks 1540096 # number of writebacks
689 system.cpu.dcache.writebacks::total 1540096 # number of writebacks
690 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309816 # number of ReadReq MSHR misses
691 system.cpu.dcache.ReadReq_mshr_misses::total 1309816 # number of ReadReq MSHR misses
692 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315519 # number of WriteReq MSHR misses
693 system.cpu.dcache.WriteReq_mshr_misses::total 315519 # number of WriteReq MSHR misses
694 system.cpu.dcache.demand_mshr_misses::cpu.data 1625335 # number of demand (read+write) MSHR misses
695 system.cpu.dcache.demand_mshr_misses::total 1625335 # number of demand (read+write) MSHR misses
696 system.cpu.dcache.overall_mshr_misses::cpu.data 1625335 # number of overall MSHR misses
697 system.cpu.dcache.overall_mshr_misses::total 1625335 # number of overall MSHR misses
698 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15959698500 # number of ReadReq MSHR miss cycles
699 system.cpu.dcache.ReadReq_mshr_miss_latency::total 15959698500 # number of ReadReq MSHR miss cycles
700 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401590001 # number of WriteReq MSHR miss cycles
701 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401590001 # number of WriteReq MSHR miss cycles
702 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24361288501 # number of demand (read+write) MSHR miss cycles
703 system.cpu.dcache.demand_mshr_miss_latency::total 24361288501 # number of demand (read+write) MSHR miss cycles
704 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24361288501 # number of overall MSHR miss cycles
705 system.cpu.dcache.overall_mshr_miss_latency::total 24361288501 # number of overall MSHR miss cycles
706 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles
707 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles
708 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467826500 # number of WriteReq MSHR uncacheable cycles
709 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467826500 # number of WriteReq MSHR uncacheable cycles
710 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096503000 # number of overall MSHR uncacheable cycles
711 system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096503000 # number of overall MSHR uncacheable cycles
712 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098509 # mshr miss rate for ReadReq accesses
713 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098509 # mshr miss rate for ReadReq accesses
714 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037785 # mshr miss rate for WriteReq accesses
715 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037785 # mshr miss rate for WriteReq accesses
716 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for demand accesses
717 system.cpu.dcache.demand_mshr_miss_rate::total 0.075085 # mshr miss rate for demand accesses
718 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for overall accesses
719 system.cpu.dcache.overall_mshr_miss_rate::total 0.075085 # mshr miss rate for overall accesses
720 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391 # average ReadReq mshr miss latency
721 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391 # average ReadReq mshr miss latency
722 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750 # average WriteReq mshr miss latency
723 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750 # average WriteReq mshr miss latency
724 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency
725 system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency
726 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency
727 system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency
728 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
729 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
730 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
731 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
732 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
733 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
734 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
736 ---------- End Simulation Statistics ----------
projects / gem5.git / blob