2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.195470 # Number of seconds simulated
4 sim_ticks 5195470393000 # Number of ticks simulated
5 final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 792632 # Simulator instruction rate (inst/s)
8 host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 29811367673 # Simulator tick rate (ticks/s)
10 host_mem_usage 354100 # Number of bytes of host memory used
11 host_seconds 174.28 # Real time elapsed on the host
12 sim_insts 138138472 # Number of instructions simulated
13 sim_ops 265147881 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s)
49 system.l2c.replacements 136133 # number of replacements
50 system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
51 system.l2c.total_refs 3363370 # Total number of references to valid blocks.
52 system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
53 system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
54 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
55 system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor
56 system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor
57 system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor
58 system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor
59 system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor
60 system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy
61 system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy
62 system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
63 system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy
64 system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy
65 system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy
66 system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits
67 system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits
68 system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits
69 system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits
70 system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits
71 system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits
72 system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
73 system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits
74 system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
75 system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits
76 system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits
77 system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits
78 system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits
79 system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits
80 system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits
81 system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
82 system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits
83 system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits
84 system.l2c.overall_hits::cpu.inst 773419 # number of overall hits
85 system.l2c.overall_hits::cpu.data 1467421 # number of overall hits
86 system.l2c.overall_hits::total 2250401 # number of overall hits
87 system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses
88 system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses
89 system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses
90 system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses
91 system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses
92 system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses
93 system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
94 system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses
95 system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses
96 system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses
97 system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses
98 system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses
99 system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses
100 system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
101 system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses
102 system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses
103 system.l2c.overall_misses::cpu.inst 15226 # number of overall misses
104 system.l2c.overall_misses::cpu.data 155749 # number of overall misses
105 system.l2c.overall_misses::total 170998 # number of overall misses
106 system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles
107 system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles
108 system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles
109 system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles
110 system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles
111 system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles
112 system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles
113 system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles
114 system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles
115 system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles
116 system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles
117 system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles
118 system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles
119 system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles
120 system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles
121 system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles
122 system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles
123 system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles
124 system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles
125 system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses)
126 system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses)
127 system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses)
128 system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses)
129 system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses)
130 system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses)
131 system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
132 system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses)
133 system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
134 system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses)
135 system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses)
136 system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses
137 system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses
138 system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses
139 system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses
140 system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses
141 system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses
142 system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses
143 system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses
144 system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses
145 system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
146 system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses
147 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses
148 system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses
149 system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses
150 system.l2c.ReadReq_miss_rate::total 0.024110 # miss rate for ReadReq accesses
151 system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses
152 system.l2c.UpgradeReq_miss_rate::total 0.810539 # miss rate for UpgradeReq accesses
153 system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses
154 system.l2c.ReadExReq_miss_rate::total 0.383769 # miss rate for ReadExReq accesses
155 system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses
156 system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses
157 system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses
158 system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses
159 system.l2c.demand_miss_rate::total 0.070620 # miss rate for demand accesses
160 system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses
161 system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses
162 system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses
163 system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses
164 system.l2c.overall_miss_rate::total 0.070620 # miss rate for overall accesses
165 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
166 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
167 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency
168 system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency
169 system.l2c.ReadReq_avg_miss_latency::total 52255.016722 # average ReadReq miss latency
170 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency
171 system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295 # average UpgradeReq miss latency
172 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency
173 system.l2c.ReadExReq_avg_miss_latency::total 52004.897310 # average ReadExReq miss latency
174 system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
175 system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
176 system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency
177 system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency
178 system.l2c.demand_avg_miss_latency::total 52079.246541 # average overall miss latency
179 system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
180 system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
181 system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency
182 system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency
183 system.l2c.overall_avg_miss_latency::total 52079.246541 # average overall miss latency
184 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
185 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
186 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
187 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
188 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
189 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
190 system.l2c.fast_writes 0 # number of fast writes performed
191 system.l2c.cache_copies 0 # number of cache copies performed
192 system.l2c.writebacks::writebacks 116255 # number of writebacks
193 system.l2c.writebacks::total 116255 # number of writebacks
194 system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses
195 system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses
196 system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses
197 system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses
198 system.l2c.ReadReq_mshr_misses::total 50830 # number of ReadReq MSHR misses
199 system.l2c.UpgradeReq_mshr_misses::cpu.data 1369 # number of UpgradeReq MSHR misses
200 system.l2c.UpgradeReq_mshr_misses::total 1369 # number of UpgradeReq MSHR misses
201 system.l2c.ReadExReq_mshr_misses::cpu.data 120168 # number of ReadExReq MSHR misses
202 system.l2c.ReadExReq_mshr_misses::total 120168 # number of ReadExReq MSHR misses
203 system.l2c.demand_mshr_misses::cpu.dtb.walker 13 # number of demand (read+write) MSHR misses
204 system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses
205 system.l2c.demand_mshr_misses::cpu.inst 15226 # number of demand (read+write) MSHR misses
206 system.l2c.demand_mshr_misses::cpu.data 155749 # number of demand (read+write) MSHR misses
207 system.l2c.demand_mshr_misses::total 170998 # number of demand (read+write) MSHR misses
208 system.l2c.overall_mshr_misses::cpu.dtb.walker 13 # number of overall MSHR misses
209 system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses
210 system.l2c.overall_mshr_misses::cpu.inst 15226 # number of overall MSHR misses
211 system.l2c.overall_mshr_misses::cpu.data 155749 # number of overall MSHR misses
212 system.l2c.overall_mshr_misses::total 170998 # number of overall MSHR misses
213 system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 520000 # number of ReadReq MSHR miss cycles
214 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles
215 system.l2c.ReadReq_mshr_miss_latency::cpu.inst 609142000 # number of ReadReq MSHR miss cycles
216 system.l2c.ReadReq_mshr_miss_latency::cpu.data 1436082000 # number of ReadReq MSHR miss cycles
217 system.l2c.ReadReq_mshr_miss_latency::total 2046144000 # number of ReadReq MSHR miss cycles
218 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55109000 # number of UpgradeReq MSHR miss cycles
219 system.l2c.UpgradeReq_mshr_miss_latency::total 55109000 # number of UpgradeReq MSHR miss cycles
220 system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4807305000 # number of ReadExReq MSHR miss cycles
221 system.l2c.ReadExReq_mshr_miss_latency::total 4807305000 # number of ReadExReq MSHR miss cycles
222 system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 520000 # number of demand (read+write) MSHR miss cycles
223 system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles
224 system.l2c.demand_mshr_miss_latency::cpu.inst 609142000 # number of demand (read+write) MSHR miss cycles
225 system.l2c.demand_mshr_miss_latency::cpu.data 6243387000 # number of demand (read+write) MSHR miss cycles
226 system.l2c.demand_mshr_miss_latency::total 6853449000 # number of demand (read+write) MSHR miss cycles
227 system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 520000 # number of overall MSHR miss cycles
228 system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles
229 system.l2c.overall_mshr_miss_latency::cpu.inst 609142000 # number of overall MSHR miss cycles
230 system.l2c.overall_mshr_miss_latency::cpu.data 6243387000 # number of overall MSHR miss cycles
231 system.l2c.overall_mshr_miss_latency::total 6853449000 # number of overall MSHR miss cycles
232 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051785000 # number of ReadReq MSHR uncacheable cycles
233 system.l2c.ReadReq_mshr_uncacheable_latency::total 56051785000 # number of ReadReq MSHR uncacheable cycles
234 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218050000 # number of WriteReq MSHR uncacheable cycles
235 system.l2c.WriteReq_mshr_uncacheable_latency::total 1218050000 # number of WriteReq MSHR uncacheable cycles
236 system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269835000 # number of overall MSHR uncacheable cycles
237 system.l2c.overall_mshr_uncacheable_latency::total 57269835000 # number of overall MSHR uncacheable cycles
238 system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for ReadReq accesses
239 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses
240 system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses
241 system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses
242 system.l2c.ReadReq_mshr_miss_rate::total 0.024110 # mshr miss rate for ReadReq accesses
243 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses
244 system.l2c.UpgradeReq_mshr_miss_rate::total 0.810539 # mshr miss rate for UpgradeReq accesses
245 system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses
246 system.l2c.ReadExReq_mshr_miss_rate::total 0.383769 # mshr miss rate for ReadExReq accesses
247 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses
248 system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses
249 system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses
250 system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses
251 system.l2c.demand_mshr_miss_rate::total 0.070620 # mshr miss rate for demand accesses
252 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses
253 system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses
254 system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses
255 system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses
256 system.l2c.overall_mshr_miss_rate::total 0.070620 # mshr miss rate for overall accesses
257 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
258 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
259 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency
260 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency
261 system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764 # average ReadReq mshr miss latency
262 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency
263 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606 # average UpgradeReq mshr miss latency
264 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency
265 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185 # average ReadExReq mshr miss latency
266 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
267 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
268 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency
269 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency
270 system.l2c.demand_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency
271 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
272 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
273 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency
274 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency
275 system.l2c.overall_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency
276 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
277 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
278 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
279 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
280 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
281 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
282 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
283 system.iocache.replacements 47510 # number of replacements
284 system.iocache.tagsinuse 0.120586 # Cycle average of tags in use
285 system.iocache.total_refs 0 # Total number of references to valid blocks.
286 system.iocache.sampled_refs 47526 # Sample count of references to valid blocks.
287 system.iocache.avg_refs 0 # Average number of references to valid blocks.
288 system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
289 system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor
290 system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy
291 system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy
292 system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
293 system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
294 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
295 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
296 system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses
297 system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
298 system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
299 system.iocache.overall_misses::total 47564 # number of overall misses
300 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles
301 system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles
302 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles
303 system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles
304 system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles
305 system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles
306 system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles
307 system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles
308 system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
309 system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
310 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
311 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
312 system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
313 system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
314 system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses
315 system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
316 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
317 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
318 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
319 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
320 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
321 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
322 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
323 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
324 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency
325 system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency
326 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency
327 system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency
328 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency
329 system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency
330 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency
331 system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency
332 system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked
333 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
334 system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked
335 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
336 system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked
337 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
338 system.iocache.fast_writes 0 # number of fast writes performed
339 system.iocache.cache_copies 0 # number of cache copies performed
340 system.iocache.writebacks::writebacks 46668 # number of writebacks
341 system.iocache.writebacks::total 46668 # number of writebacks
342 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
343 system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
344 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
345 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
346 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses
347 system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
348 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
349 system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
350 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles
351 system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles
352 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles
353 system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles
354 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles
355 system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles
356 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles
357 system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles
358 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
359 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
360 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
361 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
362 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
363 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
364 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
365 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
366 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency
367 system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency
368 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency
369 system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency
370 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency
371 system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency
372 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency
373 system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency
374 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
375 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
376 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
377 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
378 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
379 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
380 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
381 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
382 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
383 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
384 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
385 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
386 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
387 system.cpu.numCycles 10390940786 # number of cpu cycles simulated
388 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
389 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
390 system.cpu.committedInsts 138138472 # Number of instructions committed
391 system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed
392 system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
393 system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
394 system.cpu.num_func_calls 0 # number of times a function call or return occured
395 system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls
396 system.cpu.num_int_insts 249556386 # number of integer instructions
397 system.cpu.num_fp_insts 0 # number of float instructions
398 system.cpu.num_int_register_reads 778086007 # number of times the integer registers were read
399 system.cpu.num_int_register_writes 422921187 # number of times the integer registers were written
400 system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
401 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
402 system.cpu.num_mem_refs 23169904 # number of memory refs
403 system.cpu.num_load_insts 14812525 # Number of load instructions
404 system.cpu.num_store_insts 8357379 # Number of store instructions
405 system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles
406 system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
407 system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles
408 system.cpu.idle_fraction 0.941953 # Percentage of idle cycles
409 system.cpu.kern.inst.arm 0 # number of arm instructions executed
410 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
411 system.cpu.icache.replacements 788139 # number of replacements
412 system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use
413 system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks.
414 system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks.
415 system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks.
416 system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit.
417 system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor
418 system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy
419 system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy
420 system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits
421 system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits
422 system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits
423 system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits
424 system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits
425 system.cpu.icache.overall_hits::total 158433932 # number of overall hits
426 system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses
427 system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses
428 system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses
429 system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses
430 system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses
431 system.cpu.icache.overall_misses::total 788658 # number of overall misses
432 system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles
433 system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles
434 system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles
435 system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles
436 system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles
437 system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles
438 system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses)
439 system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses)
440 system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses
441 system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses
442 system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses
443 system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses
444 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses
445 system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses
446 system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses
447 system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses
448 system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses
449 system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses
450 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency
451 system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency
452 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency
453 system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency
454 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency
455 system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency
456 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
457 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
458 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
459 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
460 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
461 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
462 system.cpu.icache.fast_writes 0 # number of fast writes performed
463 system.cpu.icache.cache_copies 0 # number of cache copies performed
464 system.cpu.icache.writebacks::writebacks 805 # number of writebacks
465 system.cpu.icache.writebacks::total 805 # number of writebacks
466 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses
467 system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses
468 system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses
469 system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses
470 system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses
471 system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses
472 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles
473 system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles
474 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles
475 system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles
476 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles
477 system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles
478 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses
479 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses
480 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses
481 system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses
482 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses
483 system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses
484 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency
485 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency
486 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency
487 system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency
488 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency
489 system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency
490 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
491 system.cpu.itb_walker_cache.replacements 3754 # number of replacements
492 system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
493 system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks.
494 system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks.
495 system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks.
496 system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit.
497 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor
498 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy
499 system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy
500 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits
501 system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits
502 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
503 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
504 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits
505 system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits
506 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits
507 system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits
508 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses
509 system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses
510 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses
511 system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses
512 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses
513 system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses
514 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles
515 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles
516 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles
517 system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles
518 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles
519 system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles
520 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses)
521 system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
522 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
523 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
524 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses
525 system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
526 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses
527 system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
528 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses
529 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses
530 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses
531 system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses
532 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses
533 system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses
534 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency
535 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency
536 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency
537 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency
538 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency
539 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency
540 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
541 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
542 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
543 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
544 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
545 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
546 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
547 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
548 system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks
549 system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks
550 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses
551 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses
552 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses
553 system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses
554 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses
555 system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses
556 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles
557 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles
558 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles
559 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles
560 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles
561 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles
562 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses
563 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses
564 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses
565 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses
566 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses
567 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses
568 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency
569 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency
570 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency
571 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency
572 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency
573 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency
574 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
575 system.cpu.dtb_walker_cache.replacements 7704 # number of replacements
576 system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use
577 system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks.
578 system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks.
579 system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks.
580 system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit.
581 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor
582 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy
583 system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy
584 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits
585 system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits
586 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits
587 system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits
588 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits
589 system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits
590 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses
591 system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses
592 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses
593 system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses
594 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses
595 system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses
596 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles
597 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles
598 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles
599 system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles
600 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles
601 system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles
602 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses)
603 system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses)
604 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses
605 system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses
606 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses
607 system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses
608 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses
609 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses
610 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses
611 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses
612 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses
613 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses
614 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency
615 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency
616 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency
617 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency
618 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency
619 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency
620 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
621 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
622 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
623 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
624 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
625 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
626 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
627 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
628 system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks
629 system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks
630 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses
631 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses
632 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses
633 system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses
634 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses
635 system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses
636 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles
637 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles
638 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles
639 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles
640 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles
641 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles
642 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses
643 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses
644 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses
645 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses
646 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses
647 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses
648 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency
649 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency
650 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency
651 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency
652 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency
653 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency
654 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
655 system.cpu.dcache.replacements 1623424 # number of replacements
656 system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use
657 system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks.
658 system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks.
659 system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks.
660 system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit.
661 system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor
662 system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
663 system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
664 system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits
665 system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits
666 system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits
667 system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits
668 system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits
669 system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits
670 system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits
671 system.cpu.dcache.overall_hits::total 20009191 # number of overall hits
672 system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses
673 system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses
674 system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses
675 system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses
676 system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses
677 system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses
678 system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses
679 system.cpu.dcache.overall_misses::total 1626168 # number of overall misses
680 system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles
681 system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles
682 system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles
683 system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles
684 system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles
685 system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles
686 system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles
687 system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles
688 system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses)
689 system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
690 system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses)
691 system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses)
692 system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses
693 system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses
694 system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses
695 system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses
696 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses
697 system.cpu.dcache.ReadReq_miss_rate::total 0.098647 # miss rate for ReadReq accesses
698 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses
699 system.cpu.dcache.WriteReq_miss_rate::total 0.037778 # miss rate for WriteReq accesses
700 system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses
701 system.cpu.dcache.demand_miss_rate::total 0.075163 # miss rate for demand accesses
702 system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses
703 system.cpu.dcache.overall_miss_rate::total 0.075163 # miss rate for overall accesses
704 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency
705 system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649 # average ReadReq miss latency
706 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency
707 system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044 # average WriteReq miss latency
708 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency
709 system.cpu.dcache.demand_avg_miss_latency::total 18058.802043 # average overall miss latency
710 system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency
711 system.cpu.dcache.overall_avg_miss_latency::total 18058.802043 # average overall miss latency
712 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
713 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
714 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
715 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
716 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
717 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
718 system.cpu.dcache.fast_writes 0 # number of fast writes performed
719 system.cpu.dcache.cache_copies 0 # number of cache copies performed
720 system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks
721 system.cpu.dcache.writebacks::total 1529951 # number of writebacks
722 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses
723 system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses
724 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses
725 system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses
726 system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses
727 system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses
728 system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses
729 system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses
730 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles
731 system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles
732 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles
733 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles
734 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles
735 system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles
736 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles
737 system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles
738 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles
739 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles
740 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles
741 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles
742 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles
743 system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles
744 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses
745 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098647 # mshr miss rate for ReadReq accesses
746 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses
747 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037778 # mshr miss rate for WriteReq accesses
748 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses
749 system.cpu.dcache.demand_mshr_miss_rate::total 0.075163 # mshr miss rate for demand accesses
750 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses
751 system.cpu.dcache.overall_mshr_miss_rate::total 0.075163 # mshr miss rate for overall accesses
752 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency
753 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227 # average ReadReq mshr miss latency
754 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency
755 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747 # average WriteReq mshr miss latency
756 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
757 system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency
758 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
759 system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency
760 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
761 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
762 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
763 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
764 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
765 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
766 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
768 ---------- End Simulation Statistics ----------
projects / gem5.git / blob