tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 exit_on_work_items=false
  19 init_param=0
  20 kernel=
  21 kernel_addr_check=true
  22 load_addr_mask=1099511627775
  23 load_offset=0
  24 mem_mode=timing
  25 mem_ranges=
  26 memories=system.physmem
  27 mmap_using_noreserve=false
  28 multi_thread=false
  29 num_work_ids=16
  30 readfile=
  31 symbolfile=
  32 work_begin_ckpt_count=0
  33 work_begin_cpu_id_exit=-1
  34 work_begin_exit_count=0
  35 work_cpus_ckpt_count=0
  36 work_end_ckpt_count=0
  37 work_end_exit_count=0
  38 work_item_id=-1
  39 system_port=system.membus.slave[0]
  40
  41 [system.clk_domain]
  42 type=SrcClockDomain
  43 clock=1000
  44 domain_id=-1
  45 eventq_index=0
  46 init_perf_level=0
  47 voltage_domain=system.voltage_domain
  48
  49 [system.cpu]
  50 type=MinorCPU
  51 children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
  52 branchPred=system.cpu.branchPred
  53 checker=Null
  54 clk_domain=system.cpu_clk_domain
  55 cpu_id=0
  56 decodeCycleInput=true
  57 decodeInputBufferSize=3
  58 decodeInputWidth=2
  59 decodeToExecuteForwardDelay=1
  60 do_checkpoint_insts=true
  61 do_quiesce=true
  62 do_statistics_insts=true
  63 dtb=system.cpu.dtb
  64 enableIdling=true
  65 eventq_index=0
  66 executeAllowEarlyMemoryIssue=true
  67 executeBranchDelay=1
  68 executeCommitLimit=2
  69 executeCycleInput=true
  70 executeFuncUnits=system.cpu.executeFuncUnits
  71 executeInputBufferSize=7
  72 executeInputWidth=2
  73 executeIssueLimit=2
  74 executeLSQMaxStoreBufferStoresPerCycle=2
  75 executeLSQRequestsQueueSize=1
  76 executeLSQStoreBufferSize=5
  77 executeLSQTransfersQueueSize=2
  78 executeMaxAccessesInMemory=2
  79 executeMemoryCommitLimit=1
  80 executeMemoryIssueLimit=1
  81 executeMemoryWidth=0
  82 executeSetTraceTimeOnCommit=true
  83 executeSetTraceTimeOnIssue=false
  84 fetch1FetchLimit=1
  85 fetch1LineSnapWidth=0
  86 fetch1LineWidth=0
  87 fetch1ToFetch2BackwardDelay=1
  88 fetch1ToFetch2ForwardDelay=1
  89 fetch2CycleInput=true
  90 fetch2InputBufferSize=2
  91 fetch2ToDecodeForwardDelay=1
  92 function_trace=false
  93 function_trace_start=0
  94 interrupts=system.cpu.interrupts
  95 isa=system.cpu.isa
  96 itb=system.cpu.itb
  97 max_insts_all_threads=0
  98 max_insts_any_thread=0
  99 max_loads_all_threads=0
 100 max_loads_any_thread=0
 101 numThreads=1
 102 profile=0
 103 progress_interval=0
 104 simpoint_start_insts=
 105 socket_id=0
 106 switched_out=false
 107 system=system
 108 tracer=system.cpu.tracer
 109 workload=system.cpu.workload
 110 dcache_port=system.cpu.dcache.cpu_side
 111 icache_port=system.cpu.icache.cpu_side
 112
 113 [system.cpu.branchPred]
 114 type=TournamentBP
 115 BTBEntries=4096
 116 BTBTagSize=16
 117 RASSize=16
 118 choiceCtrBits=2
 119 choicePredictorSize=8192
 120 eventq_index=0
 121 globalCtrBits=2
 122 globalPredictorSize=8192
 123 instShiftAmt=2
 124 localCtrBits=2
 125 localHistoryTableSize=2048
 126 localPredictorSize=2048
 127 numThreads=1
 128
 129 [system.cpu.dcache]
 130 type=Cache
 131 children=tags
 132 addr_ranges=0:18446744073709551615
 133 assoc=2
 134 clk_domain=system.cpu_clk_domain
 135 clusivity=mostly_incl
 136 demand_mshr_reserve=1
 137 eventq_index=0
 138 forward_snoops=true
 139 hit_latency=2
 140 is_read_only=false
 141 max_miss_count=0
 142 mshrs=4
 143 prefetch_on_access=false
 144 prefetcher=Null
 145 response_latency=2
 146 sequential_access=false
 147 size=262144
 148 system=system
 149 tags=system.cpu.dcache.tags
 150 tgts_per_mshr=20
 151 write_buffers=8
 152 writeback_clean=false
 153 cpu_side=system.cpu.dcache_port
 154 mem_side=system.cpu.toL2Bus.slave[1]
 155
 156 [system.cpu.dcache.tags]
 157 type=LRU
 158 assoc=2
 159 block_size=64
 160 clk_domain=system.cpu_clk_domain
 161 eventq_index=0
 162 hit_latency=2
 163 sequential_access=false
 164 size=262144
 165
 166 [system.cpu.dtb]
 167 type=AlphaTLB
 168 eventq_index=0
 169 size=64
 170
 171 [system.cpu.executeFuncUnits]
 172 type=MinorFUPool
 173 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 174 eventq_index=0
 175 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 176
 177 [system.cpu.executeFuncUnits.funcUnits0]
 178 type=MinorFU
 179 children=opClasses timings
 180 cantForwardFromFUIndices=
 181 eventq_index=0
 182 issueLat=1
 183 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 184 opLat=3
 185 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 186
 187 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 188 type=MinorOpClassSet
 189 children=opClasses
 190 eventq_index=0
 191 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 192
 193 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 194 type=MinorOpClass
 195 eventq_index=0
 196 opClass=IntAlu
 197
 198 [system.cpu.executeFuncUnits.funcUnits0.timings]
 199 type=MinorFUTiming
 200 children=opClasses
 201 description=Int
 202 eventq_index=0
 203 extraAssumedLat=0
 204 extraCommitLat=0
 205 extraCommitLatExpr=Null
 206 mask=0
 207 match=0
 208 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 209 srcRegsRelativeLats=2
 210 suppress=false
 211
 212 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 213 type=MinorOpClassSet
 214 eventq_index=0
 215 opClasses=
 216
 217 [system.cpu.executeFuncUnits.funcUnits1]
 218 type=MinorFU
 219 children=opClasses timings
 220 cantForwardFromFUIndices=
 221 eventq_index=0
 222 issueLat=1
 223 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 224 opLat=3
 225 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 226
 227 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 228 type=MinorOpClassSet
 229 children=opClasses
 230 eventq_index=0
 231 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 232
 233 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 234 type=MinorOpClass
 235 eventq_index=0
 236 opClass=IntAlu
 237
 238 [system.cpu.executeFuncUnits.funcUnits1.timings]
 239 type=MinorFUTiming
 240 children=opClasses
 241 description=Int
 242 eventq_index=0
 243 extraAssumedLat=0
 244 extraCommitLat=0
 245 extraCommitLatExpr=Null
 246 mask=0
 247 match=0
 248 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 249 srcRegsRelativeLats=2
 250 suppress=false
 251
 252 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 253 type=MinorOpClassSet
 254 eventq_index=0
 255 opClasses=
 256
 257 [system.cpu.executeFuncUnits.funcUnits2]
 258 type=MinorFU
 259 children=opClasses timings
 260 cantForwardFromFUIndices=
 261 eventq_index=0
 262 issueLat=1
 263 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 264 opLat=3
 265 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 266
 267 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 268 type=MinorOpClassSet
 269 children=opClasses
 270 eventq_index=0
 271 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 272
 273 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 274 type=MinorOpClass
 275 eventq_index=0
 276 opClass=IntMult
 277
 278 [system.cpu.executeFuncUnits.funcUnits2.timings]
 279 type=MinorFUTiming
 280 children=opClasses
 281 description=Mul
 282 eventq_index=0
 283 extraAssumedLat=0
 284 extraCommitLat=0
 285 extraCommitLatExpr=Null
 286 mask=0
 287 match=0
 288 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 289 srcRegsRelativeLats=0
 290 suppress=false
 291
 292 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 293 type=MinorOpClassSet
 294 eventq_index=0
 295 opClasses=
 296
 297 [system.cpu.executeFuncUnits.funcUnits3]
 298 type=MinorFU
 299 children=opClasses
 300 cantForwardFromFUIndices=
 301 eventq_index=0
 302 issueLat=9
 303 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 304 opLat=9
 305 timings=
 306
 307 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 308 type=MinorOpClassSet
 309 children=opClasses
 310 eventq_index=0
 311 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 312
 313 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 314 type=MinorOpClass
 315 eventq_index=0
 316 opClass=IntDiv
 317
 318 [system.cpu.executeFuncUnits.funcUnits4]
 319 type=MinorFU
 320 children=opClasses timings
 321 cantForwardFromFUIndices=
 322 eventq_index=0
 323 issueLat=1
 324 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 325 opLat=6
 326 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 327
 328 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 329 type=MinorOpClassSet
 330 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 331 eventq_index=0
 332 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 333
 334 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 335 type=MinorOpClass
 336 eventq_index=0
 337 opClass=FloatAdd
 338
 339 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 340 type=MinorOpClass
 341 eventq_index=0
 342 opClass=FloatCmp
 343
 344 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 345 type=MinorOpClass
 346 eventq_index=0
 347 opClass=FloatCvt
 348
 349 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 350 type=MinorOpClass
 351 eventq_index=0
 352 opClass=FloatMult
 353
 354 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 355 type=MinorOpClass
 356 eventq_index=0
 357 opClass=FloatDiv
 358
 359 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 360 type=MinorOpClass
 361 eventq_index=0
 362 opClass=FloatSqrt
 363
 364 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 365 type=MinorOpClass
 366 eventq_index=0
 367 opClass=SimdAdd
 368
 369 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 370 type=MinorOpClass
 371 eventq_index=0
 372 opClass=SimdAddAcc
 373
 374 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 375 type=MinorOpClass
 376 eventq_index=0
 377 opClass=SimdAlu
 378
 379 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 380 type=MinorOpClass
 381 eventq_index=0
 382 opClass=SimdCmp
 383
 384 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 385 type=MinorOpClass
 386 eventq_index=0
 387 opClass=SimdCvt
 388
 389 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 390 type=MinorOpClass
 391 eventq_index=0
 392 opClass=SimdMisc
 393
 394 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 395 type=MinorOpClass
 396 eventq_index=0
 397 opClass=SimdMult
 398
 399 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 400 type=MinorOpClass
 401 eventq_index=0
 402 opClass=SimdMultAcc
 403
 404 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 405 type=MinorOpClass
 406 eventq_index=0
 407 opClass=SimdShift
 408
 409 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 410 type=MinorOpClass
 411 eventq_index=0
 412 opClass=SimdShiftAcc
 413
 414 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 415 type=MinorOpClass
 416 eventq_index=0
 417 opClass=SimdSqrt
 418
 419 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 420 type=MinorOpClass
 421 eventq_index=0
 422 opClass=SimdFloatAdd
 423
 424 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 425 type=MinorOpClass
 426 eventq_index=0
 427 opClass=SimdFloatAlu
 428
 429 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 430 type=MinorOpClass
 431 eventq_index=0
 432 opClass=SimdFloatCmp
 433
 434 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 435 type=MinorOpClass
 436 eventq_index=0
 437 opClass=SimdFloatCvt
 438
 439 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 440 type=MinorOpClass
 441 eventq_index=0
 442 opClass=SimdFloatDiv
 443
 444 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 445 type=MinorOpClass
 446 eventq_index=0
 447 opClass=SimdFloatMisc
 448
 449 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 450 type=MinorOpClass
 451 eventq_index=0
 452 opClass=SimdFloatMult
 453
 454 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 455 type=MinorOpClass
 456 eventq_index=0
 457 opClass=SimdFloatMultAcc
 458
 459 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 460 type=MinorOpClass
 461 eventq_index=0
 462 opClass=SimdFloatSqrt
 463
 464 [system.cpu.executeFuncUnits.funcUnits4.timings]
 465 type=MinorFUTiming
 466 children=opClasses
 467 description=FloatSimd
 468 eventq_index=0
 469 extraAssumedLat=0
 470 extraCommitLat=0
 471 extraCommitLatExpr=Null
 472 mask=0
 473 match=0
 474 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 475 srcRegsRelativeLats=2
 476 suppress=false
 477
 478 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 479 type=MinorOpClassSet
 480 eventq_index=0
 481 opClasses=
 482
 483 [system.cpu.executeFuncUnits.funcUnits5]
 484 type=MinorFU
 485 children=opClasses timings
 486 cantForwardFromFUIndices=
 487 eventq_index=0
 488 issueLat=1
 489 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 490 opLat=1
 491 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 492
 493 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 494 type=MinorOpClassSet
 495 children=opClasses0 opClasses1
 496 eventq_index=0
 497 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 498
 499 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 500 type=MinorOpClass
 501 eventq_index=0
 502 opClass=MemRead
 503
 504 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 505 type=MinorOpClass
 506 eventq_index=0
 507 opClass=MemWrite
 508
 509 [system.cpu.executeFuncUnits.funcUnits5.timings]
 510 type=MinorFUTiming
 511 children=opClasses
 512 description=Mem
 513 eventq_index=0
 514 extraAssumedLat=2
 515 extraCommitLat=0
 516 extraCommitLatExpr=Null
 517 mask=0
 518 match=0
 519 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 520 srcRegsRelativeLats=1
 521 suppress=false
 522
 523 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 524 type=MinorOpClassSet
 525 eventq_index=0
 526 opClasses=
 527
 528 [system.cpu.executeFuncUnits.funcUnits6]
 529 type=MinorFU
 530 children=opClasses
 531 cantForwardFromFUIndices=
 532 eventq_index=0
 533 issueLat=1
 534 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 535 opLat=1
 536 timings=
 537
 538 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 539 type=MinorOpClassSet
 540 children=opClasses0 opClasses1
 541 eventq_index=0
 542 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 543
 544 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 545 type=MinorOpClass
 546 eventq_index=0
 547 opClass=IprAccess
 548
 549 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 550 type=MinorOpClass
 551 eventq_index=0
 552 opClass=InstPrefetch
 553
 554 [system.cpu.icache]
 555 type=Cache
 556 children=tags
 557 addr_ranges=0:18446744073709551615
 558 assoc=2
 559 clk_domain=system.cpu_clk_domain
 560 clusivity=mostly_incl
 561 demand_mshr_reserve=1
 562 eventq_index=0
 563 forward_snoops=true
 564 hit_latency=2
 565 is_read_only=true
 566 max_miss_count=0
 567 mshrs=4
 568 prefetch_on_access=false
 569 prefetcher=Null
 570 response_latency=2
 571 sequential_access=false
 572 size=131072
 573 system=system
 574 tags=system.cpu.icache.tags
 575 tgts_per_mshr=20
 576 write_buffers=8
 577 writeback_clean=true
 578 cpu_side=system.cpu.icache_port
 579 mem_side=system.cpu.toL2Bus.slave[0]
 580
 581 [system.cpu.icache.tags]
 582 type=LRU
 583 assoc=2
 584 block_size=64
 585 clk_domain=system.cpu_clk_domain
 586 eventq_index=0
 587 hit_latency=2
 588 sequential_access=false
 589 size=131072
 590
 591 [system.cpu.interrupts]
 592 type=AlphaInterrupts
 593 eventq_index=0
 594
 595 [system.cpu.isa]
 596 type=AlphaISA
 597 eventq_index=0
 598 system=system
 599
 600 [system.cpu.itb]
 601 type=AlphaTLB
 602 eventq_index=0
 603 size=48
 604
 605 [system.cpu.l2cache]
 606 type=Cache
 607 children=tags
 608 addr_ranges=0:18446744073709551615
 609 assoc=8
 610 clk_domain=system.cpu_clk_domain
 611 clusivity=mostly_incl
 612 demand_mshr_reserve=1
 613 eventq_index=0
 614 forward_snoops=true
 615 hit_latency=20
 616 is_read_only=false
 617 max_miss_count=0
 618 mshrs=20
 619 prefetch_on_access=false
 620 prefetcher=Null
 621 response_latency=20
 622 sequential_access=false
 623 size=2097152
 624 system=system
 625 tags=system.cpu.l2cache.tags
 626 tgts_per_mshr=12
 627 write_buffers=8
 628 writeback_clean=false
 629 cpu_side=system.cpu.toL2Bus.master[0]
 630 mem_side=system.membus.slave[1]
 631
 632 [system.cpu.l2cache.tags]
 633 type=LRU
 634 assoc=8
 635 block_size=64
 636 clk_domain=system.cpu_clk_domain
 637 eventq_index=0
 638 hit_latency=20
 639 sequential_access=false
 640 size=2097152
 641
 642 [system.cpu.toL2Bus]
 643 type=CoherentXBar
 644 children=snoop_filter
 645 clk_domain=system.cpu_clk_domain
 646 eventq_index=0
 647 forward_latency=0
 648 frontend_latency=1
 649 response_latency=1
 650 snoop_filter=system.cpu.toL2Bus.snoop_filter
 651 snoop_response_latency=1
 652 system=system
 653 use_default_range=false
 654 width=32
 655 master=system.cpu.l2cache.cpu_side
 656 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 657
 658 [system.cpu.toL2Bus.snoop_filter]
 659 type=SnoopFilter
 660 eventq_index=0
 661 lookup_latency=0
 662 max_capacity=8388608
 663 system=system
 664
 665 [system.cpu.tracer]
 666 type=ExeTracer
 667 eventq_index=0
 668
 669 [system.cpu.workload]
 670 type=LiveProcess
 671 cmd=hello
 672 cwd=
 673 drivers=
 674 egid=100
 675 env=
 676 errout=cerr
 677 euid=100
 678 eventq_index=0
 679 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 680 gid=100
 681 input=cin
 682 kvmInSE=false
 683 max_stack_size=67108864
 684 output=cout
 685 pid=100
 686 ppid=99
 687 simpoint=0
 688 system=system
 689 uid=100
 690 useArchPT=false
 691
 692 [system.cpu_clk_domain]
 693 type=SrcClockDomain
 694 clock=500
 695 domain_id=-1
 696 eventq_index=0
 697 init_perf_level=0
 698 voltage_domain=system.voltage_domain
 699
 700 [system.dvfs_handler]
 701 type=DVFSHandler
 702 domains=
 703 enable=false
 704 eventq_index=0
 705 sys_clk_domain=system.clk_domain
 706 transition_latency=100000000
 707
 708 [system.membus]
 709 type=CoherentXBar
 710 clk_domain=system.clk_domain
 711 eventq_index=0
 712 forward_latency=4
 713 frontend_latency=3
 714 response_latency=2
 715 snoop_filter=Null
 716 snoop_response_latency=4
 717 system=system
 718 use_default_range=false
 719 width=16
 720 master=system.physmem.port
 721 slave=system.system_port system.cpu.l2cache.mem_side
 722
 723 [system.physmem]
 724 type=DRAMCtrl
 725 IDD0=0.075000
 726 IDD02=0.000000
 727 IDD2N=0.050000
 728 IDD2N2=0.000000
 729 IDD2P0=0.000000
 730 IDD2P02=0.000000
 731 IDD2P1=0.000000
 732 IDD2P12=0.000000
 733 IDD3N=0.057000
 734 IDD3N2=0.000000
 735 IDD3P0=0.000000
 736 IDD3P02=0.000000
 737 IDD3P1=0.000000
 738 IDD3P12=0.000000
 739 IDD4R=0.187000
 740 IDD4R2=0.000000
 741 IDD4W=0.165000
 742 IDD4W2=0.000000
 743 IDD5=0.220000
 744 IDD52=0.000000
 745 IDD6=0.000000
 746 IDD62=0.000000
 747 VDD=1.500000
 748 VDD2=0.000000
 749 activation_limit=4
 750 addr_mapping=RoRaBaCoCh
 751 bank_groups_per_rank=0
 752 banks_per_rank=8
 753 burst_length=8
 754 channels=1
 755 clk_domain=system.clk_domain
 756 conf_table_reported=true
 757 device_bus_width=8
 758 device_rowbuffer_size=1024
 759 device_size=536870912
 760 devices_per_rank=8
 761 dll=true
 762 eventq_index=0
 763 in_addr_map=true
 764 max_accesses_per_row=16
 765 mem_sched_policy=frfcfs
 766 min_writes_per_switch=16
 767 null=false
 768 page_policy=open_adaptive
 769 range=0:134217727
 770 ranks_per_channel=2
 771 read_buffer_size=32
 772 static_backend_latency=10000
 773 static_frontend_latency=10000
 774 tBURST=5000
 775 tCCD_L=0
 776 tCK=1250
 777 tCL=13750
 778 tCS=2500
 779 tRAS=35000
 780 tRCD=13750
 781 tREFI=7800000
 782 tRFC=260000
 783 tRP=13750
 784 tRRD=6000
 785 tRRD_L=0
 786 tRTP=7500
 787 tRTW=2500
 788 tWR=15000
 789 tWTR=7500
 790 tXAW=30000
 791 tXP=0
 792 tXPDLL=0
 793 tXS=0
 794 tXSDLL=0
 795 write_buffer_size=64
 796 write_high_thresh_perc=85
 797 write_low_thresh_perc=50
 798 port=system.membus.master[0]
 799
 800 [system.voltage_domain]
 801 type=VoltageDomain
 802 eventq_index=0
 803 voltage=1.000000
 804