tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu]
  49 type=MinorCPU
  50 children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
  51 branchPred=system.cpu.branchPred
  52 checker=Null
  53 clk_domain=system.cpu_clk_domain
  54 cpu_id=0
  55 decodeCycleInput=true
  56 decodeInputBufferSize=3
  57 decodeInputWidth=2
  58 decodeToExecuteForwardDelay=1
  59 do_checkpoint_insts=true
  60 do_quiesce=true
  61 do_statistics_insts=true
  62 dtb=system.cpu.dtb
  63 enableIdling=true
  64 eventq_index=0
  65 executeAllowEarlyMemoryIssue=true
  66 executeBranchDelay=1
  67 executeCommitLimit=2
  68 executeCycleInput=true
  69 executeFuncUnits=system.cpu.executeFuncUnits
  70 executeInputBufferSize=7
  71 executeInputWidth=2
  72 executeIssueLimit=2
  73 executeLSQMaxStoreBufferStoresPerCycle=2
  74 executeLSQRequestsQueueSize=1
  75 executeLSQStoreBufferSize=5
  76 executeLSQTransfersQueueSize=2
  77 executeMaxAccessesInMemory=2
  78 executeMemoryCommitLimit=1
  79 executeMemoryIssueLimit=1
  80 executeMemoryWidth=0
  81 executeSetTraceTimeOnCommit=true
  82 executeSetTraceTimeOnIssue=false
  83 fetch1FetchLimit=1
  84 fetch1LineSnapWidth=0
  85 fetch1LineWidth=0
  86 fetch1ToFetch2BackwardDelay=1
  87 fetch1ToFetch2ForwardDelay=1
  88 fetch2CycleInput=true
  89 fetch2InputBufferSize=2
  90 fetch2ToDecodeForwardDelay=1
  91 function_trace=false
  92 function_trace_start=0
  93 interrupts=system.cpu.interrupts
  94 isa=system.cpu.isa
  95 itb=system.cpu.itb
  96 max_insts_all_threads=0
  97 max_insts_any_thread=0
  98 max_loads_all_threads=0
  99 max_loads_any_thread=0
 100 numThreads=1
 101 profile=0
 102 progress_interval=0
 103 simpoint_start_insts=
 104 socket_id=0
 105 switched_out=false
 106 system=system
 107 tracer=system.cpu.tracer
 108 workload=system.cpu.workload
 109 dcache_port=system.cpu.dcache.cpu_side
 110 icache_port=system.cpu.icache.cpu_side
 111
 112 [system.cpu.branchPred]
 113 type=TournamentBP
 114 BTBEntries=4096
 115 BTBTagSize=16
 116 RASSize=16
 117 choiceCtrBits=2
 118 choicePredictorSize=8192
 119 eventq_index=0
 120 globalCtrBits=2
 121 globalPredictorSize=8192
 122 instShiftAmt=2
 123 localCtrBits=2
 124 localHistoryTableSize=2048
 125 localPredictorSize=2048
 126 numThreads=1
 127
 128 [system.cpu.dcache]
 129 type=Cache
 130 children=tags
 131 addr_ranges=0:18446744073709551615
 132 assoc=2
 133 clk_domain=system.cpu_clk_domain
 134 clusivity=mostly_incl
 135 demand_mshr_reserve=1
 136 eventq_index=0
 137 forward_snoops=true
 138 hit_latency=2
 139 is_read_only=false
 140 max_miss_count=0
 141 mshrs=4
 142 prefetch_on_access=false
 143 prefetcher=Null
 144 response_latency=2
 145 sequential_access=false
 146 size=262144
 147 system=system
 148 tags=system.cpu.dcache.tags
 149 tgts_per_mshr=20
 150 write_buffers=8
 151 writeback_clean=false
 152 cpu_side=system.cpu.dcache_port
 153 mem_side=system.cpu.toL2Bus.slave[1]
 154
 155 [system.cpu.dcache.tags]
 156 type=LRU
 157 assoc=2
 158 block_size=64
 159 clk_domain=system.cpu_clk_domain
 160 eventq_index=0
 161 hit_latency=2
 162 sequential_access=false
 163 size=262144
 164
 165 [system.cpu.dtb]
 166 type=AlphaTLB
 167 eventq_index=0
 168 size=64
 169
 170 [system.cpu.executeFuncUnits]
 171 type=MinorFUPool
 172 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 173 eventq_index=0
 174 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 175
 176 [system.cpu.executeFuncUnits.funcUnits0]
 177 type=MinorFU
 178 children=opClasses timings
 179 cantForwardFromFUIndices=
 180 eventq_index=0
 181 issueLat=1
 182 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 183 opLat=3
 184 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 185
 186 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 187 type=MinorOpClassSet
 188 children=opClasses
 189 eventq_index=0
 190 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 191
 192 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 193 type=MinorOpClass
 194 eventq_index=0
 195 opClass=IntAlu
 196
 197 [system.cpu.executeFuncUnits.funcUnits0.timings]
 198 type=MinorFUTiming
 199 children=opClasses
 200 description=Int
 201 eventq_index=0
 202 extraAssumedLat=0
 203 extraCommitLat=0
 204 extraCommitLatExpr=Null
 205 mask=0
 206 match=0
 207 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 208 srcRegsRelativeLats=2
 209 suppress=false
 210
 211 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 212 type=MinorOpClassSet
 213 eventq_index=0
 214 opClasses=
 215
 216 [system.cpu.executeFuncUnits.funcUnits1]
 217 type=MinorFU
 218 children=opClasses timings
 219 cantForwardFromFUIndices=
 220 eventq_index=0
 221 issueLat=1
 222 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 223 opLat=3
 224 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 225
 226 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 227 type=MinorOpClassSet
 228 children=opClasses
 229 eventq_index=0
 230 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 231
 232 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 233 type=MinorOpClass
 234 eventq_index=0
 235 opClass=IntAlu
 236
 237 [system.cpu.executeFuncUnits.funcUnits1.timings]
 238 type=MinorFUTiming
 239 children=opClasses
 240 description=Int
 241 eventq_index=0
 242 extraAssumedLat=0
 243 extraCommitLat=0
 244 extraCommitLatExpr=Null
 245 mask=0
 246 match=0
 247 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 248 srcRegsRelativeLats=2
 249 suppress=false
 250
 251 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 252 type=MinorOpClassSet
 253 eventq_index=0
 254 opClasses=
 255
 256 [system.cpu.executeFuncUnits.funcUnits2]
 257 type=MinorFU
 258 children=opClasses timings
 259 cantForwardFromFUIndices=
 260 eventq_index=0
 261 issueLat=1
 262 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 263 opLat=3
 264 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 265
 266 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 267 type=MinorOpClassSet
 268 children=opClasses
 269 eventq_index=0
 270 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 271
 272 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 273 type=MinorOpClass
 274 eventq_index=0
 275 opClass=IntMult
 276
 277 [system.cpu.executeFuncUnits.funcUnits2.timings]
 278 type=MinorFUTiming
 279 children=opClasses
 280 description=Mul
 281 eventq_index=0
 282 extraAssumedLat=0
 283 extraCommitLat=0
 284 extraCommitLatExpr=Null
 285 mask=0
 286 match=0
 287 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 288 srcRegsRelativeLats=0
 289 suppress=false
 290
 291 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 292 type=MinorOpClassSet
 293 eventq_index=0
 294 opClasses=
 295
 296 [system.cpu.executeFuncUnits.funcUnits3]
 297 type=MinorFU
 298 children=opClasses
 299 cantForwardFromFUIndices=
 300 eventq_index=0
 301 issueLat=9
 302 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 303 opLat=9
 304 timings=
 305
 306 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 307 type=MinorOpClassSet
 308 children=opClasses
 309 eventq_index=0
 310 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 311
 312 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 313 type=MinorOpClass
 314 eventq_index=0
 315 opClass=IntDiv
 316
 317 [system.cpu.executeFuncUnits.funcUnits4]
 318 type=MinorFU
 319 children=opClasses timings
 320 cantForwardFromFUIndices=
 321 eventq_index=0
 322 issueLat=1
 323 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 324 opLat=6
 325 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 326
 327 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 328 type=MinorOpClassSet
 329 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 330 eventq_index=0
 331 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 332
 333 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 334 type=MinorOpClass
 335 eventq_index=0
 336 opClass=FloatAdd
 337
 338 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 339 type=MinorOpClass
 340 eventq_index=0
 341 opClass=FloatCmp
 342
 343 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 344 type=MinorOpClass
 345 eventq_index=0
 346 opClass=FloatCvt
 347
 348 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 349 type=MinorOpClass
 350 eventq_index=0
 351 opClass=FloatMult
 352
 353 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 354 type=MinorOpClass
 355 eventq_index=0
 356 opClass=FloatDiv
 357
 358 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 359 type=MinorOpClass
 360 eventq_index=0
 361 opClass=FloatSqrt
 362
 363 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 364 type=MinorOpClass
 365 eventq_index=0
 366 opClass=SimdAdd
 367
 368 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 369 type=MinorOpClass
 370 eventq_index=0
 371 opClass=SimdAddAcc
 372
 373 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 374 type=MinorOpClass
 375 eventq_index=0
 376 opClass=SimdAlu
 377
 378 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 379 type=MinorOpClass
 380 eventq_index=0
 381 opClass=SimdCmp
 382
 383 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 384 type=MinorOpClass
 385 eventq_index=0
 386 opClass=SimdCvt
 387
 388 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 389 type=MinorOpClass
 390 eventq_index=0
 391 opClass=SimdMisc
 392
 393 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 394 type=MinorOpClass
 395 eventq_index=0
 396 opClass=SimdMult
 397
 398 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 399 type=MinorOpClass
 400 eventq_index=0
 401 opClass=SimdMultAcc
 402
 403 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 404 type=MinorOpClass
 405 eventq_index=0
 406 opClass=SimdShift
 407
 408 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 409 type=MinorOpClass
 410 eventq_index=0
 411 opClass=SimdShiftAcc
 412
 413 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 414 type=MinorOpClass
 415 eventq_index=0
 416 opClass=SimdSqrt
 417
 418 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 419 type=MinorOpClass
 420 eventq_index=0
 421 opClass=SimdFloatAdd
 422
 423 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 424 type=MinorOpClass
 425 eventq_index=0
 426 opClass=SimdFloatAlu
 427
 428 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 429 type=MinorOpClass
 430 eventq_index=0
 431 opClass=SimdFloatCmp
 432
 433 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 434 type=MinorOpClass
 435 eventq_index=0
 436 opClass=SimdFloatCvt
 437
 438 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 439 type=MinorOpClass
 440 eventq_index=0
 441 opClass=SimdFloatDiv
 442
 443 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 444 type=MinorOpClass
 445 eventq_index=0
 446 opClass=SimdFloatMisc
 447
 448 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 449 type=MinorOpClass
 450 eventq_index=0
 451 opClass=SimdFloatMult
 452
 453 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 454 type=MinorOpClass
 455 eventq_index=0
 456 opClass=SimdFloatMultAcc
 457
 458 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 459 type=MinorOpClass
 460 eventq_index=0
 461 opClass=SimdFloatSqrt
 462
 463 [system.cpu.executeFuncUnits.funcUnits4.timings]
 464 type=MinorFUTiming
 465 children=opClasses
 466 description=FloatSimd
 467 eventq_index=0
 468 extraAssumedLat=0
 469 extraCommitLat=0
 470 extraCommitLatExpr=Null
 471 mask=0
 472 match=0
 473 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 474 srcRegsRelativeLats=2
 475 suppress=false
 476
 477 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 478 type=MinorOpClassSet
 479 eventq_index=0
 480 opClasses=
 481
 482 [system.cpu.executeFuncUnits.funcUnits5]
 483 type=MinorFU
 484 children=opClasses timings
 485 cantForwardFromFUIndices=
 486 eventq_index=0
 487 issueLat=1
 488 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 489 opLat=1
 490 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 491
 492 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 493 type=MinorOpClassSet
 494 children=opClasses0 opClasses1
 495 eventq_index=0
 496 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 497
 498 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 499 type=MinorOpClass
 500 eventq_index=0
 501 opClass=MemRead
 502
 503 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 504 type=MinorOpClass
 505 eventq_index=0
 506 opClass=MemWrite
 507
 508 [system.cpu.executeFuncUnits.funcUnits5.timings]
 509 type=MinorFUTiming
 510 children=opClasses
 511 description=Mem
 512 eventq_index=0
 513 extraAssumedLat=2
 514 extraCommitLat=0
 515 extraCommitLatExpr=Null
 516 mask=0
 517 match=0
 518 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 519 srcRegsRelativeLats=1
 520 suppress=false
 521
 522 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 523 type=MinorOpClassSet
 524 eventq_index=0
 525 opClasses=
 526
 527 [system.cpu.executeFuncUnits.funcUnits6]
 528 type=MinorFU
 529 children=opClasses
 530 cantForwardFromFUIndices=
 531 eventq_index=0
 532 issueLat=1
 533 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 534 opLat=1
 535 timings=
 536
 537 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 538 type=MinorOpClassSet
 539 children=opClasses0 opClasses1
 540 eventq_index=0
 541 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 542
 543 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 544 type=MinorOpClass
 545 eventq_index=0
 546 opClass=IprAccess
 547
 548 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 549 type=MinorOpClass
 550 eventq_index=0
 551 opClass=InstPrefetch
 552
 553 [system.cpu.icache]
 554 type=Cache
 555 children=tags
 556 addr_ranges=0:18446744073709551615
 557 assoc=2
 558 clk_domain=system.cpu_clk_domain
 559 clusivity=mostly_incl
 560 demand_mshr_reserve=1
 561 eventq_index=0
 562 forward_snoops=true
 563 hit_latency=2
 564 is_read_only=true
 565 max_miss_count=0
 566 mshrs=4
 567 prefetch_on_access=false
 568 prefetcher=Null
 569 response_latency=2
 570 sequential_access=false
 571 size=131072
 572 system=system
 573 tags=system.cpu.icache.tags
 574 tgts_per_mshr=20
 575 write_buffers=8
 576 writeback_clean=true
 577 cpu_side=system.cpu.icache_port
 578 mem_side=system.cpu.toL2Bus.slave[0]
 579
 580 [system.cpu.icache.tags]
 581 type=LRU
 582 assoc=2
 583 block_size=64
 584 clk_domain=system.cpu_clk_domain
 585 eventq_index=0
 586 hit_latency=2
 587 sequential_access=false
 588 size=131072
 589
 590 [system.cpu.interrupts]
 591 type=AlphaInterrupts
 592 eventq_index=0
 593
 594 [system.cpu.isa]
 595 type=AlphaISA
 596 eventq_index=0
 597 system=system
 598
 599 [system.cpu.itb]
 600 type=AlphaTLB
 601 eventq_index=0
 602 size=48
 603
 604 [system.cpu.l2cache]
 605 type=Cache
 606 children=tags
 607 addr_ranges=0:18446744073709551615
 608 assoc=8
 609 clk_domain=system.cpu_clk_domain
 610 clusivity=mostly_incl
 611 demand_mshr_reserve=1
 612 eventq_index=0
 613 forward_snoops=true
 614 hit_latency=20
 615 is_read_only=false
 616 max_miss_count=0
 617 mshrs=20
 618 prefetch_on_access=false
 619 prefetcher=Null
 620 response_latency=20
 621 sequential_access=false
 622 size=2097152
 623 system=system
 624 tags=system.cpu.l2cache.tags
 625 tgts_per_mshr=12
 626 write_buffers=8
 627 writeback_clean=false
 628 cpu_side=system.cpu.toL2Bus.master[0]
 629 mem_side=system.membus.slave[1]
 630
 631 [system.cpu.l2cache.tags]
 632 type=LRU
 633 assoc=8
 634 block_size=64
 635 clk_domain=system.cpu_clk_domain
 636 eventq_index=0
 637 hit_latency=20
 638 sequential_access=false
 639 size=2097152
 640
 641 [system.cpu.toL2Bus]
 642 type=CoherentXBar
 643 children=snoop_filter
 644 clk_domain=system.cpu_clk_domain
 645 eventq_index=0
 646 forward_latency=0
 647 frontend_latency=1
 648 response_latency=1
 649 snoop_filter=system.cpu.toL2Bus.snoop_filter
 650 snoop_response_latency=1
 651 system=system
 652 use_default_range=false
 653 width=32
 654 master=system.cpu.l2cache.cpu_side
 655 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 656
 657 [system.cpu.toL2Bus.snoop_filter]
 658 type=SnoopFilter
 659 eventq_index=0
 660 lookup_latency=0
 661 max_capacity=8388608
 662 system=system
 663
 664 [system.cpu.tracer]
 665 type=ExeTracer
 666 eventq_index=0
 667
 668 [system.cpu.workload]
 669 type=LiveProcess
 670 cmd=hello
 671 cwd=
 672 drivers=
 673 egid=100
 674 env=
 675 errout=cerr
 676 euid=100
 677 eventq_index=0
 678 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 679 gid=100
 680 input=cin
 681 kvmInSE=false
 682 max_stack_size=67108864
 683 output=cout
 684 pid=100
 685 ppid=99
 686 simpoint=0
 687 system=system
 688 uid=100
 689 useArchPT=false
 690
 691 [system.cpu_clk_domain]
 692 type=SrcClockDomain
 693 clock=500
 694 domain_id=-1
 695 eventq_index=0
 696 init_perf_level=0
 697 voltage_domain=system.voltage_domain
 698
 699 [system.dvfs_handler]
 700 type=DVFSHandler
 701 domains=
 702 enable=false
 703 eventq_index=0
 704 sys_clk_domain=system.clk_domain
 705 transition_latency=100000000
 706
 707 [system.membus]
 708 type=CoherentXBar
 709 clk_domain=system.clk_domain
 710 eventq_index=0
 711 forward_latency=4
 712 frontend_latency=3
 713 response_latency=2
 714 snoop_filter=Null
 715 snoop_response_latency=4
 716 system=system
 717 use_default_range=false
 718 width=16
 719 master=system.physmem.port
 720 slave=system.system_port system.cpu.l2cache.mem_side
 721
 722 [system.physmem]
 723 type=DRAMCtrl
 724 IDD0=0.075000
 725 IDD02=0.000000
 726 IDD2N=0.050000
 727 IDD2N2=0.000000
 728 IDD2P0=0.000000
 729 IDD2P02=0.000000
 730 IDD2P1=0.000000
 731 IDD2P12=0.000000
 732 IDD3N=0.057000
 733 IDD3N2=0.000000
 734 IDD3P0=0.000000
 735 IDD3P02=0.000000
 736 IDD3P1=0.000000
 737 IDD3P12=0.000000
 738 IDD4R=0.187000
 739 IDD4R2=0.000000
 740 IDD4W=0.165000
 741 IDD4W2=0.000000
 742 IDD5=0.220000
 743 IDD52=0.000000
 744 IDD6=0.000000
 745 IDD62=0.000000
 746 VDD=1.500000
 747 VDD2=0.000000
 748 activation_limit=4
 749 addr_mapping=RoRaBaCoCh
 750 bank_groups_per_rank=0
 751 banks_per_rank=8
 752 burst_length=8
 753 channels=1
 754 clk_domain=system.clk_domain
 755 conf_table_reported=true
 756 device_bus_width=8
 757 device_rowbuffer_size=1024
 758 device_size=536870912
 759 devices_per_rank=8
 760 dll=true
 761 eventq_index=0
 762 in_addr_map=true
 763 max_accesses_per_row=16
 764 mem_sched_policy=frfcfs
 765 min_writes_per_switch=16
 766 null=false
 767 page_policy=open_adaptive
 768 range=0:134217727
 769 ranks_per_channel=2
 770 read_buffer_size=32
 771 static_backend_latency=10000
 772 static_frontend_latency=10000
 773 tBURST=5000
 774 tCCD_L=0
 775 tCK=1250
 776 tCL=13750
 777 tCS=2500
 778 tRAS=35000
 779 tRCD=13750
 780 tREFI=7800000
 781 tRFC=260000
 782 tRP=13750
 783 tRRD=6000
 784 tRRD_L=0
 785 tRTP=7500
 786 tRTW=2500
 787 tWR=15000
 788 tWTR=7500
 789 tXAW=30000
 790 tXP=0
 791 tXPDLL=0
 792 tXS=0
 793 tXSDLL=0
 794 write_buffer_size=64
 795 write_high_thresh_perc=85
 796 write_low_thresh_perc=50
 797 port=system.membus.master[0]
 798
 799 [system.voltage_domain]
 800 type=VoltageDomain
 801 eventq_index=0
 802 voltage=1.000000
 803