tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 load_offset=0
  22 mem_mode=timing
  23 mem_ranges=
  24 memories=system.physmem
  25 num_work_ids=16
  26 readfile=
  27 symbolfile=
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.slave[0]
  36
  37 [system.clk_domain]
  38 type=SrcClockDomain
  39 clock=1000
  40 eventq_index=0
  41 voltage_domain=system.voltage_domain
  42
  43 [system.cpu]
  44 type=MinorCPU
  45 children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
  46 branchPred=system.cpu.branchPred
  47 checker=Null
  48 clk_domain=system.cpu_clk_domain
  49 cpu_id=0
  50 decodeCycleInput=true
  51 decodeInputBufferSize=3
  52 decodeInputWidth=2
  53 decodeToExecuteForwardDelay=1
  54 do_checkpoint_insts=true
  55 do_quiesce=true
  56 do_statistics_insts=true
  57 dtb=system.cpu.dtb
  58 enableIdling=true
  59 eventq_index=0
  60 executeAllowEarlyMemoryIssue=true
  61 executeBranchDelay=1
  62 executeCommitLimit=2
  63 executeCycleInput=true
  64 executeFuncUnits=system.cpu.executeFuncUnits
  65 executeInputBufferSize=7
  66 executeInputWidth=2
  67 executeIssueLimit=2
  68 executeLSQMaxStoreBufferStoresPerCycle=2
  69 executeLSQRequestsQueueSize=1
  70 executeLSQStoreBufferSize=5
  71 executeLSQTransfersQueueSize=2
  72 executeMaxAccessesInMemory=2
  73 executeMemoryCommitLimit=1
  74 executeMemoryIssueLimit=1
  75 executeMemoryWidth=0
  76 executeSetTraceTimeOnCommit=true
  77 executeSetTraceTimeOnIssue=false
  78 fetch1FetchLimit=1
  79 fetch1LineSnapWidth=0
  80 fetch1LineWidth=0
  81 fetch1ToFetch2BackwardDelay=1
  82 fetch1ToFetch2ForwardDelay=1
  83 fetch2CycleInput=true
  84 fetch2InputBufferSize=2
  85 fetch2ToDecodeForwardDelay=1
  86 function_trace=false
  87 function_trace_start=0
  88 interrupts=system.cpu.interrupts
  89 isa=system.cpu.isa
  90 itb=system.cpu.itb
  91 max_insts_all_threads=0
  92 max_insts_any_thread=0
  93 max_loads_all_threads=0
  94 max_loads_any_thread=0
  95 numThreads=1
  96 profile=0
  97 progress_interval=0
  98 simpoint_start_insts=
  99 switched_out=false
 100 system=system
 101 tracer=system.cpu.tracer
 102 workload=system.cpu.workload
 103 dcache_port=system.cpu.dcache.cpu_side
 104 icache_port=system.cpu.icache.cpu_side
 105
 106 [system.cpu.branchPred]
 107 type=BranchPredictor
 108 BTBEntries=4096
 109 BTBTagSize=16
 110 RASSize=16
 111 choiceCtrBits=2
 112 choicePredictorSize=8192
 113 eventq_index=0
 114 globalCtrBits=2
 115 globalPredictorSize=8192
 116 instShiftAmt=2
 117 localCtrBits=2
 118 localHistoryTableSize=2048
 119 localPredictorSize=2048
 120 numThreads=1
 121 predType=tournament
 122
 123 [system.cpu.dcache]
 124 type=BaseCache
 125 children=tags
 126 addr_ranges=0:18446744073709551615
 127 assoc=2
 128 clk_domain=system.cpu_clk_domain
 129 eventq_index=0
 130 forward_snoops=true
 131 hit_latency=2
 132 is_top_level=true
 133 max_miss_count=0
 134 mshrs=4
 135 prefetch_on_access=false
 136 prefetcher=Null
 137 response_latency=2
 138 sequential_access=false
 139 size=262144
 140 system=system
 141 tags=system.cpu.dcache.tags
 142 tgts_per_mshr=20
 143 two_queue=false
 144 write_buffers=8
 145 cpu_side=system.cpu.dcache_port
 146 mem_side=system.cpu.toL2Bus.slave[1]
 147
 148 [system.cpu.dcache.tags]
 149 type=LRU
 150 assoc=2
 151 block_size=64
 152 clk_domain=system.cpu_clk_domain
 153 eventq_index=0
 154 hit_latency=2
 155 sequential_access=false
 156 size=262144
 157
 158 [system.cpu.dtb]
 159 type=AlphaTLB
 160 eventq_index=0
 161 size=64
 162
 163 [system.cpu.executeFuncUnits]
 164 type=MinorFUPool
 165 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 166 eventq_index=0
 167 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 168
 169 [system.cpu.executeFuncUnits.funcUnits0]
 170 type=MinorFU
 171 children=opClasses timings
 172 eventq_index=0
 173 issueLat=1
 174 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 175 opLat=3
 176 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 177
 178 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 179 type=MinorOpClassSet
 180 children=opClasses
 181 eventq_index=0
 182 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 183
 184 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 185 type=MinorOpClass
 186 eventq_index=0
 187 opClass=IntAlu
 188
 189 [system.cpu.executeFuncUnits.funcUnits0.timings]
 190 type=MinorFUTiming
 191 children=opClasses
 192 description=Int
 193 eventq_index=0
 194 extraAssumedLat=0
 195 extraCommitLat=0
 196 extraCommitLatExpr=Null
 197 mask=0
 198 match=0
 199 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 200 srcRegsRelativeLats=2
 201 suppress=false
 202
 203 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 204 type=MinorOpClassSet
 205 eventq_index=0
 206 opClasses=
 207
 208 [system.cpu.executeFuncUnits.funcUnits1]
 209 type=MinorFU
 210 children=opClasses timings
 211 eventq_index=0
 212 issueLat=1
 213 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 214 opLat=3
 215 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 216
 217 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 218 type=MinorOpClassSet
 219 children=opClasses
 220 eventq_index=0
 221 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 222
 223 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 224 type=MinorOpClass
 225 eventq_index=0
 226 opClass=IntAlu
 227
 228 [system.cpu.executeFuncUnits.funcUnits1.timings]
 229 type=MinorFUTiming
 230 children=opClasses
 231 description=Int
 232 eventq_index=0
 233 extraAssumedLat=0
 234 extraCommitLat=0
 235 extraCommitLatExpr=Null
 236 mask=0
 237 match=0
 238 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 239 srcRegsRelativeLats=2
 240 suppress=false
 241
 242 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 243 type=MinorOpClassSet
 244 eventq_index=0
 245 opClasses=
 246
 247 [system.cpu.executeFuncUnits.funcUnits2]
 248 type=MinorFU
 249 children=opClasses timings
 250 eventq_index=0
 251 issueLat=1
 252 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 253 opLat=3
 254 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 255
 256 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 257 type=MinorOpClassSet
 258 children=opClasses
 259 eventq_index=0
 260 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 261
 262 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 263 type=MinorOpClass
 264 eventq_index=0
 265 opClass=IntMult
 266
 267 [system.cpu.executeFuncUnits.funcUnits2.timings]
 268 type=MinorFUTiming
 269 children=opClasses
 270 description=Mul
 271 eventq_index=0
 272 extraAssumedLat=0
 273 extraCommitLat=0
 274 extraCommitLatExpr=Null
 275 mask=0
 276 match=0
 277 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 278 srcRegsRelativeLats=0
 279 suppress=false
 280
 281 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 282 type=MinorOpClassSet
 283 eventq_index=0
 284 opClasses=
 285
 286 [system.cpu.executeFuncUnits.funcUnits3]
 287 type=MinorFU
 288 children=opClasses
 289 eventq_index=0
 290 issueLat=9
 291 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 292 opLat=9
 293 timings=
 294
 295 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 296 type=MinorOpClassSet
 297 children=opClasses
 298 eventq_index=0
 299 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 300
 301 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 302 type=MinorOpClass
 303 eventq_index=0
 304 opClass=IntDiv
 305
 306 [system.cpu.executeFuncUnits.funcUnits4]
 307 type=MinorFU
 308 children=opClasses timings
 309 eventq_index=0
 310 issueLat=1
 311 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 312 opLat=6
 313 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 314
 315 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 316 type=MinorOpClassSet
 317 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 318 eventq_index=0
 319 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 320
 321 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 322 type=MinorOpClass
 323 eventq_index=0
 324 opClass=FloatAdd
 325
 326 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 327 type=MinorOpClass
 328 eventq_index=0
 329 opClass=FloatCmp
 330
 331 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 332 type=MinorOpClass
 333 eventq_index=0
 334 opClass=FloatCvt
 335
 336 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 337 type=MinorOpClass
 338 eventq_index=0
 339 opClass=FloatMult
 340
 341 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 342 type=MinorOpClass
 343 eventq_index=0
 344 opClass=FloatDiv
 345
 346 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 347 type=MinorOpClass
 348 eventq_index=0
 349 opClass=FloatSqrt
 350
 351 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 352 type=MinorOpClass
 353 eventq_index=0
 354 opClass=SimdAdd
 355
 356 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 357 type=MinorOpClass
 358 eventq_index=0
 359 opClass=SimdAddAcc
 360
 361 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 362 type=MinorOpClass
 363 eventq_index=0
 364 opClass=SimdAlu
 365
 366 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 367 type=MinorOpClass
 368 eventq_index=0
 369 opClass=SimdCmp
 370
 371 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 372 type=MinorOpClass
 373 eventq_index=0
 374 opClass=SimdCvt
 375
 376 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 377 type=MinorOpClass
 378 eventq_index=0
 379 opClass=SimdMisc
 380
 381 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 382 type=MinorOpClass
 383 eventq_index=0
 384 opClass=SimdMult
 385
 386 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 387 type=MinorOpClass
 388 eventq_index=0
 389 opClass=SimdMultAcc
 390
 391 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 392 type=MinorOpClass
 393 eventq_index=0
 394 opClass=SimdShift
 395
 396 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 397 type=MinorOpClass
 398 eventq_index=0
 399 opClass=SimdShiftAcc
 400
 401 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 402 type=MinorOpClass
 403 eventq_index=0
 404 opClass=SimdSqrt
 405
 406 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 407 type=MinorOpClass
 408 eventq_index=0
 409 opClass=SimdFloatAdd
 410
 411 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 412 type=MinorOpClass
 413 eventq_index=0
 414 opClass=SimdFloatAlu
 415
 416 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 417 type=MinorOpClass
 418 eventq_index=0
 419 opClass=SimdFloatCmp
 420
 421 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 422 type=MinorOpClass
 423 eventq_index=0
 424 opClass=SimdFloatCvt
 425
 426 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 427 type=MinorOpClass
 428 eventq_index=0
 429 opClass=SimdFloatDiv
 430
 431 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 432 type=MinorOpClass
 433 eventq_index=0
 434 opClass=SimdFloatMisc
 435
 436 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 437 type=MinorOpClass
 438 eventq_index=0
 439 opClass=SimdFloatMult
 440
 441 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 442 type=MinorOpClass
 443 eventq_index=0
 444 opClass=SimdFloatMultAcc
 445
 446 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 447 type=MinorOpClass
 448 eventq_index=0
 449 opClass=SimdFloatSqrt
 450
 451 [system.cpu.executeFuncUnits.funcUnits4.timings]
 452 type=MinorFUTiming
 453 children=opClasses
 454 description=FloatSimd
 455 eventq_index=0
 456 extraAssumedLat=0
 457 extraCommitLat=0
 458 extraCommitLatExpr=Null
 459 mask=0
 460 match=0
 461 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 462 srcRegsRelativeLats=2
 463 suppress=false
 464
 465 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 466 type=MinorOpClassSet
 467 eventq_index=0
 468 opClasses=
 469
 470 [system.cpu.executeFuncUnits.funcUnits5]
 471 type=MinorFU
 472 children=opClasses timings
 473 eventq_index=0
 474 issueLat=1
 475 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 476 opLat=1
 477 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 478
 479 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 480 type=MinorOpClassSet
 481 children=opClasses0 opClasses1
 482 eventq_index=0
 483 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 484
 485 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 486 type=MinorOpClass
 487 eventq_index=0
 488 opClass=MemRead
 489
 490 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 491 type=MinorOpClass
 492 eventq_index=0
 493 opClass=MemWrite
 494
 495 [system.cpu.executeFuncUnits.funcUnits5.timings]
 496 type=MinorFUTiming
 497 children=opClasses
 498 description=Mem
 499 eventq_index=0
 500 extraAssumedLat=2
 501 extraCommitLat=0
 502 extraCommitLatExpr=Null
 503 mask=0
 504 match=0
 505 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 506 srcRegsRelativeLats=1
 507 suppress=false
 508
 509 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 510 type=MinorOpClassSet
 511 eventq_index=0
 512 opClasses=
 513
 514 [system.cpu.executeFuncUnits.funcUnits6]
 515 type=MinorFU
 516 children=opClasses
 517 eventq_index=0
 518 issueLat=1
 519 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 520 opLat=1
 521 timings=
 522
 523 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 524 type=MinorOpClassSet
 525 children=opClasses0 opClasses1
 526 eventq_index=0
 527 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 528
 529 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 530 type=MinorOpClass
 531 eventq_index=0
 532 opClass=IprAccess
 533
 534 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 535 type=MinorOpClass
 536 eventq_index=0
 537 opClass=InstPrefetch
 538
 539 [system.cpu.icache]
 540 type=BaseCache
 541 children=tags
 542 addr_ranges=0:18446744073709551615
 543 assoc=2
 544 clk_domain=system.cpu_clk_domain
 545 eventq_index=0
 546 forward_snoops=true
 547 hit_latency=2
 548 is_top_level=true
 549 max_miss_count=0
 550 mshrs=4
 551 prefetch_on_access=false
 552 prefetcher=Null
 553 response_latency=2
 554 sequential_access=false
 555 size=131072
 556 system=system
 557 tags=system.cpu.icache.tags
 558 tgts_per_mshr=20
 559 two_queue=false
 560 write_buffers=8
 561 cpu_side=system.cpu.icache_port
 562 mem_side=system.cpu.toL2Bus.slave[0]
 563
 564 [system.cpu.icache.tags]
 565 type=LRU
 566 assoc=2
 567 block_size=64
 568 clk_domain=system.cpu_clk_domain
 569 eventq_index=0
 570 hit_latency=2
 571 sequential_access=false
 572 size=131072
 573
 574 [system.cpu.interrupts]
 575 type=AlphaInterrupts
 576 eventq_index=0
 577
 578 [system.cpu.isa]
 579 type=AlphaISA
 580 eventq_index=0
 581 system=system
 582
 583 [system.cpu.itb]
 584 type=AlphaTLB
 585 eventq_index=0
 586 size=48
 587
 588 [system.cpu.l2cache]
 589 type=BaseCache
 590 children=tags
 591 addr_ranges=0:18446744073709551615
 592 assoc=8
 593 clk_domain=system.cpu_clk_domain
 594 eventq_index=0
 595 forward_snoops=true
 596 hit_latency=20
 597 is_top_level=false
 598 max_miss_count=0
 599 mshrs=20
 600 prefetch_on_access=false
 601 prefetcher=Null
 602 response_latency=20
 603 sequential_access=false
 604 size=2097152
 605 system=system
 606 tags=system.cpu.l2cache.tags
 607 tgts_per_mshr=12
 608 two_queue=false
 609 write_buffers=8
 610 cpu_side=system.cpu.toL2Bus.master[0]
 611 mem_side=system.membus.slave[1]
 612
 613 [system.cpu.l2cache.tags]
 614 type=LRU
 615 assoc=8
 616 block_size=64
 617 clk_domain=system.cpu_clk_domain
 618 eventq_index=0
 619 hit_latency=20
 620 sequential_access=false
 621 size=2097152
 622
 623 [system.cpu.toL2Bus]
 624 type=CoherentBus
 625 clk_domain=system.cpu_clk_domain
 626 eventq_index=0
 627 header_cycles=1
 628 system=system
 629 use_default_range=false
 630 width=32
 631 master=system.cpu.l2cache.cpu_side
 632 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 633
 634 [system.cpu.tracer]
 635 type=ExeTracer
 636 eventq_index=0
 637
 638 [system.cpu.workload]
 639 type=LiveProcess
 640 cmd=hello
 641 cwd=
 642 egid=100
 643 env=
 644 errout=cerr
 645 euid=100
 646 eventq_index=0
 647 executable=/arm/projectscratch/pd/sysrandd/dist/test-progs/hello/bin/alpha/linux/hello
 648 gid=100
 649 input=cin
 650 max_stack_size=67108864
 651 output=cout
 652 pid=100
 653 ppid=99
 654 simpoint=0
 655 system=system
 656 uid=100
 657
 658 [system.cpu_clk_domain]
 659 type=SrcClockDomain
 660 clock=500
 661 eventq_index=0
 662 voltage_domain=system.voltage_domain
 663
 664 [system.membus]
 665 type=CoherentBus
 666 clk_domain=system.clk_domain
 667 eventq_index=0
 668 header_cycles=1
 669 system=system
 670 use_default_range=false
 671 width=8
 672 master=system.physmem.port
 673 slave=system.system_port system.cpu.l2cache.mem_side
 674
 675 [system.physmem]
 676 type=DRAMCtrl
 677 activation_limit=4
 678 addr_mapping=RoRaBaChCo
 679 banks_per_rank=8
 680 burst_length=8
 681 channels=1
 682 clk_domain=system.clk_domain
 683 conf_table_reported=true
 684 device_bus_width=8
 685 device_rowbuffer_size=1024
 686 devices_per_rank=8
 687 eventq_index=0
 688 in_addr_map=true
 689 max_accesses_per_row=16
 690 mem_sched_policy=frfcfs
 691 min_writes_per_switch=16
 692 null=false
 693 page_policy=open_adaptive
 694 range=0:134217727
 695 ranks_per_channel=2
 696 read_buffer_size=32
 697 static_backend_latency=10000
 698 static_frontend_latency=10000
 699 tBURST=5000
 700 tCL=13750
 701 tRAS=35000
 702 tRCD=13750
 703 tREFI=7800000
 704 tRFC=300000
 705 tRP=13750
 706 tRRD=6250
 707 tWTR=7500
 708 tXAW=40000
 709 write_buffer_size=64
 710 write_high_thresh_perc=85
 711 write_low_thresh_perc=50
 712 port=system.membus.master[0]
 713
 714 [system.voltage_domain]
 715 type=VoltageDomain
 716 eventq_index=0
 717 voltage=1.000000
 718