2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000041 # Number of seconds simulated
4 sim_ticks 41083000 # Number of ticks simulated
5 final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 202272 # Simulator instruction rate (inst/s)
8 host_op_rate 202193 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1294825774 # Simulator tick rate (ticks/s)
10 host_mem_usage 252636 # Number of bytes of host memory used
11 host_seconds 0.03 # Real time elapsed on the host
12 sim_insts 6413 # Number of instructions simulated
13 sim_ops 6413 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 532 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 565489375 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 263271913 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 828761288 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 565489375 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 565489375 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 565489375 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 263271913 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 828761288 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.readReqs 532 # Number of read requests accepted
34 system.physmem.writeReqs 0 # Number of write requests accepted
35 system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue
36 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37 system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM
38 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40 system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side
41 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45 system.physmem.perBankRdBursts::0 73 # Per bank write bursts
46 system.physmem.perBankRdBursts::1 39 # Per bank write bursts
47 system.physmem.perBankRdBursts::2 36 # Per bank write bursts
48 system.physmem.perBankRdBursts::3 54 # Per bank write bursts
49 system.physmem.perBankRdBursts::4 45 # Per bank write bursts
50 system.physmem.perBankRdBursts::5 21 # Per bank write bursts
51 system.physmem.perBankRdBursts::6 1 # Per bank write bursts
52 system.physmem.perBankRdBursts::7 5 # Per bank write bursts
53 system.physmem.perBankRdBursts::8 0 # Per bank write bursts
54 system.physmem.perBankRdBursts::9 1 # Per bank write bursts
55 system.physmem.perBankRdBursts::10 21 # Per bank write bursts
56 system.physmem.perBankRdBursts::11 29 # Per bank write bursts
57 system.physmem.perBankRdBursts::12 19 # Per bank write bursts
58 system.physmem.perBankRdBursts::13 127 # Per bank write bursts
59 system.physmem.perBankRdBursts::14 47 # Per bank write bursts
60 system.physmem.perBankRdBursts::15 14 # Per bank write bursts
61 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79 system.physmem.totGap 40972000 # Total gap between requests
80 system.physmem.readPktSize::0 0 # Read request sizes (log2)
81 system.physmem.readPktSize::1 0 # Read request sizes (log2)
82 system.physmem.readPktSize::2 0 # Read request sizes (log2)
83 system.physmem.readPktSize::3 0 # Read request sizes (log2)
84 system.physmem.readPktSize::4 0 # Read request sizes (log2)
85 system.physmem.readPktSize::5 0 # Read request sizes (log2)
86 system.physmem.readPktSize::6 532 # Read request sizes (log2)
87 system.physmem.writePktSize::0 0 # Write request sizes (log2)
88 system.physmem.writePktSize::1 0 # Write request sizes (log2)
89 system.physmem.writePktSize::2 0 # Write request sizes (log2)
90 system.physmem.writePktSize::3 0 # Write request sizes (log2)
91 system.physmem.writePktSize::4 0 # Write request sizes (log2)
92 system.physmem.writePktSize::5 0 # Write request sizes (log2)
93 system.physmem.writePktSize::6 0 # Write request sizes (log2)
94 system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190 system.physmem.bytesPerActivate::samples 91 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::mean 363.604396 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::gmean 235.588514 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::stdev 321.826485 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::0-127 22 24.18% 24.18% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::128-255 22 24.18% 48.35% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation
204 system.physmem.totQLat 6584250 # Total ticks spent queuing
205 system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM
206 system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
207 system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst
208 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209 system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst
210 system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s
211 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212 system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s
213 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215 system.physmem.busUtil 6.47 # Data bus utilization in percentage
216 system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads
217 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218 system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
219 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220 system.physmem.readRowHits 436 # Number of row buffer hits during reads
221 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222 system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
223 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224 system.physmem.avgGap 77015.04 # Average gap between requests
225 system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
226 system.physmem_0.actEnergy 264180 # Energy for activate commands per rank (pJ)
227 system.physmem_0.preEnergy 136620 # Energy for precharge commands per rank (pJ)
228 system.physmem_0.readEnergy 1956360 # Energy for read commands per rank (pJ)
229 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230 system.physmem_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
231 system.physmem_0.actBackEnergy 3932430 # Energy for active background per rank (pJ)
232 system.physmem_0.preBackEnergy 68640 # Energy for precharge background per rank (pJ)
233 system.physmem_0.actPowerDownEnergy 13617300 # Energy for active power-down per rank (pJ)
234 system.physmem_0.prePowerDownEnergy 928800 # Energy for precharge power-down per rank (pJ)
235 system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236 system.physmem_0.totalEnergy 23977530 # Total energy per rank (pJ)
237 system.physmem_0.averagePower 583.625643 # Core power per rank (mW)
238 system.physmem_0.totalIdleTime 32009500 # Total Idle time Per DRAM Rank
239 system.physmem_0.memoryStateTime::IDLE 39500 # Time in different power states
240 system.physmem_0.memoryStateTime::REF 1300000 # Time in different power states
241 system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242 system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states
243 system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states
244 system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states
245 system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ)
246 system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ)
247 system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ)
248 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249 system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
250 system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ)
251 system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ)
252 system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ)
253 system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ)
254 system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255 system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ)
256 system.physmem_1.averagePower 589.365503 # Core power per rank (mW)
257 system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank
258 system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states
259 system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states
260 system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261 system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states
262 system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states
263 system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states
264 system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
265 system.cpu.branchPred.lookups 2002 # Number of BP lookups
266 system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted
267 system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect
268 system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups
269 system.cpu.branchPred.BTBHits 377 # Number of BTB hits
270 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271 system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage
272 system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
273 system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
274 system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups.
275 system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
276 system.cpu.branchPred.indirectMisses 319 # Number of indirect misses.
277 system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches.
278 system.cpu_clk_domain.clock 500 # Clock period in ticks
279 system.cpu.dtb.fetch_hits 0 # ITB hits
280 system.cpu.dtb.fetch_misses 0 # ITB misses
281 system.cpu.dtb.fetch_acv 0 # ITB acv
282 system.cpu.dtb.fetch_accesses 0 # ITB accesses
283 system.cpu.dtb.read_hits 1365 # DTB read hits
284 system.cpu.dtb.read_misses 11 # DTB read misses
285 system.cpu.dtb.read_acv 0 # DTB read access violations
286 system.cpu.dtb.read_accesses 1376 # DTB read accesses
287 system.cpu.dtb.write_hits 884 # DTB write hits
288 system.cpu.dtb.write_misses 3 # DTB write misses
289 system.cpu.dtb.write_acv 0 # DTB write access violations
290 system.cpu.dtb.write_accesses 887 # DTB write accesses
291 system.cpu.dtb.data_hits 2249 # DTB hits
292 system.cpu.dtb.data_misses 14 # DTB misses
293 system.cpu.dtb.data_acv 0 # DTB access violations
294 system.cpu.dtb.data_accesses 2263 # DTB accesses
295 system.cpu.itb.fetch_hits 2685 # ITB hits
296 system.cpu.itb.fetch_misses 17 # ITB misses
297 system.cpu.itb.fetch_acv 0 # ITB acv
298 system.cpu.itb.fetch_accesses 2702 # ITB accesses
299 system.cpu.itb.read_hits 0 # DTB read hits
300 system.cpu.itb.read_misses 0 # DTB read misses
301 system.cpu.itb.read_acv 0 # DTB read access violations
302 system.cpu.itb.read_accesses 0 # DTB read accesses
303 system.cpu.itb.write_hits 0 # DTB write hits
304 system.cpu.itb.write_misses 0 # DTB write misses
305 system.cpu.itb.write_acv 0 # DTB write access violations
306 system.cpu.itb.write_accesses 0 # DTB write accesses
307 system.cpu.itb.data_hits 0 # DTB hits
308 system.cpu.itb.data_misses 0 # DTB misses
309 system.cpu.itb.data_acv 0 # DTB access violations
310 system.cpu.itb.data_accesses 0 # DTB accesses
311 system.cpu.workload.numSyscalls 17 # Number of system calls
312 system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states
313 system.cpu.numCycles 82166 # number of cpu cycles simulated
314 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
315 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
316 system.cpu.committedInsts 6413 # Number of instructions committed
317 system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
318 system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit
319 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
320 system.cpu.cpi 12.812412 # CPI: cycles per instruction
321 system.cpu.ipc 0.078049 # IPC: instructions per cycle
322 system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
323 system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
324 system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
325 system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction
326 system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction
327 system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction
328 system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction
329 system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction
330 system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction
331 system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction
332 system.cpu.op_class_0::FloatMisc 0 0.00% 67.88% # Class of committed instruction
333 system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction
334 system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction
335 system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction
336 system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction
337 system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction
338 system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction
339 system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction
340 system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction
341 system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction
342 system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction
343 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction
344 system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction
345 system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction
346 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction
347 system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction
348 system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction
349 system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction
350 system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction
351 system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction
352 system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction
353 system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
354 system.cpu.op_class_0::MemRead 1191 18.57% 86.45% # Class of committed instruction
355 system.cpu.op_class_0::MemWrite 861 13.43% 99.88% # Class of committed instruction
356 system.cpu.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
357 system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
358 system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
359 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
360 system.cpu.op_class_0::total 6413 # Class of committed instruction
361 system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked
362 system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped
363 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
364 system.cpu.dcache.tags.replacements 0 # number of replacements
365 system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use
366 system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks.
367 system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
368 system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks.
369 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
370 system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor
371 system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy
372 system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy
373 system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
374 system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
375 system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
376 system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
377 system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses
378 system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses
379 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
380 system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits
381 system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits
382 system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
383 system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
384 system.cpu.dcache.demand_hits::cpu.data 1990 # number of demand (read+write) hits
385 system.cpu.dcache.demand_hits::total 1990 # number of demand (read+write) hits
386 system.cpu.dcache.overall_hits::cpu.data 1990 # number of overall hits
387 system.cpu.dcache.overall_hits::total 1990 # number of overall hits
388 system.cpu.dcache.ReadReq_misses::cpu.data 96 # number of ReadReq misses
389 system.cpu.dcache.ReadReq_misses::total 96 # number of ReadReq misses
390 system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
391 system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
392 system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses
393 system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses
394 system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses
395 system.cpu.dcache.overall_misses::total 221 # number of overall misses
396 system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles
397 system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles
398 system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles
399 system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles
400 system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles
401 system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles
402 system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles
403 system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles
404 system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses)
405 system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses)
406 system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
407 system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
408 system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses
409 system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses
410 system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses
411 system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses
412 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses
413 system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses
414 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
415 system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
416 system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses
417 system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses
418 system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses
419 system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses
420 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency
421 system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency
422 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency
423 system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency
424 system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
425 system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency
426 system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
427 system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency
428 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
429 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
430 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
431 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
432 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
433 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
434 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
435 system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
436 system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits
437 system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
438 system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits
439 system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits
440 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses
441 system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
442 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
443 system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
444 system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
445 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
446 system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
447 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
448 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles
449 system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles
450 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles
451 system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles
452 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles
453 system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles
454 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles
455 system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles
456 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses
457 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses
458 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
459 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
460 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses
461 system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses
462 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses
463 system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses
464 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency
465 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency
466 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency
467 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency
468 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
469 system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
470 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
471 system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
472 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
473 system.cpu.icache.tags.replacements 0 # number of replacements
474 system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use
475 system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks.
476 system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.
477 system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks.
478 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
479 system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor
480 system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy
481 system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy
482 system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
483 system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
484 system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id
485 system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
486 system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses
487 system.cpu.icache.tags.data_accesses 5734 # Number of data accesses
488 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
489 system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits
490 system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits
491 system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits
492 system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits
493 system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits
494 system.cpu.icache.overall_hits::total 2321 # number of overall hits
495 system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
496 system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
497 system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
498 system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
499 system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
500 system.cpu.icache.overall_misses::total 364 # number of overall misses
501 system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles
502 system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles
503 system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles
504 system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles
505 system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles
506 system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles
507 system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses)
508 system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses)
509 system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses
510 system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses
511 system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses
512 system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses
513 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses
514 system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses
515 system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses
516 system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses
517 system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses
518 system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses
519 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency
520 system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency
521 system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
522 system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency
523 system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
524 system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency
525 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
526 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
527 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
528 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
529 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
530 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
531 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses
532 system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses
533 system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses
534 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses
535 system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
536 system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses
537 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles
538 system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles
539 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles
540 system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles
541 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles
542 system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles
543 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses
544 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses
545 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses
546 system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses
547 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses
548 system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses
549 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency
550 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency
551 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
552 system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
553 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
554 system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
555 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
556 system.cpu.l2cache.tags.replacements 0 # number of replacements
557 system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use
558 system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
559 system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
560 system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
561 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
562 system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor
563 system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor
564 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy
565 system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy
566 system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy
567 system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
568 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
569 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id
570 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id
571 system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
572 system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
573 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
574 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
575 system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
576 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
577 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
578 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
579 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
580 system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
581 system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
582 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
583 system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
584 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses
585 system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses
586 system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
587 system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses
588 system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses
589 system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
590 system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
591 system.cpu.l2cache.overall_misses::total 532 # number of overall misses
592 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles
593 system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles
594 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles
595 system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles
596 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles
597 system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles
598 system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles
599 system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles
600 system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles
601 system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles
602 system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles
603 system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles
604 system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
605 system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
606 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
607 system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses)
608 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses)
609 system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses)
610 system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses
611 system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses
612 system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses
613 system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses
614 system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses
615 system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses
616 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
617 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
618 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses
619 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses
620 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
621 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
622 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses
623 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
624 system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses
625 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses
626 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
627 system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses
628 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency
629 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency
630 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency
631 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency
632 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency
633 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency
634 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
635 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
636 system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency
637 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
638 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
639 system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency
640 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
641 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
643 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
644 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
645 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
646 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
647 system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
648 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
649 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
650 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
651 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
652 system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
653 system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
654 system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses
655 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
656 system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
657 system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses
658 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles
659 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles
660 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles
661 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles
662 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles
663 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles
664 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles
665 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles
666 system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles
667 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles
668 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles
669 system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles
670 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
671 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
672 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
673 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses
674 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
675 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
676 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses
677 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
678 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses
679 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
680 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
681 system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses
682 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency
683 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency
684 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency
685 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency
686 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency
687 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency
688 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
689 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
690 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
691 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
692 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
693 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
694 system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
695 system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
696 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
697 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
698 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
699 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
700 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
701 system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
702 system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
703 system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
704 system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution
705 system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution
706 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes)
707 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
708 system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
709 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes)
710 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
711 system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
712 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
713 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
714 system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram
715 system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram
716 system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram
717 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
718 system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram
719 system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram
720 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
721 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
722 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
723 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
724 system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram
725 system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks)
726 system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
727 system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks)
728 system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
729 system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
730 system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
731 system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter.
732 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
733 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
734 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
735 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
736 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
737 system.membus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
738 system.membus.trans_dist::ReadResp 459 # Transaction distribution
739 system.membus.trans_dist::ReadExReq 73 # Transaction distribution
740 system.membus.trans_dist::ReadExResp 73 # Transaction distribution
741 system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution
742 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes)
743 system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes)
744 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes)
745 system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes)
746 system.membus.snoops 0 # Total snoops (count)
747 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
748 system.membus.snoop_fanout::samples 532 # Request fanout histogram
749 system.membus.snoop_fanout::mean 0 # Request fanout histogram
750 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
751 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
752 system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram
753 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
754 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
755 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
756 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
757 system.membus.snoop_fanout::total 532 # Request fanout histogram
758 system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks)
759 system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
760 system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks)
761 system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
763 ---------- End Simulation Statistics ----------
projects / gem5.git / blob