tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu]
  49 type=DerivO3CPU
  50 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  51 LFSTSize=1024
  52 LQEntries=32
  53 LSQCheckLoads=true
  54 LSQDepCheckShift=4
  55 SQEntries=32
  56 SSITSize=1024
  57 activity=0
  58 backComSize=5
  59 branchPred=system.cpu.branchPred
  60 cachePorts=200
  61 checker=Null
  62 clk_domain=system.cpu_clk_domain
  63 commitToDecodeDelay=1
  64 commitToFetchDelay=1
  65 commitToIEWDelay=1
  66 commitToRenameDelay=1
  67 commitWidth=8
  68 cpu_id=0
  69 decodeToFetchDelay=1
  70 decodeToRenameDelay=1
  71 decodeWidth=8
  72 dispatchWidth=8
  73 do_checkpoint_insts=true
  74 do_quiesce=true
  75 do_statistics_insts=true
  76 dtb=system.cpu.dtb
  77 eventq_index=0
  78 fetchBufferSize=64
  79 fetchQueueSize=32
  80 fetchToDecodeDelay=1
  81 fetchTrapLatency=1
  82 fetchWidth=8
  83 forwardComSize=5
  84 fuPool=system.cpu.fuPool
  85 function_trace=false
  86 function_trace_start=0
  87 iewToCommitDelay=1
  88 iewToDecodeDelay=1
  89 iewToFetchDelay=1
  90 iewToRenameDelay=1
  91 interrupts=system.cpu.interrupts
  92 isa=system.cpu.isa
  93 issueToExecuteDelay=1
  94 issueWidth=8
  95 itb=system.cpu.itb
  96 max_insts_all_threads=0
  97 max_insts_any_thread=0
  98 max_loads_all_threads=0
  99 max_loads_any_thread=0
 100 needsTSO=false
 101 numIQEntries=64
 102 numPhysCCRegs=0
 103 numPhysFloatRegs=256
 104 numPhysIntRegs=256
 105 numROBEntries=192
 106 numRobs=1
 107 numThreads=1
 108 profile=0
 109 progress_interval=0
 110 renameToDecodeDelay=1
 111 renameToFetchDelay=1
 112 renameToIEWDelay=2
 113 renameToROBDelay=1
 114 renameWidth=8
 115 simpoint_start_insts=
 116 smtCommitPolicy=RoundRobin
 117 smtFetchPolicy=SingleThread
 118 smtIQPolicy=Partitioned
 119 smtIQThreshold=100
 120 smtLSQPolicy=Partitioned
 121 smtLSQThreshold=100
 122 smtNumFetchingThreads=1
 123 smtROBPolicy=Partitioned
 124 smtROBThreshold=100
 125 socket_id=0
 126 squashWidth=8
 127 store_set_clear_period=250000
 128 switched_out=false
 129 system=system
 130 tracer=system.cpu.tracer
 131 trapLatency=13
 132 wbWidth=8
 133 workload=system.cpu.workload
 134 dcache_port=system.cpu.dcache.cpu_side
 135 icache_port=system.cpu.icache.cpu_side
 136
 137 [system.cpu.branchPred]
 138 type=TournamentBP
 139 BTBEntries=4096
 140 BTBTagSize=16
 141 RASSize=16
 142 choiceCtrBits=2
 143 choicePredictorSize=8192
 144 eventq_index=0
 145 globalCtrBits=2
 146 globalPredictorSize=8192
 147 instShiftAmt=2
 148 localCtrBits=2
 149 localHistoryTableSize=2048
 150 localPredictorSize=2048
 151 numThreads=1
 152
 153 [system.cpu.dcache]
 154 type=Cache
 155 children=tags
 156 addr_ranges=0:18446744073709551615
 157 assoc=2
 158 clk_domain=system.cpu_clk_domain
 159 clusivity=mostly_incl
 160 demand_mshr_reserve=1
 161 eventq_index=0
 162 forward_snoops=true
 163 hit_latency=2
 164 is_read_only=false
 165 max_miss_count=0
 166 mshrs=4
 167 prefetch_on_access=false
 168 prefetcher=Null
 169 response_latency=2
 170 sequential_access=false
 171 size=262144
 172 system=system
 173 tags=system.cpu.dcache.tags
 174 tgts_per_mshr=20
 175 write_buffers=8
 176 writeback_clean=false
 177 cpu_side=system.cpu.dcache_port
 178 mem_side=system.cpu.toL2Bus.slave[1]
 179
 180 [system.cpu.dcache.tags]
 181 type=LRU
 182 assoc=2
 183 block_size=64
 184 clk_domain=system.cpu_clk_domain
 185 eventq_index=0
 186 hit_latency=2
 187 sequential_access=false
 188 size=262144
 189
 190 [system.cpu.dtb]
 191 type=AlphaTLB
 192 eventq_index=0
 193 size=64
 194
 195 [system.cpu.fuPool]
 196 type=FUPool
 197 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 198 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 199 eventq_index=0
 200
 201 [system.cpu.fuPool.FUList0]
 202 type=FUDesc
 203 children=opList
 204 count=6
 205 eventq_index=0
 206 opList=system.cpu.fuPool.FUList0.opList
 207
 208 [system.cpu.fuPool.FUList0.opList]
 209 type=OpDesc
 210 eventq_index=0
 211 opClass=IntAlu
 212 opLat=1
 213 pipelined=true
 214
 215 [system.cpu.fuPool.FUList1]
 216 type=FUDesc
 217 children=opList0 opList1
 218 count=2
 219 eventq_index=0
 220 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 221
 222 [system.cpu.fuPool.FUList1.opList0]
 223 type=OpDesc
 224 eventq_index=0
 225 opClass=IntMult
 226 opLat=3
 227 pipelined=true
 228
 229 [system.cpu.fuPool.FUList1.opList1]
 230 type=OpDesc
 231 eventq_index=0
 232 opClass=IntDiv
 233 opLat=20
 234 pipelined=false
 235
 236 [system.cpu.fuPool.FUList2]
 237 type=FUDesc
 238 children=opList0 opList1 opList2
 239 count=4
 240 eventq_index=0
 241 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 242
 243 [system.cpu.fuPool.FUList2.opList0]
 244 type=OpDesc
 245 eventq_index=0
 246 opClass=FloatAdd
 247 opLat=2
 248 pipelined=true
 249
 250 [system.cpu.fuPool.FUList2.opList1]
 251 type=OpDesc
 252 eventq_index=0
 253 opClass=FloatCmp
 254 opLat=2
 255 pipelined=true
 256
 257 [system.cpu.fuPool.FUList2.opList2]
 258 type=OpDesc
 259 eventq_index=0
 260 opClass=FloatCvt
 261 opLat=2
 262 pipelined=true
 263
 264 [system.cpu.fuPool.FUList3]
 265 type=FUDesc
 266 children=opList0 opList1 opList2
 267 count=2
 268 eventq_index=0
 269 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 270
 271 [system.cpu.fuPool.FUList3.opList0]
 272 type=OpDesc
 273 eventq_index=0
 274 opClass=FloatMult
 275 opLat=4
 276 pipelined=true
 277
 278 [system.cpu.fuPool.FUList3.opList1]
 279 type=OpDesc
 280 eventq_index=0
 281 opClass=FloatDiv
 282 opLat=12
 283 pipelined=false
 284
 285 [system.cpu.fuPool.FUList3.opList2]
 286 type=OpDesc
 287 eventq_index=0
 288 opClass=FloatSqrt
 289 opLat=24
 290 pipelined=false
 291
 292 [system.cpu.fuPool.FUList4]
 293 type=FUDesc
 294 children=opList
 295 count=0
 296 eventq_index=0
 297 opList=system.cpu.fuPool.FUList4.opList
 298
 299 [system.cpu.fuPool.FUList4.opList]
 300 type=OpDesc
 301 eventq_index=0
 302 opClass=MemRead
 303 opLat=1
 304 pipelined=true
 305
 306 [system.cpu.fuPool.FUList5]
 307 type=FUDesc
 308 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 309 count=4
 310 eventq_index=0
 311 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 312
 313 [system.cpu.fuPool.FUList5.opList00]
 314 type=OpDesc
 315 eventq_index=0
 316 opClass=SimdAdd
 317 opLat=1
 318 pipelined=true
 319
 320 [system.cpu.fuPool.FUList5.opList01]
 321 type=OpDesc
 322 eventq_index=0
 323 opClass=SimdAddAcc
 324 opLat=1
 325 pipelined=true
 326
 327 [system.cpu.fuPool.FUList5.opList02]
 328 type=OpDesc
 329 eventq_index=0
 330 opClass=SimdAlu
 331 opLat=1
 332 pipelined=true
 333
 334 [system.cpu.fuPool.FUList5.opList03]
 335 type=OpDesc
 336 eventq_index=0
 337 opClass=SimdCmp
 338 opLat=1
 339 pipelined=true
 340
 341 [system.cpu.fuPool.FUList5.opList04]
 342 type=OpDesc
 343 eventq_index=0
 344 opClass=SimdCvt
 345 opLat=1
 346 pipelined=true
 347
 348 [system.cpu.fuPool.FUList5.opList05]
 349 type=OpDesc
 350 eventq_index=0
 351 opClass=SimdMisc
 352 opLat=1
 353 pipelined=true
 354
 355 [system.cpu.fuPool.FUList5.opList06]
 356 type=OpDesc
 357 eventq_index=0
 358 opClass=SimdMult
 359 opLat=1
 360 pipelined=true
 361
 362 [system.cpu.fuPool.FUList5.opList07]
 363 type=OpDesc
 364 eventq_index=0
 365 opClass=SimdMultAcc
 366 opLat=1
 367 pipelined=true
 368
 369 [system.cpu.fuPool.FUList5.opList08]
 370 type=OpDesc
 371 eventq_index=0
 372 opClass=SimdShift
 373 opLat=1
 374 pipelined=true
 375
 376 [system.cpu.fuPool.FUList5.opList09]
 377 type=OpDesc
 378 eventq_index=0
 379 opClass=SimdShiftAcc
 380 opLat=1
 381 pipelined=true
 382
 383 [system.cpu.fuPool.FUList5.opList10]
 384 type=OpDesc
 385 eventq_index=0
 386 opClass=SimdSqrt
 387 opLat=1
 388 pipelined=true
 389
 390 [system.cpu.fuPool.FUList5.opList11]
 391 type=OpDesc
 392 eventq_index=0
 393 opClass=SimdFloatAdd
 394 opLat=1
 395 pipelined=true
 396
 397 [system.cpu.fuPool.FUList5.opList12]
 398 type=OpDesc
 399 eventq_index=0
 400 opClass=SimdFloatAlu
 401 opLat=1
 402 pipelined=true
 403
 404 [system.cpu.fuPool.FUList5.opList13]
 405 type=OpDesc
 406 eventq_index=0
 407 opClass=SimdFloatCmp
 408 opLat=1
 409 pipelined=true
 410
 411 [system.cpu.fuPool.FUList5.opList14]
 412 type=OpDesc
 413 eventq_index=0
 414 opClass=SimdFloatCvt
 415 opLat=1
 416 pipelined=true
 417
 418 [system.cpu.fuPool.FUList5.opList15]
 419 type=OpDesc
 420 eventq_index=0
 421 opClass=SimdFloatDiv
 422 opLat=1
 423 pipelined=true
 424
 425 [system.cpu.fuPool.FUList5.opList16]
 426 type=OpDesc
 427 eventq_index=0
 428 opClass=SimdFloatMisc
 429 opLat=1
 430 pipelined=true
 431
 432 [system.cpu.fuPool.FUList5.opList17]
 433 type=OpDesc
 434 eventq_index=0
 435 opClass=SimdFloatMult
 436 opLat=1
 437 pipelined=true
 438
 439 [system.cpu.fuPool.FUList5.opList18]
 440 type=OpDesc
 441 eventq_index=0
 442 opClass=SimdFloatMultAcc
 443 opLat=1
 444 pipelined=true
 445
 446 [system.cpu.fuPool.FUList5.opList19]
 447 type=OpDesc
 448 eventq_index=0
 449 opClass=SimdFloatSqrt
 450 opLat=1
 451 pipelined=true
 452
 453 [system.cpu.fuPool.FUList6]
 454 type=FUDesc
 455 children=opList
 456 count=0
 457 eventq_index=0
 458 opList=system.cpu.fuPool.FUList6.opList
 459
 460 [system.cpu.fuPool.FUList6.opList]
 461 type=OpDesc
 462 eventq_index=0
 463 opClass=MemWrite
 464 opLat=1
 465 pipelined=true
 466
 467 [system.cpu.fuPool.FUList7]
 468 type=FUDesc
 469 children=opList0 opList1
 470 count=4
 471 eventq_index=0
 472 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 473
 474 [system.cpu.fuPool.FUList7.opList0]
 475 type=OpDesc
 476 eventq_index=0
 477 opClass=MemRead
 478 opLat=1
 479 pipelined=true
 480
 481 [system.cpu.fuPool.FUList7.opList1]
 482 type=OpDesc
 483 eventq_index=0
 484 opClass=MemWrite
 485 opLat=1
 486 pipelined=true
 487
 488 [system.cpu.fuPool.FUList8]
 489 type=FUDesc
 490 children=opList
 491 count=1
 492 eventq_index=0
 493 opList=system.cpu.fuPool.FUList8.opList
 494
 495 [system.cpu.fuPool.FUList8.opList]
 496 type=OpDesc
 497 eventq_index=0
 498 opClass=IprAccess
 499 opLat=3
 500 pipelined=false
 501
 502 [system.cpu.icache]
 503 type=Cache
 504 children=tags
 505 addr_ranges=0:18446744073709551615
 506 assoc=2
 507 clk_domain=system.cpu_clk_domain
 508 clusivity=mostly_incl
 509 demand_mshr_reserve=1
 510 eventq_index=0
 511 forward_snoops=true
 512 hit_latency=2
 513 is_read_only=true
 514 max_miss_count=0
 515 mshrs=4
 516 prefetch_on_access=false
 517 prefetcher=Null
 518 response_latency=2
 519 sequential_access=false
 520 size=131072
 521 system=system
 522 tags=system.cpu.icache.tags
 523 tgts_per_mshr=20
 524 write_buffers=8
 525 writeback_clean=true
 526 cpu_side=system.cpu.icache_port
 527 mem_side=system.cpu.toL2Bus.slave[0]
 528
 529 [system.cpu.icache.tags]
 530 type=LRU
 531 assoc=2
 532 block_size=64
 533 clk_domain=system.cpu_clk_domain
 534 eventq_index=0
 535 hit_latency=2
 536 sequential_access=false
 537 size=131072
 538
 539 [system.cpu.interrupts]
 540 type=AlphaInterrupts
 541 eventq_index=0
 542
 543 [system.cpu.isa]
 544 type=AlphaISA
 545 eventq_index=0
 546 system=system
 547
 548 [system.cpu.itb]
 549 type=AlphaTLB
 550 eventq_index=0
 551 size=48
 552
 553 [system.cpu.l2cache]
 554 type=Cache
 555 children=tags
 556 addr_ranges=0:18446744073709551615
 557 assoc=8
 558 clk_domain=system.cpu_clk_domain
 559 clusivity=mostly_incl
 560 demand_mshr_reserve=1
 561 eventq_index=0
 562 forward_snoops=true
 563 hit_latency=20
 564 is_read_only=false
 565 max_miss_count=0
 566 mshrs=20
 567 prefetch_on_access=false
 568 prefetcher=Null
 569 response_latency=20
 570 sequential_access=false
 571 size=2097152
 572 system=system
 573 tags=system.cpu.l2cache.tags
 574 tgts_per_mshr=12
 575 write_buffers=8
 576 writeback_clean=false
 577 cpu_side=system.cpu.toL2Bus.master[0]
 578 mem_side=system.membus.slave[1]
 579
 580 [system.cpu.l2cache.tags]
 581 type=LRU
 582 assoc=8
 583 block_size=64
 584 clk_domain=system.cpu_clk_domain
 585 eventq_index=0
 586 hit_latency=20
 587 sequential_access=false
 588 size=2097152
 589
 590 [system.cpu.toL2Bus]
 591 type=CoherentXBar
 592 children=snoop_filter
 593 clk_domain=system.cpu_clk_domain
 594 eventq_index=0
 595 forward_latency=0
 596 frontend_latency=1
 597 response_latency=1
 598 snoop_filter=system.cpu.toL2Bus.snoop_filter
 599 snoop_response_latency=1
 600 system=system
 601 use_default_range=false
 602 width=32
 603 master=system.cpu.l2cache.cpu_side
 604 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 605
 606 [system.cpu.toL2Bus.snoop_filter]
 607 type=SnoopFilter
 608 eventq_index=0
 609 lookup_latency=0
 610 max_capacity=8388608
 611 system=system
 612
 613 [system.cpu.tracer]
 614 type=ExeTracer
 615 eventq_index=0
 616
 617 [system.cpu.workload]
 618 type=LiveProcess
 619 cmd=hello
 620 cwd=
 621 drivers=
 622 egid=100
 623 env=
 624 errout=cerr
 625 euid=100
 626 eventq_index=0
 627 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 628 gid=100
 629 input=cin
 630 kvmInSE=false
 631 max_stack_size=67108864
 632 output=cout
 633 pid=100
 634 ppid=99
 635 simpoint=0
 636 system=system
 637 uid=100
 638 useArchPT=false
 639
 640 [system.cpu_clk_domain]
 641 type=SrcClockDomain
 642 clock=500
 643 domain_id=-1
 644 eventq_index=0
 645 init_perf_level=0
 646 voltage_domain=system.voltage_domain
 647
 648 [system.dvfs_handler]
 649 type=DVFSHandler
 650 domains=
 651 enable=false
 652 eventq_index=0
 653 sys_clk_domain=system.clk_domain
 654 transition_latency=100000000
 655
 656 [system.membus]
 657 type=CoherentXBar
 658 clk_domain=system.clk_domain
 659 eventq_index=0
 660 forward_latency=4
 661 frontend_latency=3
 662 response_latency=2
 663 snoop_filter=Null
 664 snoop_response_latency=4
 665 system=system
 666 use_default_range=false
 667 width=16
 668 master=system.physmem.port
 669 slave=system.system_port system.cpu.l2cache.mem_side
 670
 671 [system.physmem]
 672 type=DRAMCtrl
 673 IDD0=0.075000
 674 IDD02=0.000000
 675 IDD2N=0.050000
 676 IDD2N2=0.000000
 677 IDD2P0=0.000000
 678 IDD2P02=0.000000
 679 IDD2P1=0.000000
 680 IDD2P12=0.000000
 681 IDD3N=0.057000
 682 IDD3N2=0.000000
 683 IDD3P0=0.000000
 684 IDD3P02=0.000000
 685 IDD3P1=0.000000
 686 IDD3P12=0.000000
 687 IDD4R=0.187000
 688 IDD4R2=0.000000
 689 IDD4W=0.165000
 690 IDD4W2=0.000000
 691 IDD5=0.220000
 692 IDD52=0.000000
 693 IDD6=0.000000
 694 IDD62=0.000000
 695 VDD=1.500000
 696 VDD2=0.000000
 697 activation_limit=4
 698 addr_mapping=RoRaBaCoCh
 699 bank_groups_per_rank=0
 700 banks_per_rank=8
 701 burst_length=8
 702 channels=1
 703 clk_domain=system.clk_domain
 704 conf_table_reported=true
 705 device_bus_width=8
 706 device_rowbuffer_size=1024
 707 device_size=536870912
 708 devices_per_rank=8
 709 dll=true
 710 eventq_index=0
 711 in_addr_map=true
 712 max_accesses_per_row=16
 713 mem_sched_policy=frfcfs
 714 min_writes_per_switch=16
 715 null=false
 716 page_policy=open_adaptive
 717 range=0:134217727
 718 ranks_per_channel=2
 719 read_buffer_size=32
 720 static_backend_latency=10000
 721 static_frontend_latency=10000
 722 tBURST=5000
 723 tCCD_L=0
 724 tCK=1250
 725 tCL=13750
 726 tCS=2500
 727 tRAS=35000
 728 tRCD=13750
 729 tREFI=7800000
 730 tRFC=260000
 731 tRP=13750
 732 tRRD=6000
 733 tRRD_L=0
 734 tRTP=7500
 735 tRTW=2500
 736 tWR=15000
 737 tWTR=7500
 738 tXAW=30000
 739 tXP=0
 740 tXPDLL=0
 741 tXS=0
 742 tXSDLL=0
 743 write_buffer_size=64
 744 write_high_thresh_perc=85
 745 write_low_thresh_perc=50
 746 port=system.membus.master[0]
 747
 748 [system.voltage_domain]
 749 type=VoltageDomain
 750 eventq_index=0
 751 voltage=1.000000
 752