regressions: update due to cache latency fix
[gem5.git] / tests / quick / se / 00.hello / ref / alpha / linux / o3-timing / simout
1 Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
2 Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
3 gem5 Simulator System. http://gem5.org
4 gem5 is copyrighted software; use the --copyright option for details.
5
6 gem5 compiled Mar 26 2013 14:38:52
7 gem5 started Mar 26 2013 14:39:12
8 gem5 executing on ribera.cs.wisc.edu
9 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
10 Global frequency set at 1000000000000 ticks per second
11 info: Entering event queue @ 0. Starting simulation...
12 info: Increasing stack size by one page.
13 Hello world!
14 Exiting @ tick 16032500 because target called exit()