2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000016 # Number of seconds simulated
4 sim_ticks 15653000 # Number of ticks simulated
5 final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 11804 # Simulator instruction rate (inst/s)
8 host_op_rate 11803 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 28994780 # Simulator tick rate (ticks/s)
10 host_mem_usage 217308 # Number of bytes of host memory used
11 host_seconds 0.54 # Real time elapsed on the host
12 sim_insts 6372 # Number of instructions simulated
13 sim_ops 6372 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 31168 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 487 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 487 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 31168 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 15508000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 487 # Categorize read packet sizes
81 system.physmem.readPktSize::7 0 # Categorize read packet sizes
82 system.physmem.readPktSize::8 0 # Categorize read packet sizes
83 system.physmem.writePktSize::0 0 # categorize write packet sizes
84 system.physmem.writePktSize::1 0 # categorize write packet sizes
85 system.physmem.writePktSize::2 0 # categorize write packet sizes
86 system.physmem.writePktSize::3 0 # categorize write packet sizes
87 system.physmem.writePktSize::4 0 # categorize write packet sizes
88 system.physmem.writePktSize::5 0 # categorize write packet sizes
89 system.physmem.writePktSize::6 0 # categorize write packet sizes
90 system.physmem.writePktSize::7 0 # categorize write packet sizes
91 system.physmem.writePktSize::8 0 # categorize write packet sizes
92 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98 system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101 system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
134 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167 system.physmem.totQLat 2668987 # Total cycles spent in queuing delays
168 system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests
169 system.physmem.totBusLat 1948000 # Total cycles spent in databus access
170 system.physmem.totBankLat 7798000 # Total cycles spent in bank access
171 system.physmem.avgQLat 5480.47 # Average queueing delay per request
172 system.physmem.avgBankLat 16012.32 # Average bank access latency per request
173 system.physmem.avgBusLat 4000.00 # Average bus latency per request
174 system.physmem.avgMemAccLat 25492.79 # Average memory access latency
175 system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s
176 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177 system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s
178 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180 system.physmem.busUtil 12.44 # Data bus utilization in percentage
181 system.physmem.avgRdQLen 0.79 # Average read queue length over time
182 system.physmem.avgWrQLen 0.00 # Average write queue length over time
183 system.physmem.readRowHits 417 # Number of row buffer hits during reads
184 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185 system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads
186 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187 system.physmem.avgGap 31843.94 # Average gap between requests
188 system.cpu.dtb.fetch_hits 0 # ITB hits
189 system.cpu.dtb.fetch_misses 0 # ITB misses
190 system.cpu.dtb.fetch_acv 0 # ITB acv
191 system.cpu.dtb.fetch_accesses 0 # ITB accesses
192 system.cpu.dtb.read_hits 2048 # DTB read hits
193 system.cpu.dtb.read_misses 58 # DTB read misses
194 system.cpu.dtb.read_acv 0 # DTB read access violations
195 system.cpu.dtb.read_accesses 2106 # DTB read accesses
196 system.cpu.dtb.write_hits 1074 # DTB write hits
197 system.cpu.dtb.write_misses 32 # DTB write misses
198 system.cpu.dtb.write_acv 0 # DTB write access violations
199 system.cpu.dtb.write_accesses 1106 # DTB write accesses
200 system.cpu.dtb.data_hits 3122 # DTB hits
201 system.cpu.dtb.data_misses 90 # DTB misses
202 system.cpu.dtb.data_acv 0 # DTB access violations
203 system.cpu.dtb.data_accesses 3212 # DTB accesses
204 system.cpu.itb.fetch_hits 2395 # ITB hits
205 system.cpu.itb.fetch_misses 38 # ITB misses
206 system.cpu.itb.fetch_acv 0 # ITB acv
207 system.cpu.itb.fetch_accesses 2433 # ITB accesses
208 system.cpu.itb.read_hits 0 # DTB read hits
209 system.cpu.itb.read_misses 0 # DTB read misses
210 system.cpu.itb.read_acv 0 # DTB read access violations
211 system.cpu.itb.read_accesses 0 # DTB read accesses
212 system.cpu.itb.write_hits 0 # DTB write hits
213 system.cpu.itb.write_misses 0 # DTB write misses
214 system.cpu.itb.write_acv 0 # DTB write access violations
215 system.cpu.itb.write_accesses 0 # DTB write accesses
216 system.cpu.itb.data_hits 0 # DTB hits
217 system.cpu.itb.data_misses 0 # DTB misses
218 system.cpu.itb.data_acv 0 # DTB access violations
219 system.cpu.itb.data_accesses 0 # DTB accesses
220 system.cpu.workload.num_syscalls 17 # Number of system calls
221 system.cpu.numCycles 31307 # number of cpu cycles simulated
222 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
223 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
224 system.cpu.BPredUnit.lookups 2894 # Number of BP lookups
225 system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted
226 system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect
227 system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups
228 system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits
229 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
230 system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target.
231 system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions.
232 system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss
233 system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed
234 system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered
235 system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken
236 system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked
237 system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing
238 system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked
239 system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
240 system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps
241 system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched
242 system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed
243 system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total)
244 system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total)
245 system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total)
246 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
247 system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total)
248 system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total)
252 system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total)
253 system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
258 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
259 system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total)
260 system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle
261 system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle
262 system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle
263 system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked
264 system.cpu.decode.RunCycles 2779 # Number of cycles decode is running
265 system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking
266 system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing
267 system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch
268 system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
269 system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode
270 system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode
271 system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing
272 system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle
273 system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking
274 system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst
275 system.cpu.rename.RunCycles 2656 # Number of cycles rename is running
276 system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking
277 system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename
278 system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full
279 system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed
280 system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made
281 system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups
282 system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
283 system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
284 system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
285 system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
286 system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
287 system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer
288 system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit.
289 system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit.
290 system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
291 system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
292 system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec)
293 system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
294 system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued
295 system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
296 system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling
297 system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph
298 system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
299 system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle
300 system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle
301 system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle
302 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
303 system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle
304 system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle
305 system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle
306 system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle
310 system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle
311 system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle
312 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle
316 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
317 system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available
318 system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available
319 system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available
320 system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available
321 system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available
322 system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available
323 system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available
324 system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available
325 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
326 system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available
327 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available
328 system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available
329 system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available
330 system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available
331 system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available
332 system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
346 system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available
347 system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available
348 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
349 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
350 system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
351 system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued
352 system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued
353 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued
354 system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued
355 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued
356 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued
357 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued
358 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued
359 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued
360 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued
361 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued
362 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued
363 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued
364 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued
365 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued
366 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued
380 system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued
381 system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued
382 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
383 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
384 system.cpu.iq.FU_type_0::total 10660 # Type of FU issued
385 system.cpu.iq.rate 0.340499 # Inst issue rate
386 system.cpu.iq.fu_busy_cnt 114 # FU busy when requested
387 system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst)
388 system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads
389 system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes
390 system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses
391 system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
392 system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
393 system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
394 system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses
395 system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
396 system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
397 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
398 system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed
399 system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
400 system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
401 system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed
402 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
403 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
404 system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
405 system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked
406 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
407 system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing
408 system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking
409 system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
410 system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ
411 system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
412 system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions
413 system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions
414 system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
415 system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
416 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
417 system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
418 system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly
419 system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly
420 system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute
421 system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions
422 system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed
423 system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute
424 system.cpu.iew.exec_swp 0 # number of swp insts executed
425 system.cpu.iew.exec_nop 88 # number of nop insts executed
426 system.cpu.iew.exec_refs 3225 # number of memory reference insts executed
427 system.cpu.iew.exec_branches 1609 # Number of branches executed
428 system.cpu.iew.exec_stores 1108 # Number of stores executed
429 system.cpu.iew.exec_rate 0.319833 # Inst execution rate
430 system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit
431 system.cpu.iew.wb_count 9555 # cumulative count of insts written-back
432 system.cpu.iew.wb_producers 5016 # num instructions producing a value
433 system.cpu.iew.wb_consumers 6802 # num instructions consuming a value
434 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
435 system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle
436 system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back
437 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
438 system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit
439 system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
440 system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted
441 system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle
442 system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle
443 system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle
444 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
445 system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle
446 system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle
447 system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle
448 system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle
453 system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle
454 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle
458 system.cpu.commit.committedInsts 6389 # Number of instructions committed
459 system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
460 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
461 system.cpu.commit.refs 2048 # Number of memory references committed
462 system.cpu.commit.loads 1183 # Number of loads committed
463 system.cpu.commit.membars 0 # Number of memory barriers committed
464 system.cpu.commit.branches 1050 # Number of branches committed
465 system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
466 system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
467 system.cpu.commit.function_calls 127 # Number of function calls committed.
468 system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached
469 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
470 system.cpu.rob.rob_reads 25734 # The number of ROB reads
471 system.cpu.rob.rob_writes 27303 # The number of ROB writes
472 system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
473 system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling
474 system.cpu.committedInsts 6372 # Number of Instructions Simulated
475 system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
476 system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
477 system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction
478 system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads
479 system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle
480 system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads
481 system.cpu.int_regfile_reads 12695 # number of integer regfile reads
482 system.cpu.int_regfile_writes 7186 # number of integer regfile writes
483 system.cpu.fp_regfile_reads 8 # number of floating regfile reads
484 system.cpu.fp_regfile_writes 2 # number of floating regfile writes
485 system.cpu.misc_regfile_reads 1 # number of misc regfile reads
486 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
487 system.cpu.icache.replacements 0 # number of replacements
488 system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use
489 system.cpu.icache.total_refs 1916 # Total number of references to valid blocks.
490 system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
491 system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks.
492 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
493 system.cpu.icache.occ_blocks::cpu.inst 160.377030 # Average occupied blocks per requestor
494 system.cpu.icache.occ_percent::cpu.inst 0.078309 # Average percentage of cache occupancy
495 system.cpu.icache.occ_percent::total 0.078309 # Average percentage of cache occupancy
496 system.cpu.icache.ReadReq_hits::cpu.inst 1916 # number of ReadReq hits
497 system.cpu.icache.ReadReq_hits::total 1916 # number of ReadReq hits
498 system.cpu.icache.demand_hits::cpu.inst 1916 # number of demand (read+write) hits
499 system.cpu.icache.demand_hits::total 1916 # number of demand (read+write) hits
500 system.cpu.icache.overall_hits::cpu.inst 1916 # number of overall hits
501 system.cpu.icache.overall_hits::total 1916 # number of overall hits
502 system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses
503 system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses
504 system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses
505 system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses
506 system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses
507 system.cpu.icache.overall_misses::total 479 # number of overall misses
508 system.cpu.icache.ReadReq_miss_latency::cpu.inst 21334000 # number of ReadReq miss cycles
509 system.cpu.icache.ReadReq_miss_latency::total 21334000 # number of ReadReq miss cycles
510 system.cpu.icache.demand_miss_latency::cpu.inst 21334000 # number of demand (read+write) miss cycles
511 system.cpu.icache.demand_miss_latency::total 21334000 # number of demand (read+write) miss cycles
512 system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles
513 system.cpu.icache.overall_miss_latency::total 21334000 # number of overall miss cycles
514 system.cpu.icache.ReadReq_accesses::cpu.inst 2395 # number of ReadReq accesses(hits+misses)
515 system.cpu.icache.ReadReq_accesses::total 2395 # number of ReadReq accesses(hits+misses)
516 system.cpu.icache.demand_accesses::cpu.inst 2395 # number of demand (read+write) accesses
517 system.cpu.icache.demand_accesses::total 2395 # number of demand (read+write) accesses
518 system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses
519 system.cpu.icache.overall_accesses::total 2395 # number of overall (read+write) accesses
520 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses
521 system.cpu.icache.ReadReq_miss_rate::total 0.200000 # miss rate for ReadReq accesses
522 system.cpu.icache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses
523 system.cpu.icache.demand_miss_rate::total 0.200000 # miss rate for demand accesses
524 system.cpu.icache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses
525 system.cpu.icache.overall_miss_rate::total 0.200000 # miss rate for overall accesses
526 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44538.622129 # average ReadReq miss latency
527 system.cpu.icache.ReadReq_avg_miss_latency::total 44538.622129 # average ReadReq miss latency
528 system.cpu.icache.demand_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency
529 system.cpu.icache.demand_avg_miss_latency::total 44538.622129 # average overall miss latency
530 system.cpu.icache.overall_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency
531 system.cpu.icache.overall_avg_miss_latency::total 44538.622129 # average overall miss latency
532 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
533 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
534 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
535 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
536 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
537 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
538 system.cpu.icache.fast_writes 0 # number of fast writes performed
539 system.cpu.icache.cache_copies 0 # number of cache copies performed
540 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits
541 system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits
542 system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits
543 system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
544 system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits
545 system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits
546 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
547 system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses
548 system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
549 system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses
550 system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
551 system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses
552 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15306500 # number of ReadReq MSHR miss cycles
553 system.cpu.icache.ReadReq_mshr_miss_latency::total 15306500 # number of ReadReq MSHR miss cycles
554 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15306500 # number of demand (read+write) MSHR miss cycles
555 system.cpu.icache.demand_mshr_miss_latency::total 15306500 # number of demand (read+write) MSHR miss cycles
556 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15306500 # number of overall MSHR miss cycles
557 system.cpu.icache.overall_mshr_miss_latency::total 15306500 # number of overall MSHR miss cycles
558 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for ReadReq accesses
559 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131106 # mshr miss rate for ReadReq accesses
560 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for demand accesses
561 system.cpu.icache.demand_mshr_miss_rate::total 0.131106 # mshr miss rate for demand accesses
562 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for overall accesses
563 system.cpu.icache.overall_mshr_miss_rate::total 0.131106 # mshr miss rate for overall accesses
564 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48746.815287 # average ReadReq mshr miss latency
565 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48746.815287 # average ReadReq mshr miss latency
566 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency
567 system.cpu.icache.demand_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency
568 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency
569 system.cpu.icache.overall_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency
570 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
571 system.cpu.dcache.replacements 0 # number of replacements
572 system.cpu.dcache.tagsinuse 107.831538 # Cycle average of tags in use
573 system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks.
574 system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
575 system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks.
576 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
577 system.cpu.dcache.occ_blocks::cpu.data 107.831538 # Average occupied blocks per requestor
578 system.cpu.dcache.occ_percent::cpu.data 0.026326 # Average percentage of cache occupancy
579 system.cpu.dcache.occ_percent::total 0.026326 # Average percentage of cache occupancy
580 system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits
581 system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits
582 system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
583 system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
584 system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits
585 system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits
586 system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits
587 system.cpu.dcache.overall_hits::total 2240 # number of overall hits
588 system.cpu.dcache.ReadReq_misses::cpu.data 160 # number of ReadReq misses
589 system.cpu.dcache.ReadReq_misses::total 160 # number of ReadReq misses
590 system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
591 system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
592 system.cpu.dcache.demand_misses::cpu.data 519 # number of demand (read+write) misses
593 system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses
594 system.cpu.dcache.overall_misses::cpu.data 519 # number of overall misses
595 system.cpu.dcache.overall_misses::total 519 # number of overall misses
596 system.cpu.dcache.ReadReq_miss_latency::cpu.data 8308500 # number of ReadReq miss cycles
597 system.cpu.dcache.ReadReq_miss_latency::total 8308500 # number of ReadReq miss cycles
598 system.cpu.dcache.WriteReq_miss_latency::cpu.data 15746484 # number of WriteReq miss cycles
599 system.cpu.dcache.WriteReq_miss_latency::total 15746484 # number of WriteReq miss cycles
600 system.cpu.dcache.demand_miss_latency::cpu.data 24054984 # number of demand (read+write) miss cycles
601 system.cpu.dcache.demand_miss_latency::total 24054984 # number of demand (read+write) miss cycles
602 system.cpu.dcache.overall_miss_latency::cpu.data 24054984 # number of overall miss cycles
603 system.cpu.dcache.overall_miss_latency::total 24054984 # number of overall miss cycles
604 system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
605 system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
606 system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
607 system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
608 system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
609 system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
610 system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
611 system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
612 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084477 # miss rate for ReadReq accesses
613 system.cpu.dcache.ReadReq_miss_rate::total 0.084477 # miss rate for ReadReq accesses
614 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
615 system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
616 system.cpu.dcache.demand_miss_rate::cpu.data 0.188112 # miss rate for demand accesses
617 system.cpu.dcache.demand_miss_rate::total 0.188112 # miss rate for demand accesses
618 system.cpu.dcache.overall_miss_rate::cpu.data 0.188112 # miss rate for overall accesses
619 system.cpu.dcache.overall_miss_rate::total 0.188112 # miss rate for overall accesses
620 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51928.125000 # average ReadReq miss latency
621 system.cpu.dcache.ReadReq_avg_miss_latency::total 51928.125000 # average ReadReq miss latency
622 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43862.072423 # average WriteReq miss latency
623 system.cpu.dcache.WriteReq_avg_miss_latency::total 43862.072423 # average WriteReq miss latency
624 system.cpu.dcache.demand_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency
625 system.cpu.dcache.demand_avg_miss_latency::total 46348.716763 # average overall miss latency
626 system.cpu.dcache.overall_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency
627 system.cpu.dcache.overall_avg_miss_latency::total 46348.716763 # average overall miss latency
628 system.cpu.dcache.blocked_cycles::no_mshrs 810 # number of cycles access was blocked
629 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
630 system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
631 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
632 system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.928571 # average number of cycles each access was blocked
633 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
634 system.cpu.dcache.fast_writes 0 # number of fast writes performed
635 system.cpu.dcache.cache_copies 0 # number of cache copies performed
636 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
637 system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
638 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
639 system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
640 system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits
641 system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits
642 system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits
643 system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits
644 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
645 system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
646 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
647 system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
648 system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
649 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
650 system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
651 system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
652 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6029500 # number of ReadReq MSHR miss cycles
653 system.cpu.dcache.ReadReq_mshr_miss_latency::total 6029500 # number of ReadReq MSHR miss cycles
654 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3803500 # number of WriteReq MSHR miss cycles
655 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3803500 # number of WriteReq MSHR miss cycles
656 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9833000 # number of demand (read+write) MSHR miss cycles
657 system.cpu.dcache.demand_mshr_miss_latency::total 9833000 # number of demand (read+write) MSHR miss cycles
658 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9833000 # number of overall MSHR miss cycles
659 system.cpu.dcache.overall_mshr_miss_latency::total 9833000 # number of overall MSHR miss cycles
660 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses
661 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses
662 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
663 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
664 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
665 system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
666 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
667 system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
668 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59698.019802 # average ReadReq mshr miss latency
669 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59698.019802 # average ReadReq mshr miss latency
670 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52102.739726 # average WriteReq mshr miss latency
671 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52102.739726 # average WriteReq mshr miss latency
672 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency
673 system.cpu.dcache.demand_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency
674 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency
675 system.cpu.dcache.overall_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency
676 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
677 system.cpu.l2cache.replacements 0 # number of replacements
678 system.cpu.l2cache.tagsinuse 220.955415 # Cycle average of tags in use
679 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
680 system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks.
681 system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks.
682 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
683 system.cpu.l2cache.occ_blocks::cpu.inst 160.525117 # Average occupied blocks per requestor
684 system.cpu.l2cache.occ_blocks::cpu.data 60.430298 # Average occupied blocks per requestor
685 system.cpu.l2cache.occ_percent::cpu.inst 0.004899 # Average percentage of cache occupancy
686 system.cpu.l2cache.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy
687 system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy
688 system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
689 system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
690 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
691 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
692 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
693 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
694 system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses
695 system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
696 system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses
697 system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
698 system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
699 system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses
700 system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses
701 system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses
702 system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses
703 system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
704 system.cpu.l2cache.overall_misses::total 487 # number of overall misses
705 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14981000 # number of ReadReq miss cycles
706 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5921000 # number of ReadReq miss cycles
707 system.cpu.l2cache.ReadReq_miss_latency::total 20902000 # number of ReadReq miss cycles
708 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3727500 # number of ReadExReq miss cycles
709 system.cpu.l2cache.ReadExReq_miss_latency::total 3727500 # number of ReadExReq miss cycles
710 system.cpu.l2cache.demand_miss_latency::cpu.inst 14981000 # number of demand (read+write) miss cycles
711 system.cpu.l2cache.demand_miss_latency::cpu.data 9648500 # number of demand (read+write) miss cycles
712 system.cpu.l2cache.demand_miss_latency::total 24629500 # number of demand (read+write) miss cycles
713 system.cpu.l2cache.overall_miss_latency::cpu.inst 14981000 # number of overall miss cycles
714 system.cpu.l2cache.overall_miss_latency::cpu.data 9648500 # number of overall miss cycles
715 system.cpu.l2cache.overall_miss_latency::total 24629500 # number of overall miss cycles
716 system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses)
717 system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
718 system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
719 system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
720 system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
721 system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses
722 system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses
723 system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses
724 system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses
725 system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses
726 system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses
727 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses
728 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
729 system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses
730 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
731 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
732 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses
733 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
734 system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses
735 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses
736 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
737 system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses
738 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47862.619808 # average ReadReq miss latency
739 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58623.762376 # average ReadReq miss latency
740 system.cpu.l2cache.ReadReq_avg_miss_latency::total 50487.922705 # average ReadReq miss latency
741 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51061.643836 # average ReadExReq miss latency
742 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51061.643836 # average ReadExReq miss latency
743 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency
744 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency
745 system.cpu.l2cache.demand_avg_miss_latency::total 50573.921971 # average overall miss latency
746 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency
747 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency
748 system.cpu.l2cache.overall_avg_miss_latency::total 50573.921971 # average overall miss latency
749 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
750 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
751 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
752 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
753 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
754 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
755 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
756 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
757 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
758 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
759 system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses
760 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
761 system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
762 system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
763 system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
764 system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses
765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
766 system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
767 system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses
768 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11042494 # number of ReadReq MSHR miss cycles
769 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4678584 # number of ReadReq MSHR miss cycles
770 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15721078 # number of ReadReq MSHR miss cycles
771 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2834058 # number of ReadExReq MSHR miss cycles
772 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2834058 # number of ReadExReq MSHR miss cycles
773 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11042494 # number of demand (read+write) MSHR miss cycles
774 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7512642 # number of demand (read+write) MSHR miss cycles
775 system.cpu.l2cache.demand_mshr_miss_latency::total 18555136 # number of demand (read+write) MSHR miss cycles
776 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11042494 # number of overall MSHR miss cycles
777 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7512642 # number of overall MSHR miss cycles
778 system.cpu.l2cache.overall_mshr_miss_latency::total 18555136 # number of overall MSHR miss cycles
779 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses
780 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
781 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses
782 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
783 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
784 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
785 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
786 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses
787 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
788 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
789 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses
790 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35279.533546 # average ReadReq mshr miss latency
791 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46322.613861 # average ReadReq mshr miss latency
792 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37973.618357 # average ReadReq mshr miss latency
793 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38822.712329 # average ReadExReq mshr miss latency
794 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38822.712329 # average ReadExReq mshr miss latency
795 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency
796 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency
797 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency
798 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency
799 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency
800 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency
801 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
803 ---------- End Simulation Statistics ----------
projects / gem5.git / blob