c1171633d9d014db33acf73bfd940570643a4a6b
[gem5.git] / tests / quick / se / 00.hello / ref / alpha / linux / simple-atomic / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=false
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=System
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14 boot_osflags=a
15 cache_line_size=64
16 clk_domain=system.clk_domain
17 default_p_state=UNDEFINED
18 eventq_index=0
19 exit_on_work_items=false
20 init_param=0
21 kernel=
22 kernel_addr_check=true
23 load_addr_mask=1099511627775
24 load_offset=0
25 mem_mode=atomic
26 mem_ranges=
27 memories=system.physmem
28 mmap_using_noreserve=false
29 multi_thread=false
30 num_work_ids=16
31 p_state_clk_gate_bins=20
32 p_state_clk_gate_max=1000000000000
33 p_state_clk_gate_min=1000
34 power_model=Null
35 readfile=
36 symbolfile=
37 thermal_components=
38 thermal_model=Null
39 work_begin_ckpt_count=0
40 work_begin_cpu_id_exit=-1
41 work_begin_exit_count=0
42 work_cpus_ckpt_count=0
43 work_end_ckpt_count=0
44 work_end_exit_count=0
45 work_item_id=-1
46 system_port=system.membus.slave[0]
47
48 [system.clk_domain]
49 type=SrcClockDomain
50 clock=1000
51 domain_id=-1
52 eventq_index=0
53 init_perf_level=0
54 voltage_domain=system.voltage_domain
55
56 [system.cpu]
57 type=AtomicSimpleCPU
58 children=dtb interrupts isa itb tracer workload
59 branchPred=Null
60 checker=Null
61 clk_domain=system.cpu_clk_domain
62 cpu_id=0
63 default_p_state=UNDEFINED
64 do_checkpoint_insts=true
65 do_quiesce=true
66 do_statistics_insts=true
67 dtb=system.cpu.dtb
68 eventq_index=0
69 fastmem=false
70 function_trace=false
71 function_trace_start=0
72 interrupts=system.cpu.interrupts
73 isa=system.cpu.isa
74 itb=system.cpu.itb
75 max_insts_all_threads=0
76 max_insts_any_thread=0
77 max_loads_all_threads=0
78 max_loads_any_thread=0
79 numThreads=1
80 p_state_clk_gate_bins=20
81 p_state_clk_gate_max=1000000000000
82 p_state_clk_gate_min=1000
83 power_model=Null
84 profile=0
85 progress_interval=0
86 simpoint_start_insts=
87 simulate_data_stalls=false
88 simulate_inst_stalls=false
89 socket_id=0
90 switched_out=false
91 system=system
92 tracer=system.cpu.tracer
93 width=1
94 workload=system.cpu.workload
95 dcache_port=system.membus.slave[2]
96 icache_port=system.membus.slave[1]
97
98 [system.cpu.dtb]
99 type=AlphaTLB
100 eventq_index=0
101 size=64
102
103 [system.cpu.interrupts]
104 type=AlphaInterrupts
105 eventq_index=0
106
107 [system.cpu.isa]
108 type=AlphaISA
109 eventq_index=0
110 system=system
111
112 [system.cpu.itb]
113 type=AlphaTLB
114 eventq_index=0
115 size=48
116
117 [system.cpu.tracer]
118 type=ExeTracer
119 eventq_index=0
120
121 [system.cpu.workload]
122 type=LiveProcess
123 cmd=hello
124 cwd=
125 drivers=
126 egid=100
127 env=
128 errout=cerr
129 euid=100
130 eventq_index=0
131 executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
132 gid=100
133 input=cin
134 kvmInSE=false
135 max_stack_size=67108864
136 output=cout
137 pid=100
138 ppid=99
139 simpoint=0
140 system=system
141 uid=100
142 useArchPT=false
143
144 [system.cpu_clk_domain]
145 type=SrcClockDomain
146 clock=500
147 domain_id=-1
148 eventq_index=0
149 init_perf_level=0
150 voltage_domain=system.voltage_domain
151
152 [system.dvfs_handler]
153 type=DVFSHandler
154 domains=
155 enable=false
156 eventq_index=0
157 sys_clk_domain=system.clk_domain
158 transition_latency=100000000
159
160 [system.membus]
161 type=CoherentXBar
162 clk_domain=system.clk_domain
163 default_p_state=UNDEFINED
164 eventq_index=0
165 forward_latency=4
166 frontend_latency=3
167 p_state_clk_gate_bins=20
168 p_state_clk_gate_max=1000000000000
169 p_state_clk_gate_min=1000
170 point_of_coherency=true
171 power_model=Null
172 response_latency=2
173 snoop_filter=Null
174 snoop_response_latency=4
175 system=system
176 use_default_range=false
177 width=16
178 master=system.physmem.port
179 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
180
181 [system.physmem]
182 type=SimpleMemory
183 bandwidth=73.000000
184 clk_domain=system.clk_domain
185 conf_table_reported=true
186 default_p_state=UNDEFINED
187 eventq_index=0
188 in_addr_map=true
189 latency=30000
190 latency_var=0
191 null=false
192 p_state_clk_gate_bins=20
193 p_state_clk_gate_max=1000000000000
194 p_state_clk_gate_min=1000
195 power_model=Null
196 range=0:134217727
197 port=system.membus.master[0]
198
199 [system.voltage_domain]
200 type=VoltageDomain
201 eventq_index=0
202 voltage=1.000000
203