c1171633d9d014db33acf73bfd940570643a4a6b
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
16 clk_domain=system.clk_domain
17 default_p_state=UNDEFINED
19 exit_on_work_items=false
22 kernel_addr_check=true
23 load_addr_mask=1099511627775
27 memories=system.physmem
28 mmap_using_noreserve=false
31 p_state_clk_gate_bins=20
32 p_state_clk_gate_max=1000000000000
33 p_state_clk_gate_min=1000
39 work_begin_ckpt_count=0
40 work_begin_cpu_id_exit=-1
41 work_begin_exit_count=0
42 work_cpus_ckpt_count=0
46 system_port=system.membus.slave[0]
54 voltage_domain=system.voltage_domain
58 children=dtb interrupts isa itb tracer workload
61 clk_domain=system.cpu_clk_domain
63 default_p_state=UNDEFINED
64 do_checkpoint_insts=true
66 do_statistics_insts=true
71 function_trace_start=0
72 interrupts=system.cpu.interrupts
75 max_insts_all_threads=0
76 max_insts_any_thread=0
77 max_loads_all_threads=0
78 max_loads_any_thread=0
80 p_state_clk_gate_bins=20
81 p_state_clk_gate_max=1000000000000
82 p_state_clk_gate_min=1000
87 simulate_data_stalls=false
88 simulate_inst_stalls=false
92 tracer=system.cpu.tracer
94 workload=system.cpu.workload
95 dcache_port=system.membus.slave[2]
96 icache_port=system.membus.slave[1]
103 [system.cpu.interrupts]
121 [system.cpu.workload]
131 executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
135 max_stack_size=67108864
144 [system.cpu_clk_domain]
150 voltage_domain=system.voltage_domain
152 [system.dvfs_handler]
157 sys_clk_domain=system.clk_domain
158 transition_latency=100000000
162 clk_domain=system.clk_domain
163 default_p_state=UNDEFINED
167 p_state_clk_gate_bins=20
168 p_state_clk_gate_max=1000000000000
169 p_state_clk_gate_min=1000
170 point_of_coherency=true
174 snoop_response_latency=4
176 use_default_range=false
178 master=system.physmem.port
179 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
184 clk_domain=system.clk_domain
185 conf_table_reported=true
186 default_p_state=UNDEFINED
192 p_state_clk_gate_bins=20
193 p_state_clk_gate_max=1000000000000
194 p_state_clk_gate_min=1000
197 port=system.membus.master[0]
199 [system.voltage_domain]