62573b17c7d71fc21d0abee23ffb96f171cbb4c2
[gem5.git] / tests / quick / se / 00.hello / ref / alpha / linux / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=false
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=System
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14 boot_osflags=a
15 cache_line_size=64
16 clk_domain=system.clk_domain
17 eventq_index=0
18 init_param=0
19 kernel=
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
22 load_offset=0
23 mem_mode=timing
24 mem_ranges=
25 memories=system.physmem
26 mmap_using_noreserve=false
27 multi_thread=false
28 num_work_ids=16
29 readfile=
30 symbolfile=
31 work_begin_ckpt_count=0
32 work_begin_cpu_id_exit=-1
33 work_begin_exit_count=0
34 work_cpus_ckpt_count=0
35 work_end_ckpt_count=0
36 work_end_exit_count=0
37 work_item_id=-1
38 system_port=system.membus.slave[0]
39
40 [system.clk_domain]
41 type=SrcClockDomain
42 clock=1000
43 domain_id=-1
44 eventq_index=0
45 init_perf_level=0
46 voltage_domain=system.voltage_domain
47
48 [system.cpu]
49 type=TimingSimpleCPU
50 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
51 branchPred=Null
52 checker=Null
53 clk_domain=system.cpu_clk_domain
54 cpu_id=0
55 do_checkpoint_insts=true
56 do_quiesce=true
57 do_statistics_insts=true
58 dtb=system.cpu.dtb
59 eventq_index=0
60 function_trace=false
61 function_trace_start=0
62 interrupts=system.cpu.interrupts
63 isa=system.cpu.isa
64 itb=system.cpu.itb
65 max_insts_all_threads=0
66 max_insts_any_thread=0
67 max_loads_all_threads=0
68 max_loads_any_thread=0
69 numThreads=1
70 profile=0
71 progress_interval=0
72 simpoint_start_insts=
73 socket_id=0
74 switched_out=false
75 system=system
76 tracer=system.cpu.tracer
77 workload=system.cpu.workload
78 dcache_port=system.cpu.dcache.cpu_side
79 icache_port=system.cpu.icache.cpu_side
80
81 [system.cpu.dcache]
82 type=Cache
83 children=tags
84 addr_ranges=0:18446744073709551615
85 assoc=2
86 clk_domain=system.cpu_clk_domain
87 clusivity=mostly_incl
88 demand_mshr_reserve=1
89 eventq_index=0
90 forward_snoops=true
91 hit_latency=2
92 is_read_only=false
93 max_miss_count=0
94 mshrs=4
95 prefetch_on_access=false
96 prefetcher=Null
97 response_latency=2
98 sequential_access=false
99 size=262144
100 system=system
101 tags=system.cpu.dcache.tags
102 tgts_per_mshr=20
103 write_buffers=8
104 writeback_clean=false
105 cpu_side=system.cpu.dcache_port
106 mem_side=system.cpu.toL2Bus.slave[1]
107
108 [system.cpu.dcache.tags]
109 type=LRU
110 assoc=2
111 block_size=64
112 clk_domain=system.cpu_clk_domain
113 eventq_index=0
114 hit_latency=2
115 sequential_access=false
116 size=262144
117
118 [system.cpu.dtb]
119 type=AlphaTLB
120 eventq_index=0
121 size=64
122
123 [system.cpu.icache]
124 type=Cache
125 children=tags
126 addr_ranges=0:18446744073709551615
127 assoc=2
128 clk_domain=system.cpu_clk_domain
129 clusivity=mostly_incl
130 demand_mshr_reserve=1
131 eventq_index=0
132 forward_snoops=true
133 hit_latency=2
134 is_read_only=true
135 max_miss_count=0
136 mshrs=4
137 prefetch_on_access=false
138 prefetcher=Null
139 response_latency=2
140 sequential_access=false
141 size=131072
142 system=system
143 tags=system.cpu.icache.tags
144 tgts_per_mshr=20
145 write_buffers=8
146 writeback_clean=true
147 cpu_side=system.cpu.icache_port
148 mem_side=system.cpu.toL2Bus.slave[0]
149
150 [system.cpu.icache.tags]
151 type=LRU
152 assoc=2
153 block_size=64
154 clk_domain=system.cpu_clk_domain
155 eventq_index=0
156 hit_latency=2
157 sequential_access=false
158 size=131072
159
160 [system.cpu.interrupts]
161 type=AlphaInterrupts
162 eventq_index=0
163
164 [system.cpu.isa]
165 type=AlphaISA
166 eventq_index=0
167 system=system
168
169 [system.cpu.itb]
170 type=AlphaTLB
171 eventq_index=0
172 size=48
173
174 [system.cpu.l2cache]
175 type=Cache
176 children=tags
177 addr_ranges=0:18446744073709551615
178 assoc=8
179 clk_domain=system.cpu_clk_domain
180 clusivity=mostly_incl
181 demand_mshr_reserve=1
182 eventq_index=0
183 forward_snoops=true
184 hit_latency=20
185 is_read_only=false
186 max_miss_count=0
187 mshrs=20
188 prefetch_on_access=false
189 prefetcher=Null
190 response_latency=20
191 sequential_access=false
192 size=2097152
193 system=system
194 tags=system.cpu.l2cache.tags
195 tgts_per_mshr=12
196 write_buffers=8
197 writeback_clean=false
198 cpu_side=system.cpu.toL2Bus.master[0]
199 mem_side=system.membus.slave[1]
200
201 [system.cpu.l2cache.tags]
202 type=LRU
203 assoc=8
204 block_size=64
205 clk_domain=system.cpu_clk_domain
206 eventq_index=0
207 hit_latency=20
208 sequential_access=false
209 size=2097152
210
211 [system.cpu.toL2Bus]
212 type=CoherentXBar
213 children=snoop_filter
214 clk_domain=system.cpu_clk_domain
215 eventq_index=0
216 forward_latency=0
217 frontend_latency=1
218 response_latency=1
219 snoop_filter=system.cpu.toL2Bus.snoop_filter
220 snoop_response_latency=1
221 system=system
222 use_default_range=false
223 width=32
224 master=system.cpu.l2cache.cpu_side
225 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
226
227 [system.cpu.toL2Bus.snoop_filter]
228 type=SnoopFilter
229 eventq_index=0
230 lookup_latency=0
231 max_capacity=8388608
232 system=system
233
234 [system.cpu.tracer]
235 type=ExeTracer
236 eventq_index=0
237
238 [system.cpu.workload]
239 type=LiveProcess
240 cmd=hello
241 cwd=
242 drivers=
243 egid=100
244 env=
245 errout=cerr
246 euid=100
247 eventq_index=0
248 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
249 gid=100
250 input=cin
251 kvmInSE=false
252 max_stack_size=67108864
253 output=cout
254 pid=100
255 ppid=99
256 simpoint=0
257 system=system
258 uid=100
259 useArchPT=false
260
261 [system.cpu_clk_domain]
262 type=SrcClockDomain
263 clock=500
264 domain_id=-1
265 eventq_index=0
266 init_perf_level=0
267 voltage_domain=system.voltage_domain
268
269 [system.dvfs_handler]
270 type=DVFSHandler
271 domains=
272 enable=false
273 eventq_index=0
274 sys_clk_domain=system.clk_domain
275 transition_latency=100000000
276
277 [system.membus]
278 type=CoherentXBar
279 clk_domain=system.clk_domain
280 eventq_index=0
281 forward_latency=4
282 frontend_latency=3
283 response_latency=2
284 snoop_filter=Null
285 snoop_response_latency=4
286 system=system
287 use_default_range=false
288 width=16
289 master=system.physmem.port
290 slave=system.system_port system.cpu.l2cache.mem_side
291
292 [system.physmem]
293 type=SimpleMemory
294 bandwidth=73.000000
295 clk_domain=system.clk_domain
296 conf_table_reported=true
297 eventq_index=0
298 in_addr_map=true
299 latency=30000
300 latency_var=0
301 null=false
302 range=0:134217727
303 port=system.membus.master[0]
304
305 [system.voltage_domain]
306 type=VoltageDomain
307 eventq_index=0
308 voltage=1.000000
309