tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=TimingSimpleCPU
  58 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  59 branchPred=Null
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 cpu_id=0
  63 default_p_state=UNDEFINED
  64 do_checkpoint_insts=true
  65 do_quiesce=true
  66 do_statistics_insts=true
  67 dtb=system.cpu.dtb
  68 eventq_index=0
  69 function_trace=false
  70 function_trace_start=0
  71 interrupts=system.cpu.interrupts
  72 isa=system.cpu.isa
  73 itb=system.cpu.itb
  74 max_insts_all_threads=0
  75 max_insts_any_thread=0
  76 max_loads_all_threads=0
  77 max_loads_any_thread=0
  78 numThreads=1
  79 p_state_clk_gate_bins=20
  80 p_state_clk_gate_max=1000000000000
  81 p_state_clk_gate_min=1000
  82 power_model=Null
  83 profile=0
  84 progress_interval=0
  85 simpoint_start_insts=
  86 socket_id=0
  87 switched_out=false
  88 system=system
  89 tracer=system.cpu.tracer
  90 workload=system.cpu.workload
  91 dcache_port=system.cpu.dcache.cpu_side
  92 icache_port=system.cpu.icache.cpu_side
  93
  94 [system.cpu.dcache]
  95 type=Cache
  96 children=tags
  97 addr_ranges=0:18446744073709551615
  98 assoc=2
  99 clk_domain=system.cpu_clk_domain
 100 clusivity=mostly_incl
 101 default_p_state=UNDEFINED
 102 demand_mshr_reserve=1
 103 eventq_index=0
 104 hit_latency=2
 105 is_read_only=false
 106 max_miss_count=0
 107 mshrs=4
 108 p_state_clk_gate_bins=20
 109 p_state_clk_gate_max=1000000000000
 110 p_state_clk_gate_min=1000
 111 power_model=Null
 112 prefetch_on_access=false
 113 prefetcher=Null
 114 response_latency=2
 115 sequential_access=false
 116 size=262144
 117 system=system
 118 tags=system.cpu.dcache.tags
 119 tgts_per_mshr=20
 120 write_buffers=8
 121 writeback_clean=false
 122 cpu_side=system.cpu.dcache_port
 123 mem_side=system.cpu.toL2Bus.slave[1]
 124
 125 [system.cpu.dcache.tags]
 126 type=LRU
 127 assoc=2
 128 block_size=64
 129 clk_domain=system.cpu_clk_domain
 130 default_p_state=UNDEFINED
 131 eventq_index=0
 132 hit_latency=2
 133 p_state_clk_gate_bins=20
 134 p_state_clk_gate_max=1000000000000
 135 p_state_clk_gate_min=1000
 136 power_model=Null
 137 sequential_access=false
 138 size=262144
 139
 140 [system.cpu.dtb]
 141 type=AlphaTLB
 142 eventq_index=0
 143 size=64
 144
 145 [system.cpu.icache]
 146 type=Cache
 147 children=tags
 148 addr_ranges=0:18446744073709551615
 149 assoc=2
 150 clk_domain=system.cpu_clk_domain
 151 clusivity=mostly_incl
 152 default_p_state=UNDEFINED
 153 demand_mshr_reserve=1
 154 eventq_index=0
 155 hit_latency=2
 156 is_read_only=true
 157 max_miss_count=0
 158 mshrs=4
 159 p_state_clk_gate_bins=20
 160 p_state_clk_gate_max=1000000000000
 161 p_state_clk_gate_min=1000
 162 power_model=Null
 163 prefetch_on_access=false
 164 prefetcher=Null
 165 response_latency=2
 166 sequential_access=false
 167 size=131072
 168 system=system
 169 tags=system.cpu.icache.tags
 170 tgts_per_mshr=20
 171 write_buffers=8
 172 writeback_clean=true
 173 cpu_side=system.cpu.icache_port
 174 mem_side=system.cpu.toL2Bus.slave[0]
 175
 176 [system.cpu.icache.tags]
 177 type=LRU
 178 assoc=2
 179 block_size=64
 180 clk_domain=system.cpu_clk_domain
 181 default_p_state=UNDEFINED
 182 eventq_index=0
 183 hit_latency=2
 184 p_state_clk_gate_bins=20
 185 p_state_clk_gate_max=1000000000000
 186 p_state_clk_gate_min=1000
 187 power_model=Null
 188 sequential_access=false
 189 size=131072
 190
 191 [system.cpu.interrupts]
 192 type=AlphaInterrupts
 193 eventq_index=0
 194
 195 [system.cpu.isa]
 196 type=AlphaISA
 197 eventq_index=0
 198 system=system
 199
 200 [system.cpu.itb]
 201 type=AlphaTLB
 202 eventq_index=0
 203 size=48
 204
 205 [system.cpu.l2cache]
 206 type=Cache
 207 children=tags
 208 addr_ranges=0:18446744073709551615
 209 assoc=8
 210 clk_domain=system.cpu_clk_domain
 211 clusivity=mostly_incl
 212 default_p_state=UNDEFINED
 213 demand_mshr_reserve=1
 214 eventq_index=0
 215 hit_latency=20
 216 is_read_only=false
 217 max_miss_count=0
 218 mshrs=20
 219 p_state_clk_gate_bins=20
 220 p_state_clk_gate_max=1000000000000
 221 p_state_clk_gate_min=1000
 222 power_model=Null
 223 prefetch_on_access=false
 224 prefetcher=Null
 225 response_latency=20
 226 sequential_access=false
 227 size=2097152
 228 system=system
 229 tags=system.cpu.l2cache.tags
 230 tgts_per_mshr=12
 231 write_buffers=8
 232 writeback_clean=false
 233 cpu_side=system.cpu.toL2Bus.master[0]
 234 mem_side=system.membus.slave[1]
 235
 236 [system.cpu.l2cache.tags]
 237 type=LRU
 238 assoc=8
 239 block_size=64
 240 clk_domain=system.cpu_clk_domain
 241 default_p_state=UNDEFINED
 242 eventq_index=0
 243 hit_latency=20
 244 p_state_clk_gate_bins=20
 245 p_state_clk_gate_max=1000000000000
 246 p_state_clk_gate_min=1000
 247 power_model=Null
 248 sequential_access=false
 249 size=2097152
 250
 251 [system.cpu.toL2Bus]
 252 type=CoherentXBar
 253 children=snoop_filter
 254 clk_domain=system.cpu_clk_domain
 255 default_p_state=UNDEFINED
 256 eventq_index=0
 257 forward_latency=0
 258 frontend_latency=1
 259 p_state_clk_gate_bins=20
 260 p_state_clk_gate_max=1000000000000
 261 p_state_clk_gate_min=1000
 262 point_of_coherency=false
 263 power_model=Null
 264 response_latency=1
 265 snoop_filter=system.cpu.toL2Bus.snoop_filter
 266 snoop_response_latency=1
 267 system=system
 268 use_default_range=false
 269 width=32
 270 master=system.cpu.l2cache.cpu_side
 271 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 272
 273 [system.cpu.toL2Bus.snoop_filter]
 274 type=SnoopFilter
 275 eventq_index=0
 276 lookup_latency=0
 277 max_capacity=8388608
 278 system=system
 279
 280 [system.cpu.tracer]
 281 type=ExeTracer
 282 eventq_index=0
 283
 284 [system.cpu.workload]
 285 type=LiveProcess
 286 cmd=hello
 287 cwd=
 288 drivers=
 289 egid=100
 290 env=
 291 errout=cerr
 292 euid=100
 293 eventq_index=0
 294 executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
 295 gid=100
 296 input=cin
 297 kvmInSE=false
 298 max_stack_size=67108864
 299 output=cout
 300 pid=100
 301 ppid=99
 302 simpoint=0
 303 system=system
 304 uid=100
 305 useArchPT=false
 306
 307 [system.cpu_clk_domain]
 308 type=SrcClockDomain
 309 clock=500
 310 domain_id=-1
 311 eventq_index=0
 312 init_perf_level=0
 313 voltage_domain=system.voltage_domain
 314
 315 [system.dvfs_handler]
 316 type=DVFSHandler
 317 domains=
 318 enable=false
 319 eventq_index=0
 320 sys_clk_domain=system.clk_domain
 321 transition_latency=100000000
 322
 323 [system.membus]
 324 type=CoherentXBar
 325 clk_domain=system.clk_domain
 326 default_p_state=UNDEFINED
 327 eventq_index=0
 328 forward_latency=4
 329 frontend_latency=3
 330 p_state_clk_gate_bins=20
 331 p_state_clk_gate_max=1000000000000
 332 p_state_clk_gate_min=1000
 333 point_of_coherency=true
 334 power_model=Null
 335 response_latency=2
 336 snoop_filter=Null
 337 snoop_response_latency=4
 338 system=system
 339 use_default_range=false
 340 width=16
 341 master=system.physmem.port
 342 slave=system.system_port system.cpu.l2cache.mem_side
 343
 344 [system.physmem]
 345 type=SimpleMemory
 346 bandwidth=73.000000
 347 clk_domain=system.clk_domain
 348 conf_table_reported=true
 349 default_p_state=UNDEFINED
 350 eventq_index=0
 351 in_addr_map=true
 352 latency=30000
 353 latency_var=0
 354 null=false
 355 p_state_clk_gate_bins=20
 356 p_state_clk_gate_max=1000000000000
 357 p_state_clk_gate_min=1000
 358 power_model=Null
 359 range=0:134217727
 360 port=system.membus.master[0]
 361
 362 [system.voltage_domain]
 363 type=VoltageDomain
 364 eventq_index=0
 365 voltage=1.000000
 366