2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000036 # Number of seconds simulated
4 sim_ticks 36128500 # Number of ticks simulated
5 final_tick 36128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 739000 # Simulator instruction rate (inst/s)
8 host_op_rate 738191 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 4160971439 # Simulator tick rate (ticks/s)
10 host_mem_usage 251728 # Number of bytes of host memory used
11 host_seconds 0.01 # Real time elapsed on the host
12 sim_insts 6403 # Number of instructions simulated
13 sim_ops 6403 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 492464398 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 297604384 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 790068782 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 492464398 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 492464398 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 492464398 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 297604384 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 790068782 # Total bandwidth to/from this memory (bytes/s)
33 system.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
34 system.cpu_clk_domain.clock 500 # Clock period in ticks
35 system.cpu.dtb.fetch_hits 0 # ITB hits
36 system.cpu.dtb.fetch_misses 0 # ITB misses
37 system.cpu.dtb.fetch_acv 0 # ITB acv
38 system.cpu.dtb.fetch_accesses 0 # ITB accesses
39 system.cpu.dtb.read_hits 1185 # DTB read hits
40 system.cpu.dtb.read_misses 7 # DTB read misses
41 system.cpu.dtb.read_acv 0 # DTB read access violations
42 system.cpu.dtb.read_accesses 1192 # DTB read accesses
43 system.cpu.dtb.write_hits 865 # DTB write hits
44 system.cpu.dtb.write_misses 3 # DTB write misses
45 system.cpu.dtb.write_acv 0 # DTB write access violations
46 system.cpu.dtb.write_accesses 868 # DTB write accesses
47 system.cpu.dtb.data_hits 2050 # DTB hits
48 system.cpu.dtb.data_misses 10 # DTB misses
49 system.cpu.dtb.data_acv 0 # DTB access violations
50 system.cpu.dtb.data_accesses 2060 # DTB accesses
51 system.cpu.itb.fetch_hits 6414 # ITB hits
52 system.cpu.itb.fetch_misses 17 # ITB misses
53 system.cpu.itb.fetch_acv 0 # ITB acv
54 system.cpu.itb.fetch_accesses 6431 # ITB accesses
55 system.cpu.itb.read_hits 0 # DTB read hits
56 system.cpu.itb.read_misses 0 # DTB read misses
57 system.cpu.itb.read_acv 0 # DTB read access violations
58 system.cpu.itb.read_accesses 0 # DTB read accesses
59 system.cpu.itb.write_hits 0 # DTB write hits
60 system.cpu.itb.write_misses 0 # DTB write misses
61 system.cpu.itb.write_acv 0 # DTB write access violations
62 system.cpu.itb.write_accesses 0 # DTB write accesses
63 system.cpu.itb.data_hits 0 # DTB hits
64 system.cpu.itb.data_misses 0 # DTB misses
65 system.cpu.itb.data_acv 0 # DTB access violations
66 system.cpu.itb.data_accesses 0 # DTB accesses
67 system.cpu.workload.numSyscalls 17 # Number of system calls
68 system.cpu.pwrStateResidencyTicks::ON 36128500 # Cumulative time (in ticks) in various power states
69 system.cpu.numCycles 72257 # number of cpu cycles simulated
70 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
71 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
72 system.cpu.committedInsts 6403 # Number of instructions committed
73 system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
74 system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
75 system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
76 system.cpu.num_func_calls 251 # number of times a function call or return occured
77 system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
78 system.cpu.num_int_insts 6329 # number of integer instructions
79 system.cpu.num_fp_insts 10 # number of float instructions
80 system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
81 system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
82 system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
83 system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
84 system.cpu.num_mem_refs 2060 # number of memory refs
85 system.cpu.num_load_insts 1192 # Number of load instructions
86 system.cpu.num_store_insts 868 # Number of store instructions
87 system.cpu.num_idle_cycles 0 # Number of idle cycles
88 system.cpu.num_busy_cycles 72257 # Number of busy cycles
89 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
90 system.cpu.idle_fraction 0 # Percentage of idle cycles
91 system.cpu.Branches 1056 # Number of branches fetched
92 system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
93 system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
94 system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
95 system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
96 system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
97 system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
98 system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
99 system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
100 system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction
101 system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
102 system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction
103 system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
104 system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
105 system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
106 system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
107 system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
108 system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
109 system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
110 system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
111 system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
112 system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
113 system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
114 system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
115 system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
116 system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
117 system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
118 system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
119 system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
120 system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
121 system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
122 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
123 system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
124 system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction
125 system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction
126 system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction
127 system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction
128 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
129 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
130 system.cpu.op_class::total 6413 # Class of executed instruction
131 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
132 system.cpu.dcache.tags.replacements 0 # number of replacements
133 system.cpu.dcache.tags.tagsinuse 103.721081 # Cycle average of tags in use
134 system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks.
135 system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
136 system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks.
137 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
138 system.cpu.dcache.tags.occ_blocks::cpu.data 103.721081 # Average occupied blocks per requestor
139 system.cpu.dcache.tags.occ_percent::cpu.data 0.025323 # Average percentage of cache occupancy
140 system.cpu.dcache.tags.occ_percent::total 0.025323 # Average percentage of cache occupancy
141 system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
142 system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
143 system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
144 system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
145 system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses
146 system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses
147 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
148 system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
149 system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
150 system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
151 system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
152 system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
153 system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
154 system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
155 system.cpu.dcache.overall_hits::total 1882 # number of overall hits
156 system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
157 system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
158 system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
159 system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
160 system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
161 system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
162 system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
163 system.cpu.dcache.overall_misses::total 168 # number of overall misses
164 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5985000 # number of ReadReq miss cycles
165 system.cpu.dcache.ReadReq_miss_latency::total 5985000 # number of ReadReq miss cycles
166 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4599000 # number of WriteReq miss cycles
167 system.cpu.dcache.WriteReq_miss_latency::total 4599000 # number of WriteReq miss cycles
168 system.cpu.dcache.demand_miss_latency::cpu.data 10584000 # number of demand (read+write) miss cycles
169 system.cpu.dcache.demand_miss_latency::total 10584000 # number of demand (read+write) miss cycles
170 system.cpu.dcache.overall_miss_latency::cpu.data 10584000 # number of overall miss cycles
171 system.cpu.dcache.overall_miss_latency::total 10584000 # number of overall miss cycles
172 system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
173 system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
174 system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
175 system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
176 system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
177 system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
178 system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
179 system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
180 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
181 system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
182 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
183 system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
184 system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
185 system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
186 system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
187 system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
188 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
189 system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
190 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
191 system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
192 system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
193 system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
194 system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
195 system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
196 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
197 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
198 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
199 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
200 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
201 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
202 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
203 system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
204 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
205 system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
206 system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
207 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
208 system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
209 system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
210 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890000 # number of ReadReq MSHR miss cycles
211 system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890000 # number of ReadReq MSHR miss cycles
212 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles
213 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles
214 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10416000 # number of demand (read+write) MSHR miss cycles
215 system.cpu.dcache.demand_mshr_miss_latency::total 10416000 # number of demand (read+write) MSHR miss cycles
216 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10416000 # number of overall MSHR miss cycles
217 system.cpu.dcache.overall_mshr_miss_latency::total 10416000 # number of overall MSHR miss cycles
218 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
219 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
220 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
221 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
222 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
223 system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
224 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
225 system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
226 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
227 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
228 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
229 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
230 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
231 system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
232 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
233 system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
234 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
235 system.cpu.icache.tags.replacements 0 # number of replacements
236 system.cpu.icache.tags.tagsinuse 127.170991 # Cycle average of tags in use
237 system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
238 system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
239 system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks.
240 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
241 system.cpu.icache.tags.occ_blocks::cpu.inst 127.170991 # Average occupied blocks per requestor
242 system.cpu.icache.tags.occ_percent::cpu.inst 0.062095 # Average percentage of cache occupancy
243 system.cpu.icache.tags.occ_percent::total 0.062095 # Average percentage of cache occupancy
244 system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
245 system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
246 system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
247 system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
248 system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses
249 system.cpu.icache.tags.data_accesses 13107 # Number of data accesses
250 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
251 system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits
252 system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits
253 system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits
254 system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits
255 system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits
256 system.cpu.icache.overall_hits::total 6135 # number of overall hits
257 system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
258 system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
259 system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
260 system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
261 system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
262 system.cpu.icache.overall_misses::total 279 # number of overall misses
263 system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528500 # number of ReadReq miss cycles
264 system.cpu.icache.ReadReq_miss_latency::total 17528500 # number of ReadReq miss cycles
265 system.cpu.icache.demand_miss_latency::cpu.inst 17528500 # number of demand (read+write) miss cycles
266 system.cpu.icache.demand_miss_latency::total 17528500 # number of demand (read+write) miss cycles
267 system.cpu.icache.overall_miss_latency::cpu.inst 17528500 # number of overall miss cycles
268 system.cpu.icache.overall_miss_latency::total 17528500 # number of overall miss cycles
269 system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses)
270 system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses)
271 system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses
272 system.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses
273 system.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses
274 system.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses
275 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses
276 system.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses
277 system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses
278 system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses
279 system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses
280 system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses
281 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875 # average ReadReq miss latency
282 system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875 # average ReadReq miss latency
283 system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency
284 system.cpu.icache.demand_avg_miss_latency::total 62826.164875 # average overall miss latency
285 system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency
286 system.cpu.icache.overall_avg_miss_latency::total 62826.164875 # average overall miss latency
287 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
288 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
289 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
290 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
291 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
292 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
293 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
294 system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
295 system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
296 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
297 system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
298 system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
299 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17249500 # number of ReadReq MSHR miss cycles
300 system.cpu.icache.ReadReq_mshr_miss_latency::total 17249500 # number of ReadReq MSHR miss cycles
301 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17249500 # number of demand (read+write) MSHR miss cycles
302 system.cpu.icache.demand_mshr_miss_latency::total 17249500 # number of demand (read+write) MSHR miss cycles
303 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17249500 # number of overall MSHR miss cycles
304 system.cpu.icache.overall_mshr_miss_latency::total 17249500 # number of overall MSHR miss cycles
305 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses
306 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses
307 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses
308 system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses
309 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses
310 system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses
311 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875 # average ReadReq mshr miss latency
312 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875 # average ReadReq mshr miss latency
313 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency
314 system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency
315 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency
316 system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency
317 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
318 system.cpu.l2cache.tags.replacements 0 # number of replacements
319 system.cpu.l2cache.tags.tagsinuse 230.937880 # Cycle average of tags in use
320 system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
321 system.cpu.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks.
322 system.cpu.l2cache.tags.avg_refs 0.002242 # Average number of references to valid blocks.
323 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
324 system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.167974 # Average occupied blocks per requestor
325 system.cpu.l2cache.tags.occ_blocks::cpu.data 103.769906 # Average occupied blocks per requestor
326 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003881 # Average percentage of cache occupancy
327 system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy
328 system.cpu.l2cache.tags.occ_percent::total 0.007048 # Average percentage of cache occupancy
329 system.cpu.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id
330 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
331 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
332 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013611 # Percentage of cache occupancy per task id
333 system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
334 system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
335 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
336 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
337 system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
338 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
339 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
340 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
341 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
342 system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
343 system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
344 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
345 system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
346 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses
347 system.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses
348 system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
349 system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
350 system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
351 system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
352 system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
353 system.cpu.l2cache.overall_misses::total 446 # number of overall misses
354 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4416500 # number of ReadExReq miss cycles
355 system.cpu.l2cache.ReadExReq_miss_latency::total 4416500 # number of ReadExReq miss cycles
356 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles
357 system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles
358 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5747500 # number of ReadSharedReq miss cycles
359 system.cpu.l2cache.ReadSharedReq_miss_latency::total 5747500 # number of ReadSharedReq miss cycles
360 system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles
361 system.cpu.l2cache.demand_miss_latency::cpu.data 10164000 # number of demand (read+write) miss cycles
362 system.cpu.l2cache.demand_miss_latency::total 26983500 # number of demand (read+write) miss cycles
363 system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles
364 system.cpu.l2cache.overall_miss_latency::cpu.data 10164000 # number of overall miss cycles
365 system.cpu.l2cache.overall_miss_latency::total 26983500 # number of overall miss cycles
366 system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
367 system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
368 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses)
369 system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses)
370 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses)
371 system.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses)
372 system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
373 system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
374 system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
375 system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
376 system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
377 system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
378 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
379 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
380 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses
381 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses
382 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
383 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
384 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
385 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
386 system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
387 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
388 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
389 system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
390 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
391 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
392 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency
393 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency
394 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
395 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
396 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
397 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
398 system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076 # average overall miss latency
399 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
400 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
401 system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076 # average overall miss latency
402 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
403 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
404 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
405 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
406 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
407 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
408 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
409 system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
410 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
411 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
412 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses
413 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses
414 system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
415 system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
416 system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
418 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
419 system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
420 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3686500 # number of ReadExReq MSHR miss cycles
421 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3686500 # number of ReadExReq MSHR miss cycles
422 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles
423 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles
424 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4797500 # number of ReadSharedReq MSHR miss cycles
425 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4797500 # number of ReadSharedReq MSHR miss cycles
426 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles
427 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8484000 # number of demand (read+write) MSHR miss cycles
428 system.cpu.l2cache.demand_mshr_miss_latency::total 22523500 # number of demand (read+write) MSHR miss cycles
429 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles
430 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8484000 # number of overall MSHR miss cycles
431 system.cpu.l2cache.overall_mshr_miss_latency::total 22523500 # number of overall MSHR miss cycles
432 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
433 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
434 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses
435 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses
436 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
437 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
438 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
439 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
440 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
441 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
442 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
443 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
444 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
445 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
446 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency
447 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency
448 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
449 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
450 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
451 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
452 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency
453 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
454 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
455 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency
456 system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
457 system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
458 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
459 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
460 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
461 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
462 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
463 system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
464 system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
465 system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
466 system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution
467 system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution
468 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
469 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
470 system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
471 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
472 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
473 system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
474 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
475 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
476 system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram
477 system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
482 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
483 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
484 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
485 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
486 system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
487 system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
488 system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
489 system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
490 system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
491 system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
492 system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
493 system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter.
494 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
495 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
496 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
497 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
498 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
499 system.membus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
500 system.membus.trans_dist::ReadResp 373 # Transaction distribution
501 system.membus.trans_dist::ReadExReq 73 # Transaction distribution
502 system.membus.trans_dist::ReadExResp 73 # Transaction distribution
503 system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution
504 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
505 system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
506 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
507 system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
508 system.membus.snoops 0 # Total snoops (count)
509 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
510 system.membus.snoop_fanout::samples 446 # Request fanout histogram
511 system.membus.snoop_fanout::mean 0 # Request fanout histogram
512 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
513 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
514 system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
515 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
516 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
517 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
518 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
519 system.membus.snoop_fanout::total 446 # Request fanout histogram
520 system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
521 system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
522 system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
523 system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
525 ---------- End Simulation Statistics ----------
projects / gem5.git / blob