2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000033 # Number of seconds simulated
4 sim_ticks 32544000 # Number of ticks simulated
5 final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 19861 # Simulator instruction rate (inst/s)
8 host_op_rate 19860 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 101141711 # Simulator tick rate (ticks/s)
10 host_mem_usage 224276 # Number of bytes of host memory used
11 host_seconds 0.32 # Real time elapsed on the host
12 sim_insts 6390 # Number of instructions simulated
13 sim_ops 6390 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
30 system.membus.throughput 877089479 # Throughput (bytes/s)
31 system.membus.trans_dist::ReadReq 373 # Transaction distribution
32 system.membus.trans_dist::ReadResp 373 # Transaction distribution
33 system.membus.trans_dist::ReadExReq 73 # Transaction distribution
34 system.membus.trans_dist::ReadExResp 73 # Transaction distribution
35 system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
36 system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
37 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
38 system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
39 system.membus.data_through_bus 28544 # Total data (bytes)
40 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41 system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
42 system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
43 system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
44 system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
45 system.cpu.dtb.fetch_hits 0 # ITB hits
46 system.cpu.dtb.fetch_misses 0 # ITB misses
47 system.cpu.dtb.fetch_acv 0 # ITB acv
48 system.cpu.dtb.fetch_accesses 0 # ITB accesses
49 system.cpu.dtb.read_hits 1183 # DTB read hits
50 system.cpu.dtb.read_misses 7 # DTB read misses
51 system.cpu.dtb.read_acv 0 # DTB read access violations
52 system.cpu.dtb.read_accesses 1190 # DTB read accesses
53 system.cpu.dtb.write_hits 865 # DTB write hits
54 system.cpu.dtb.write_misses 3 # DTB write misses
55 system.cpu.dtb.write_acv 0 # DTB write access violations
56 system.cpu.dtb.write_accesses 868 # DTB write accesses
57 system.cpu.dtb.data_hits 2048 # DTB hits
58 system.cpu.dtb.data_misses 10 # DTB misses
59 system.cpu.dtb.data_acv 0 # DTB access violations
60 system.cpu.dtb.data_accesses 2058 # DTB accesses
61 system.cpu.itb.fetch_hits 6401 # ITB hits
62 system.cpu.itb.fetch_misses 17 # ITB misses
63 system.cpu.itb.fetch_acv 0 # ITB acv
64 system.cpu.itb.fetch_accesses 6418 # ITB accesses
65 system.cpu.itb.read_hits 0 # DTB read hits
66 system.cpu.itb.read_misses 0 # DTB read misses
67 system.cpu.itb.read_acv 0 # DTB read access violations
68 system.cpu.itb.read_accesses 0 # DTB read accesses
69 system.cpu.itb.write_hits 0 # DTB write hits
70 system.cpu.itb.write_misses 0 # DTB write misses
71 system.cpu.itb.write_acv 0 # DTB write access violations
72 system.cpu.itb.write_accesses 0 # DTB write accesses
73 system.cpu.itb.data_hits 0 # DTB hits
74 system.cpu.itb.data_misses 0 # DTB misses
75 system.cpu.itb.data_acv 0 # DTB access violations
76 system.cpu.itb.data_accesses 0 # DTB accesses
77 system.cpu.workload.num_syscalls 17 # Number of system calls
78 system.cpu.numCycles 65088 # number of cpu cycles simulated
79 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
80 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
81 system.cpu.committedInsts 6390 # Number of instructions committed
82 system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
83 system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
84 system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
85 system.cpu.num_func_calls 251 # number of times a function call or return occured
86 system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
87 system.cpu.num_int_insts 6317 # number of integer instructions
88 system.cpu.num_fp_insts 10 # number of float instructions
89 system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
90 system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
91 system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
92 system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
93 system.cpu.num_mem_refs 2058 # number of memory refs
94 system.cpu.num_load_insts 1190 # Number of load instructions
95 system.cpu.num_store_insts 868 # Number of store instructions
96 system.cpu.num_idle_cycles 0 # Number of idle cycles
97 system.cpu.num_busy_cycles 65088 # Number of busy cycles
98 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
99 system.cpu.idle_fraction 0 # Percentage of idle cycles
100 system.cpu.icache.replacements 0 # number of replacements
101 system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use
102 system.cpu.icache.total_refs 6122 # Total number of references to valid blocks.
103 system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
104 system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks.
105 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
106 system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
107 system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
108 system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy
109 system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
110 system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
111 system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
112 system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
113 system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
114 system.cpu.icache.overall_hits::total 6122 # number of overall hits
115 system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
116 system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
117 system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
118 system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
119 system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
120 system.cpu.icache.overall_misses::total 279 # number of overall misses
121 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles
122 system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles
123 system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles
124 system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles
125 system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles
126 system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles
127 system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
128 system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
129 system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
130 system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
131 system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
132 system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
133 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
134 system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
135 system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
136 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
137 system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
138 system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
139 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency
140 system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency
141 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
142 system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency
143 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
144 system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency
145 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
146 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
147 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
148 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
149 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
150 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
151 system.cpu.icache.fast_writes 0 # number of fast writes performed
152 system.cpu.icache.cache_copies 0 # number of cache copies performed
153 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
154 system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
155 system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
156 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
157 system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
158 system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
159 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
160 system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
161 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
162 system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
163 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
164 system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
165 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
166 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
167 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
168 system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
169 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
170 system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
171 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
172 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
173 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
174 system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
175 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
176 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
177 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
178 system.cpu.l2cache.replacements 0 # number of replacements
179 system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use
180 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
181 system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
182 system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
183 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
184 system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
185 system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
186 system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
187 system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
188 system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy
189 system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
190 system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
191 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
192 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
193 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
194 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
195 system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
196 system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
197 system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
198 system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
199 system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
200 system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
201 system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
202 system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
203 system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
204 system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
205 system.cpu.l2cache.overall_misses::total 446 # number of overall misses
206 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
207 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
208 system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
209 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
210 system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
211 system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
212 system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
213 system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
214 system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
215 system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
216 system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
217 system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
218 system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
219 system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
220 system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
221 system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
222 system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
223 system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
224 system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
225 system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
226 system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
227 system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
228 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
229 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
230 system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
231 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
232 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
233 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
234 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
235 system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
236 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
237 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
238 system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
239 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
240 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
241 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
242 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
243 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
244 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
245 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
246 system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
247 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
248 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
249 system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
250 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
251 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
252 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
253 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
254 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
255 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
256 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
257 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
258 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
259 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
260 system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
261 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
262 system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
263 system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
264 system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
265 system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
266 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
267 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
268 system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
269 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
270 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
271 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
272 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
273 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
274 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
275 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
276 system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
277 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
278 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
279 system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
280 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
281 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
282 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
283 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
284 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
285 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
286 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
287 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
288 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
289 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
290 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
291 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
292 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
293 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
294 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
295 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
296 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
297 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
298 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
299 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
300 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
301 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
302 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
303 system.cpu.dcache.replacements 0 # number of replacements
304 system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
305 system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
306 system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
307 system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
308 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
309 system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
310 system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
311 system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
312 system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
313 system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
314 system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
315 system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
316 system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
317 system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
318 system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
319 system.cpu.dcache.overall_hits::total 1880 # number of overall hits
320 system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
321 system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
322 system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
323 system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
324 system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
325 system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
326 system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
327 system.cpu.dcache.overall_misses::total 168 # number of overall misses
328 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
329 system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
330 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
331 system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
332 system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
333 system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
334 system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
335 system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
336 system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
337 system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
338 system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
339 system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
340 system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
341 system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
342 system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
343 system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
344 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
345 system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
346 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
347 system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
348 system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
349 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
350 system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
351 system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
352 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
353 system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
354 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
355 system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
356 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
357 system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
358 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
359 system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
360 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
361 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
362 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
363 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
364 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
365 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
366 system.cpu.dcache.fast_writes 0 # number of fast writes performed
367 system.cpu.dcache.cache_copies 0 # number of cache copies performed
368 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
369 system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
370 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
371 system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
372 system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
373 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
374 system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
375 system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
376 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
377 system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
378 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
379 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
380 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
381 system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
382 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
383 system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
384 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
385 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
386 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
387 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
388 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
389 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
390 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
391 system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
392 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
393 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
394 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
395 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
396 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
397 system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
398 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
399 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
400 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
401 system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
402 system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
403 system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
404 system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
405 system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
406 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes)
407 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
408 system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes)
409 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes)
410 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
411 system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes)
412 system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
413 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
414 system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
415 system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
416 system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
417 system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
418 system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
419 system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
421 ---------- End Simulation Statistics ----------
projects / gem5.git / blob