2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000036 # Number of seconds simulated
4 sim_ticks 35667500 # Number of ticks simulated
5 final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 102057 # Simulator instruction rate (inst/s)
8 host_op_rate 102013 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 569174066 # Simulator tick rate (ticks/s)
10 host_mem_usage 230332 # Number of bytes of host memory used
11 host_seconds 0.06 # Real time elapsed on the host
12 sim_insts 6390 # Number of instructions simulated
13 sim_ops 6390 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.dtb.fetch_hits 0 # ITB hits
34 system.cpu.dtb.fetch_misses 0 # ITB misses
35 system.cpu.dtb.fetch_acv 0 # ITB acv
36 system.cpu.dtb.fetch_accesses 0 # ITB accesses
37 system.cpu.dtb.read_hits 1183 # DTB read hits
38 system.cpu.dtb.read_misses 7 # DTB read misses
39 system.cpu.dtb.read_acv 0 # DTB read access violations
40 system.cpu.dtb.read_accesses 1190 # DTB read accesses
41 system.cpu.dtb.write_hits 865 # DTB write hits
42 system.cpu.dtb.write_misses 3 # DTB write misses
43 system.cpu.dtb.write_acv 0 # DTB write access violations
44 system.cpu.dtb.write_accesses 868 # DTB write accesses
45 system.cpu.dtb.data_hits 2048 # DTB hits
46 system.cpu.dtb.data_misses 10 # DTB misses
47 system.cpu.dtb.data_acv 0 # DTB access violations
48 system.cpu.dtb.data_accesses 2058 # DTB accesses
49 system.cpu.itb.fetch_hits 6401 # ITB hits
50 system.cpu.itb.fetch_misses 17 # ITB misses
51 system.cpu.itb.fetch_acv 0 # ITB acv
52 system.cpu.itb.fetch_accesses 6418 # ITB accesses
53 system.cpu.itb.read_hits 0 # DTB read hits
54 system.cpu.itb.read_misses 0 # DTB read misses
55 system.cpu.itb.read_acv 0 # DTB read access violations
56 system.cpu.itb.read_accesses 0 # DTB read accesses
57 system.cpu.itb.write_hits 0 # DTB write hits
58 system.cpu.itb.write_misses 0 # DTB write misses
59 system.cpu.itb.write_acv 0 # DTB write access violations
60 system.cpu.itb.write_accesses 0 # DTB write accesses
61 system.cpu.itb.data_hits 0 # DTB hits
62 system.cpu.itb.data_misses 0 # DTB misses
63 system.cpu.itb.data_acv 0 # DTB access violations
64 system.cpu.itb.data_accesses 0 # DTB accesses
65 system.cpu.workload.num_syscalls 17 # Number of system calls
66 system.cpu.numCycles 71335 # number of cpu cycles simulated
67 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69 system.cpu.committedInsts 6390 # Number of instructions committed
70 system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
71 system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
72 system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
73 system.cpu.num_func_calls 251 # number of times a function call or return occured
74 system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
75 system.cpu.num_int_insts 6317 # number of integer instructions
76 system.cpu.num_fp_insts 10 # number of float instructions
77 system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
78 system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
79 system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
80 system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
81 system.cpu.num_mem_refs 2058 # number of memory refs
82 system.cpu.num_load_insts 1190 # Number of load instructions
83 system.cpu.num_store_insts 868 # Number of store instructions
84 system.cpu.num_idle_cycles 0 # Number of idle cycles
85 system.cpu.num_busy_cycles 71335 # Number of busy cycles
86 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
87 system.cpu.idle_fraction 0 # Percentage of idle cycles
88 system.cpu.Branches 1050 # Number of branches fetched
89 system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
90 system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
91 system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
92 system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
93 system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
94 system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
95 system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
96 system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
97 system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
98 system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
99 system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
100 system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
101 system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
102 system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
103 system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
104 system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
105 system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
106 system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
107 system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
108 system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
109 system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
110 system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
111 system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
112 system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
113 system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
114 system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
115 system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
116 system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
117 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
118 system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
119 system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
120 system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
121 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
122 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
123 system.cpu.op_class::total 6400 # Class of executed instruction
124 system.cpu.dcache.tags.replacements 0 # number of replacements
125 system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use
126 system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
127 system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
128 system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
129 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
130 system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor
131 system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy
132 system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy
133 system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
134 system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
135 system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
136 system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
137 system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
138 system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
139 system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
140 system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
141 system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
142 system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
143 system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
144 system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
145 system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
146 system.cpu.dcache.overall_hits::total 1880 # number of overall hits
147 system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
148 system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
149 system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
150 system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
151 system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
152 system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
153 system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
154 system.cpu.dcache.overall_misses::total 168 # number of overall misses
155 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles
156 system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles
157 system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles
158 system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles
159 system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles
160 system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles
161 system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles
162 system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles
163 system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
164 system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
165 system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
166 system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
167 system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
168 system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
169 system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
170 system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
171 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
172 system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
173 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
174 system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
175 system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
176 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
177 system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
178 system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
179 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
180 system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
181 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
182 system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
183 system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
184 system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
185 system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
186 system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
187 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
188 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
189 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
190 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
191 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
192 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
193 system.cpu.dcache.fast_writes 0 # number of fast writes performed
194 system.cpu.dcache.cache_copies 0 # number of cache copies performed
195 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
196 system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
197 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
198 system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
199 system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
200 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
201 system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
202 system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
203 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles
204 system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles
205 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles
206 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles
207 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles
208 system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles
209 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles
210 system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles
211 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
212 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
213 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
214 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
215 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
216 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
217 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
218 system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
219 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
220 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
221 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
222 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
223 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
224 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
225 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
226 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
227 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
228 system.cpu.icache.tags.replacements 0 # number of replacements
229 system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use
230 system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
231 system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
232 system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
233 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
234 system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor
235 system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy
236 system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy
237 system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
238 system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
239 system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
240 system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
241 system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
242 system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
243 system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
244 system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
245 system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
246 system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
247 system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
248 system.cpu.icache.overall_hits::total 6122 # number of overall hits
249 system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
250 system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
251 system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
252 system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
253 system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
254 system.cpu.icache.overall_misses::total 279 # number of overall misses
255 system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles
256 system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles
257 system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles
258 system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles
259 system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles
260 system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles
261 system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
262 system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
263 system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
264 system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
265 system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
266 system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
267 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
268 system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
269 system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
270 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
271 system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
272 system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
273 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency
274 system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency
275 system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
276 system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency
277 system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
278 system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency
279 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
280 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
281 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
282 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
283 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
284 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
285 system.cpu.icache.fast_writes 0 # number of fast writes performed
286 system.cpu.icache.cache_copies 0 # number of cache copies performed
287 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
288 system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
289 system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
290 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
291 system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
292 system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
293 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles
294 system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles
295 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles
296 system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles
297 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles
298 system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles
299 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
300 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
301 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
302 system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
303 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
304 system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
305 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency
306 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency
307 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
308 system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
309 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
310 system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
311 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
312 system.cpu.l2cache.tags.replacements 0 # number of replacements
313 system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use
314 system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
315 system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
316 system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
317 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
318 system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor
319 system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor
320 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy
321 system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy
322 system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy
323 system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
324 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
325 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
326 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
327 system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
328 system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
329 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
330 system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
331 system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
332 system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
333 system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
334 system.cpu.l2cache.overall_hits::total 1 # number of overall hits
335 system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
336 system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
337 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
338 system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
339 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses
340 system.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses
341 system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
342 system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
343 system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
344 system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
345 system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
346 system.cpu.l2cache.overall_misses::total 446 # number of overall misses
347 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles
348 system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles
349 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
350 system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
351 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles
352 system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles
353 system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
354 system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles
355 system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles
356 system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
357 system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles
358 system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles
359 system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
360 system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
361 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses)
362 system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses)
363 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses)
364 system.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses)
365 system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
366 system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
367 system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
368 system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
369 system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
370 system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
371 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
372 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
373 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses
374 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses
375 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
376 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
377 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
378 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
379 system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
380 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
381 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
382 system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
383 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
384 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
385 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
386 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
387 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
388 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
389 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
390 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
391 system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency
392 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
393 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
394 system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency
395 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
396 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
397 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
398 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
399 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
400 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
401 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
402 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
403 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
404 system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
405 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
406 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
407 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses
408 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses
409 system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
410 system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
411 system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
412 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
413 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
414 system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
415 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles
416 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles
417 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
418 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
419 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles
420 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles
421 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
422 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles
423 system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles
424 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
425 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles
426 system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles
427 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
428 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
429 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses
430 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses
431 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
432 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
433 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
434 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
435 system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
436 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
437 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
438 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
439 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
440 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
441 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
442 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
443 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
444 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
445 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
446 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
447 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
448 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
449 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
450 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
451 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
452 system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
453 system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
454 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
455 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
456 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
457 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
458 system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
459 system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
460 system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
461 system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution
462 system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution
463 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
464 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
465 system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
466 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
467 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
468 system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
469 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
470 system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram
471 system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram
472 system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram
473 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
474 system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram
475 system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
476 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
477 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
481 system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
482 system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
483 system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
484 system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
485 system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
486 system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
487 system.membus.trans_dist::ReadResp 373 # Transaction distribution
488 system.membus.trans_dist::ReadExReq 73 # Transaction distribution
489 system.membus.trans_dist::ReadExResp 73 # Transaction distribution
490 system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution
491 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
492 system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
493 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
494 system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
495 system.membus.snoops 0 # Total snoops (count)
496 system.membus.snoop_fanout::samples 446 # Request fanout histogram
497 system.membus.snoop_fanout::mean 0 # Request fanout histogram
498 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
499 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
500 system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
501 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
502 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
503 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
504 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
505 system.membus.snoop_fanout::total 446 # Request fanout histogram
506 system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
507 system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
508 system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
509 system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
511 ---------- End Simulation Statistics ----------
projects / gem5.git / blob