2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000020 # Number of seconds simulated
4 sim_ticks 20075000 # Number of ticks simulated
5 final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 11823 # Simulator instruction rate (inst/s)
8 host_op_rate 11822 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 91797329 # Simulator tick rate (ticks/s)
10 host_mem_usage 230008 # Number of bytes of host memory used
11 host_seconds 0.22 # Real time elapsed on the host
12 sim_insts 2585 # Number of instructions simulated
13 sim_ops 2585 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 14272 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 19712 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 308 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 19712 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 19712 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 0 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 1 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 3 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 24 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 21 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 0 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 27 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 47 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 68 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 2 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 15 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 14 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 18 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 52 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 15 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 1 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 19987000 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 308 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189 system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::mean 430.829268 # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::gmean 282.802413 # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::stdev 330.088769 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::512-639 6 14.63% 68.29% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::640-767 4 9.76% 78.05% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
203 system.physmem.totQLat 1568250 # Total ticks spent queuing
204 system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM
205 system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
206 system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst
207 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208 system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst
209 system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s
210 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211 system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s
212 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214 system.physmem.busUtil 7.67 # Data bus utilization in percentage
215 system.physmem.busUtilRead 7.67 # Data bus utilization in percentage for reads
216 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217 system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
218 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219 system.physmem.readRowHits 258 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223 system.physmem.avgGap 64892.86 # Average gap between requests
224 system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined
225 system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
226 system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
227 system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ)
228 system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229 system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
230 system.physmem_0.actBackEnergy 10605420 # Energy for active background per rank (pJ)
231 system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ)
232 system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ)
233 system.physmem_0.averagePower 803.889152 # Core power per rank (mW)
234 system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states
235 system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
236 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237 system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states
238 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239 system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
240 system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
241 system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ)
242 system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243 system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
244 system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ)
245 system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ)
246 system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ)
247 system.physmem_1.averagePower 839.916627 # Core power per rank (mW)
248 system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states
249 system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
250 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251 system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states
252 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253 system.cpu.branchPred.lookups 787 # Number of BP lookups
254 system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted
255 system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect
256 system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups
257 system.cpu.branchPred.BTBHits 60 # Number of BTB hits
258 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259 system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage
260 system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target.
261 system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
262 system.cpu_clk_domain.clock 500 # Clock period in ticks
263 system.cpu.dtb.fetch_hits 0 # ITB hits
264 system.cpu.dtb.fetch_misses 0 # ITB misses
265 system.cpu.dtb.fetch_acv 0 # ITB acv
266 system.cpu.dtb.fetch_accesses 0 # ITB accesses
267 system.cpu.dtb.read_hits 506 # DTB read hits
268 system.cpu.dtb.read_misses 7 # DTB read misses
269 system.cpu.dtb.read_acv 1 # DTB read access violations
270 system.cpu.dtb.read_accesses 513 # DTB read accesses
271 system.cpu.dtb.write_hits 307 # DTB write hits
272 system.cpu.dtb.write_misses 6 # DTB write misses
273 system.cpu.dtb.write_acv 0 # DTB write access violations
274 system.cpu.dtb.write_accesses 313 # DTB write accesses
275 system.cpu.dtb.data_hits 813 # DTB hits
276 system.cpu.dtb.data_misses 13 # DTB misses
277 system.cpu.dtb.data_acv 1 # DTB access violations
278 system.cpu.dtb.data_accesses 826 # DTB accesses
279 system.cpu.itb.fetch_hits 965 # ITB hits
280 system.cpu.itb.fetch_misses 13 # ITB misses
281 system.cpu.itb.fetch_acv 0 # ITB acv
282 system.cpu.itb.fetch_accesses 978 # ITB accesses
283 system.cpu.itb.read_hits 0 # DTB read hits
284 system.cpu.itb.read_misses 0 # DTB read misses
285 system.cpu.itb.read_acv 0 # DTB read access violations
286 system.cpu.itb.read_accesses 0 # DTB read accesses
287 system.cpu.itb.write_hits 0 # DTB write hits
288 system.cpu.itb.write_misses 0 # DTB write misses
289 system.cpu.itb.write_acv 0 # DTB write access violations
290 system.cpu.itb.write_accesses 0 # DTB write accesses
291 system.cpu.itb.data_hits 0 # DTB hits
292 system.cpu.itb.data_misses 0 # DTB misses
293 system.cpu.itb.data_acv 0 # DTB access violations
294 system.cpu.itb.data_accesses 0 # DTB accesses
295 system.cpu.workload.num_syscalls 4 # Number of system calls
296 system.cpu.numCycles 40150 # number of cpu cycles simulated
297 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
298 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
299 system.cpu.committedInsts 2585 # Number of instructions committed
300 system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
301 system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit
302 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
303 system.cpu.cpi 15.531915 # CPI: cycles per instruction
304 system.cpu.ipc 0.064384 # IPC: instructions per cycle
305 system.cpu.tickCycles 5369 # Number of cycles that the object actually ticked
306 system.cpu.idleCycles 34781 # Total number of cycles that the object has spent stopped
307 system.cpu.dcache.tags.replacements 0 # number of replacements
308 system.cpu.dcache.tags.tagsinuse 48.313800 # Cycle average of tags in use
309 system.cpu.dcache.tags.total_refs 689 # Total number of references to valid blocks.
310 system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
311 system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks.
312 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
313 system.cpu.dcache.tags.occ_blocks::cpu.data 48.313800 # Average occupied blocks per requestor
314 system.cpu.dcache.tags.occ_percent::cpu.data 0.011795 # Average percentage of cache occupancy
315 system.cpu.dcache.tags.occ_percent::total 0.011795 # Average percentage of cache occupancy
316 system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
317 system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
318 system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
319 system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
320 system.cpu.dcache.tags.tag_accesses 1671 # Number of tag accesses
321 system.cpu.dcache.tags.data_accesses 1671 # Number of data accesses
322 system.cpu.dcache.ReadReq_hits::cpu.data 438 # number of ReadReq hits
323 system.cpu.dcache.ReadReq_hits::total 438 # number of ReadReq hits
324 system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
325 system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
326 system.cpu.dcache.demand_hits::cpu.data 689 # number of demand (read+write) hits
327 system.cpu.dcache.demand_hits::total 689 # number of demand (read+write) hits
328 system.cpu.dcache.overall_hits::cpu.data 689 # number of overall hits
329 system.cpu.dcache.overall_hits::total 689 # number of overall hits
330 system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
331 system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
332 system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
333 system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
334 system.cpu.dcache.demand_misses::cpu.data 104 # number of demand (read+write) misses
335 system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
336 system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses
337 system.cpu.dcache.overall_misses::total 104 # number of overall misses
338 system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723000 # number of ReadReq miss cycles
339 system.cpu.dcache.ReadReq_miss_latency::total 4723000 # number of ReadReq miss cycles
340 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258500 # number of WriteReq miss cycles
341 system.cpu.dcache.WriteReq_miss_latency::total 3258500 # number of WriteReq miss cycles
342 system.cpu.dcache.demand_miss_latency::cpu.data 7981500 # number of demand (read+write) miss cycles
343 system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles
344 system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles
345 system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles
346 system.cpu.dcache.ReadReq_accesses::cpu.data 499 # number of ReadReq accesses(hits+misses)
347 system.cpu.dcache.ReadReq_accesses::total 499 # number of ReadReq accesses(hits+misses)
348 system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
349 system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
350 system.cpu.dcache.demand_accesses::cpu.data 793 # number of demand (read+write) accesses
351 system.cpu.dcache.demand_accesses::total 793 # number of demand (read+write) accesses
352 system.cpu.dcache.overall_accesses::cpu.data 793 # number of overall (read+write) accesses
353 system.cpu.dcache.overall_accesses::total 793 # number of overall (read+write) accesses
354 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.122244 # miss rate for ReadReq accesses
355 system.cpu.dcache.ReadReq_miss_rate::total 0.122244 # miss rate for ReadReq accesses
356 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses
357 system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses
358 system.cpu.dcache.demand_miss_rate::cpu.data 0.131148 # miss rate for demand accesses
359 system.cpu.dcache.demand_miss_rate::total 0.131148 # miss rate for demand accesses
360 system.cpu.dcache.overall_miss_rate::cpu.data 0.131148 # miss rate for overall accesses
361 system.cpu.dcache.overall_miss_rate::total 0.131148 # miss rate for overall accesses
362 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency
363 system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency
364 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency
365 system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767 # average WriteReq miss latency
366 system.cpu.dcache.demand_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency
367 system.cpu.dcache.demand_avg_miss_latency::total 76745.192308 # average overall miss latency
368 system.cpu.dcache.overall_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency
369 system.cpu.dcache.overall_avg_miss_latency::total 76745.192308 # average overall miss latency
370 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
371 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
372 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
373 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
374 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
375 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
376 system.cpu.dcache.fast_writes 0 # number of fast writes performed
377 system.cpu.dcache.cache_copies 0 # number of cache copies performed
378 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits
379 system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
380 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16 # number of WriteReq MSHR hits
381 system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits
382 system.cpu.dcache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits
383 system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
384 system.cpu.dcache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits
385 system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits
386 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses
387 system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses
388 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
389 system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
390 system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
391 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
392 system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
393 system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
394 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442000 # number of ReadReq MSHR miss cycles
395 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442000 # number of ReadReq MSHR miss cycles
396 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles
397 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles
398 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 # number of demand (read+write) MSHR miss cycles
399 system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles
400 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles
401 system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles
402 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116232 # mshr miss rate for ReadReq accesses
403 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116232 # mshr miss rate for ReadReq accesses
404 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
405 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
406 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for demand accesses
407 system.cpu.dcache.demand_mshr_miss_rate::total 0.107188 # mshr miss rate for demand accesses
408 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for overall accesses
409 system.cpu.dcache.overall_mshr_miss_rate::total 0.107188 # mshr miss rate for overall accesses
410 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency
411 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency
412 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency
413 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency
414 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency
415 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency
416 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency
417 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency
418 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
419 system.cpu.icache.tags.replacements 0 # number of replacements
420 system.cpu.icache.tags.tagsinuse 117.873256 # Cycle average of tags in use
421 system.cpu.icache.tags.total_refs 742 # Total number of references to valid blocks.
422 system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
423 system.cpu.icache.tags.avg_refs 3.327354 # Average number of references to valid blocks.
424 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
425 system.cpu.icache.tags.occ_blocks::cpu.inst 117.873256 # Average occupied blocks per requestor
426 system.cpu.icache.tags.occ_percent::cpu.inst 0.057555 # Average percentage of cache occupancy
427 system.cpu.icache.tags.occ_percent::total 0.057555 # Average percentage of cache occupancy
428 system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
429 system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
430 system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
431 system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
432 system.cpu.icache.tags.tag_accesses 2153 # Number of tag accesses
433 system.cpu.icache.tags.data_accesses 2153 # Number of data accesses
434 system.cpu.icache.ReadReq_hits::cpu.inst 742 # number of ReadReq hits
435 system.cpu.icache.ReadReq_hits::total 742 # number of ReadReq hits
436 system.cpu.icache.demand_hits::cpu.inst 742 # number of demand (read+write) hits
437 system.cpu.icache.demand_hits::total 742 # number of demand (read+write) hits
438 system.cpu.icache.overall_hits::cpu.inst 742 # number of overall hits
439 system.cpu.icache.overall_hits::total 742 # number of overall hits
440 system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
441 system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
442 system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
443 system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
444 system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
445 system.cpu.icache.overall_misses::total 223 # number of overall misses
446 system.cpu.icache.ReadReq_miss_latency::cpu.inst 16979500 # number of ReadReq miss cycles
447 system.cpu.icache.ReadReq_miss_latency::total 16979500 # number of ReadReq miss cycles
448 system.cpu.icache.demand_miss_latency::cpu.inst 16979500 # number of demand (read+write) miss cycles
449 system.cpu.icache.demand_miss_latency::total 16979500 # number of demand (read+write) miss cycles
450 system.cpu.icache.overall_miss_latency::cpu.inst 16979500 # number of overall miss cycles
451 system.cpu.icache.overall_miss_latency::total 16979500 # number of overall miss cycles
452 system.cpu.icache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses)
453 system.cpu.icache.ReadReq_accesses::total 965 # number of ReadReq accesses(hits+misses)
454 system.cpu.icache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses
455 system.cpu.icache.demand_accesses::total 965 # number of demand (read+write) accesses
456 system.cpu.icache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses
457 system.cpu.icache.overall_accesses::total 965 # number of overall (read+write) accesses
458 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231088 # miss rate for ReadReq accesses
459 system.cpu.icache.ReadReq_miss_rate::total 0.231088 # miss rate for ReadReq accesses
460 system.cpu.icache.demand_miss_rate::cpu.inst 0.231088 # miss rate for demand accesses
461 system.cpu.icache.demand_miss_rate::total 0.231088 # miss rate for demand accesses
462 system.cpu.icache.overall_miss_rate::cpu.inst 0.231088 # miss rate for overall accesses
463 system.cpu.icache.overall_miss_rate::total 0.231088 # miss rate for overall accesses
464 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76141.255605 # average ReadReq miss latency
465 system.cpu.icache.ReadReq_avg_miss_latency::total 76141.255605 # average ReadReq miss latency
466 system.cpu.icache.demand_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency
467 system.cpu.icache.demand_avg_miss_latency::total 76141.255605 # average overall miss latency
468 system.cpu.icache.overall_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency
469 system.cpu.icache.overall_avg_miss_latency::total 76141.255605 # average overall miss latency
470 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
471 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
472 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
473 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
474 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
475 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
476 system.cpu.icache.fast_writes 0 # number of fast writes performed
477 system.cpu.icache.cache_copies 0 # number of cache copies performed
478 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses
479 system.cpu.icache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
480 system.cpu.icache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
481 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
482 system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
483 system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
484 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16756500 # number of ReadReq MSHR miss cycles
485 system.cpu.icache.ReadReq_mshr_miss_latency::total 16756500 # number of ReadReq MSHR miss cycles
486 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16756500 # number of demand (read+write) MSHR miss cycles
487 system.cpu.icache.demand_mshr_miss_latency::total 16756500 # number of demand (read+write) MSHR miss cycles
488 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16756500 # number of overall MSHR miss cycles
489 system.cpu.icache.overall_mshr_miss_latency::total 16756500 # number of overall MSHR miss cycles
490 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for ReadReq accesses
491 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231088 # mshr miss rate for ReadReq accesses
492 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for demand accesses
493 system.cpu.icache.demand_mshr_miss_rate::total 0.231088 # mshr miss rate for demand accesses
494 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for overall accesses
495 system.cpu.icache.overall_mshr_miss_rate::total 0.231088 # mshr miss rate for overall accesses
496 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75141.255605 # average ReadReq mshr miss latency
497 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75141.255605 # average ReadReq mshr miss latency
498 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency
499 system.cpu.icache.demand_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency
500 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency
501 system.cpu.icache.overall_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency
502 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
503 system.cpu.l2cache.tags.replacements 0 # number of replacements
504 system.cpu.l2cache.tags.tagsinuse 145.780629 # Cycle average of tags in use
505 system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
506 system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
507 system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
508 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
509 system.cpu.l2cache.tags.occ_blocks::cpu.inst 117.989893 # Average occupied blocks per requestor
510 system.cpu.l2cache.tags.occ_blocks::cpu.data 27.790736 # Average occupied blocks per requestor
511 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003601 # Average percentage of cache occupancy
512 system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy
513 system.cpu.l2cache.tags.occ_percent::total 0.004449 # Average percentage of cache occupancy
514 system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
515 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
516 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
517 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id
518 system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses
519 system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses
520 system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
521 system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
522 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 223 # number of ReadCleanReq misses
523 system.cpu.l2cache.ReadCleanReq_misses::total 223 # number of ReadCleanReq misses
524 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses
525 system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses
526 system.cpu.l2cache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
527 system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
528 system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses
529 system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses
530 system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
531 system.cpu.l2cache.overall_misses::total 308 # number of overall misses
532 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles
533 system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles
534 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16422000 # number of ReadCleanReq miss cycles
535 system.cpu.l2cache.ReadCleanReq_miss_latency::total 16422000 # number of ReadCleanReq miss cycles
536 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles
537 system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles
538 system.cpu.l2cache.demand_miss_latency::cpu.inst 16422000 # number of demand (read+write) miss cycles
539 system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles
540 system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles
541 system.cpu.l2cache.overall_miss_latency::cpu.inst 16422000 # number of overall miss cycles
542 system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles
543 system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles
544 system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
545 system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
546 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses)
547 system.cpu.l2cache.ReadCleanReq_accesses::total 223 # number of ReadCleanReq accesses(hits+misses)
548 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses)
549 system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses)
550 system.cpu.l2cache.demand_accesses::cpu.inst 223 # number of demand (read+write) accesses
551 system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
552 system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses
553 system.cpu.l2cache.overall_accesses::cpu.inst 223 # number of overall (read+write) accesses
554 system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
555 system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses
556 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
557 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
558 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
559 system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
560 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
561 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
562 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
563 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
564 system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
565 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
566 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
567 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
568 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency
569 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency
570 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605 # average ReadCleanReq miss latency
571 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605 # average ReadCleanReq miss latency
572 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency
573 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency
574 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency
575 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency
576 system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623 # average overall miss latency
577 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency
578 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency
579 system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623 # average overall miss latency
580 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
581 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
582 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
583 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
584 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
585 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
586 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
587 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
588 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
589 system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
590 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 223 # number of ReadCleanReq MSHR misses
591 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 223 # number of ReadCleanReq MSHR misses
592 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses
593 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses
594 system.cpu.l2cache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
595 system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
596 system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses
597 system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
598 system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
599 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
600 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles
601 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles
602 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14192000 # number of ReadCleanReq MSHR miss cycles
603 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14192000 # number of ReadCleanReq MSHR miss cycles
604 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles
605 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles
606 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14192000 # number of demand (read+write) MSHR miss cycles
607 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles
608 system.cpu.l2cache.demand_mshr_miss_latency::total 19673000 # number of demand (read+write) MSHR miss cycles
609 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14192000 # number of overall MSHR miss cycles
610 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles
611 system.cpu.l2cache.overall_mshr_miss_latency::total 19673000 # number of overall MSHR miss cycles
612 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
613 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
614 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
615 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
616 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
617 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
618 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
619 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
620 system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
621 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
622 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
623 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
624 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency
625 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency
626 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605 # average ReadCleanReq mshr miss latency
627 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605 # average ReadCleanReq mshr miss latency
628 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency
629 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency
630 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency
631 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
632 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
633 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency
634 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
635 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
636 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
637 system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter.
638 system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
639 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
640 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
641 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
642 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
643 system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
644 system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
645 system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
646 system.cpu.toL2Bus.trans_dist::ReadCleanReq 223 # Transaction distribution
647 system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution
648 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
649 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
650 system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
651 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
652 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
653 system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
654 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
655 system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
656 system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
657 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
658 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
659 system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
660 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
661 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
662 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
663 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
664 system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
665 system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
666 system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
667 system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
668 system.cpu.toL2Bus.respLayer0.occupancy 334500 # Layer occupancy (ticks)
669 system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
670 system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
671 system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
672 system.membus.trans_dist::ReadResp 281 # Transaction distribution
673 system.membus.trans_dist::ReadExReq 27 # Transaction distribution
674 system.membus.trans_dist::ReadExResp 27 # Transaction distribution
675 system.membus.trans_dist::ReadSharedReq 281 # Transaction distribution
676 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
677 system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
678 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
679 system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
680 system.membus.snoops 0 # Total snoops (count)
681 system.membus.snoop_fanout::samples 308 # Request fanout histogram
682 system.membus.snoop_fanout::mean 0 # Request fanout histogram
683 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
684 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
685 system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
686 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
687 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
688 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
689 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
690 system.membus.snoop_fanout::total 308 # Request fanout histogram
691 system.membus.reqLayer0.occupancy 359500 # Layer occupancy (ticks)
692 system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
693 system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks)
694 system.membus.respLayer1.utilization 8.2 # Layer utilization (%)
696 ---------- End Simulation Statistics ----------
projects / gem5.git / blob