2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000012 # Number of seconds simulated
4 sim_ticks 11933500 # Number of ticks simulated
5 final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 492 # Simulator instruction rate (inst/s)
8 host_op_rate 492 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2461163 # Simulator tick rate (ticks/s)
10 host_mem_usage 226156 # Number of bytes of host memory used
11 host_seconds 4.85 # Real time elapsed on the host
12 sim_insts 2387 # Number of instructions simulated
13 sim_ops 2387 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 273 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 17472 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 11844000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 273 # Categorize read packet sizes
81 system.physmem.writePktSize::0 0 # Categorize write packet sizes
82 system.physmem.writePktSize::1 0 # Categorize write packet sizes
83 system.physmem.writePktSize::2 0 # Categorize write packet sizes
84 system.physmem.writePktSize::3 0 # Categorize write packet sizes
85 system.physmem.writePktSize::4 0 # Categorize write packet sizes
86 system.physmem.writePktSize::5 0 # Categorize write packet sizes
87 system.physmem.writePktSize::6 0 # Categorize write packet sizes
88 system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see
89 system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152 system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation
153 system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation
154 system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation
155 system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation
156 system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation
157 system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation
167 system.physmem.totQLat 1190000 # Total cycles spent in queuing delays
168 system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests
169 system.physmem.totBusLat 1365000 # Total cycles spent in databus access
170 system.physmem.totBankLat 4180000 # Total cycles spent in bank access
171 system.physmem.avgQLat 4358.97 # Average queueing delay per request
172 system.physmem.avgBankLat 15311.36 # Average bank access latency per request
173 system.physmem.avgBusLat 5000.00 # Average bus latency per request
174 system.physmem.avgMemAccLat 24670.33 # Average memory access latency
175 system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s
176 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177 system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s
178 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
180 system.physmem.busUtil 11.44 # Data bus utilization in percentage
181 system.physmem.avgRdQLen 0.56 # Average read queue length over time
182 system.physmem.avgWrQLen 0.00 # Average write queue length over time
183 system.physmem.readRowHits 240 # Number of row buffer hits during reads
184 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185 system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
186 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187 system.physmem.avgGap 43384.62 # Average gap between requests
188 system.membus.throughput 1464113630 # Throughput (bytes/s)
189 system.membus.trans_dist::ReadReq 249 # Transaction distribution
190 system.membus.trans_dist::ReadResp 249 # Transaction distribution
191 system.membus.trans_dist::ReadExReq 24 # Transaction distribution
192 system.membus.trans_dist::ReadExResp 24 # Transaction distribution
193 system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes)
194 system.membus.pkt_count 546 # Packet count per connected master and slave (bytes)
195 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes)
196 system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
197 system.membus.data_through_bus 17472 # Total data (bytes)
198 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
199 system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
200 system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
201 system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks)
202 system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
203 system.cpu.branchPred.lookups 1175 # Number of BP lookups
204 system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted
205 system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
206 system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups
207 system.cpu.branchPred.BTBHits 253 # Number of BTB hits
208 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
209 system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage
210 system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target.
211 system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions.
212 system.cpu.dtb.fetch_hits 0 # ITB hits
213 system.cpu.dtb.fetch_misses 0 # ITB misses
214 system.cpu.dtb.fetch_acv 0 # ITB acv
215 system.cpu.dtb.fetch_accesses 0 # ITB accesses
216 system.cpu.dtb.read_hits 707 # DTB read hits
217 system.cpu.dtb.read_misses 31 # DTB read misses
218 system.cpu.dtb.read_acv 1 # DTB read access violations
219 system.cpu.dtb.read_accesses 738 # DTB read accesses
220 system.cpu.dtb.write_hits 371 # DTB write hits
221 system.cpu.dtb.write_misses 20 # DTB write misses
222 system.cpu.dtb.write_acv 0 # DTB write access violations
223 system.cpu.dtb.write_accesses 391 # DTB write accesses
224 system.cpu.dtb.data_hits 1078 # DTB hits
225 system.cpu.dtb.data_misses 51 # DTB misses
226 system.cpu.dtb.data_acv 1 # DTB access violations
227 system.cpu.dtb.data_accesses 1129 # DTB accesses
228 system.cpu.itb.fetch_hits 1067 # ITB hits
229 system.cpu.itb.fetch_misses 30 # ITB misses
230 system.cpu.itb.fetch_acv 0 # ITB acv
231 system.cpu.itb.fetch_accesses 1097 # ITB accesses
232 system.cpu.itb.read_hits 0 # DTB read hits
233 system.cpu.itb.read_misses 0 # DTB read misses
234 system.cpu.itb.read_acv 0 # DTB read access violations
235 system.cpu.itb.read_accesses 0 # DTB read accesses
236 system.cpu.itb.write_hits 0 # DTB write hits
237 system.cpu.itb.write_misses 0 # DTB write misses
238 system.cpu.itb.write_acv 0 # DTB write access violations
239 system.cpu.itb.write_accesses 0 # DTB write accesses
240 system.cpu.itb.data_hits 0 # DTB hits
241 system.cpu.itb.data_misses 0 # DTB misses
242 system.cpu.itb.data_acv 0 # DTB access violations
243 system.cpu.itb.data_accesses 0 # DTB accesses
244 system.cpu.workload.num_syscalls 4 # Number of system calls
245 system.cpu.numCycles 23868 # number of cpu cycles simulated
246 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
247 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
248 system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss
249 system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed
250 system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered
251 system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken
252 system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked
253 system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing
254 system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked
255 system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
256 system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps
257 system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
258 system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched
259 system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed
260 system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total)
265 system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total)
266 system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total)
267 system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total)
268 system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total)
269 system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total)
270 system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total)
271 system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total)
272 system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total)
273 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
274 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
275 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
276 system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total)
277 system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle
278 system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle
279 system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle
280 system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked
281 system.cpu.decode.RunCycles 1156 # Number of cycles decode is running
282 system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking
283 system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing
284 system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch
285 system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
286 system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode
287 system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
288 system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing
289 system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle
290 system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
291 system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
292 system.cpu.rename.RunCycles 1065 # Number of cycles rename is running
293 system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking
294 system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename
295 system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
296 system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
297 system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full
298 system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed
299 system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made
300 system.cpu.rename.int_rename_lookups 6674 # Number of integer rename lookups
301 system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
302 system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
303 system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing
304 system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
305 system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
306 system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer
307 system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit.
308 system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
309 system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
310 system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
311 system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec)
312 system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
313 system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued
314 system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
315 system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling
316 system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph
317 system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
318 system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle
319 system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
322 system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle
323 system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle
324 system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle
325 system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle
326 system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle
327 system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle
328 system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle
329 system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle
330 system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle
331 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
332 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
333 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
334 system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle
335 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
336 system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
337 system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
338 system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available
339 system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available
340 system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available
341 system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available
342 system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available
343 system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available
344 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available
353 system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available
354 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available
355 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available
356 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available
357 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available
358 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available
359 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available
360 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available
361 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available
362 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available
363 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
365 system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available
366 system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available
367 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
368 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
369 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
370 system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued
371 system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued
372 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued
373 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued
374 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued
375 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued
376 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued
377 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued
378 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued
386 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued
387 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued
388 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued
389 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued
390 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued
391 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued
392 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued
393 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued
394 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued
395 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued
396 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued
397 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued
398 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued
399 system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued
400 system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued
401 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
402 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
403 system.cpu.iq.FU_type_0::total 4046 # Type of FU issued
404 system.cpu.iq.rate 0.169516 # Inst issue rate
405 system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
406 system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst)
407 system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads
408 system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes
409 system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses
410 system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
411 system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
412 system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
413 system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses
414 system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
415 system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
416 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
417 system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed
418 system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
419 system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
420 system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed
421 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
422 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
423 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
424 system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
425 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
426 system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing
427 system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking
428 system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
429 system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ
430 system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
431 system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions
432 system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
433 system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
434 system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
435 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
436 system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
437 system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
438 system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly
439 system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute
440 system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions
441 system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed
442 system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute
443 system.cpu.iew.exec_swp 0 # number of swp insts executed
444 system.cpu.iew.exec_nop 338 # number of nop insts executed
445 system.cpu.iew.exec_refs 1130 # number of memory reference insts executed
446 system.cpu.iew.exec_branches 644 # Number of branches executed
447 system.cpu.iew.exec_stores 391 # Number of stores executed
448 system.cpu.iew.exec_rate 0.161513 # Inst execution rate
449 system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit
450 system.cpu.iew.wb_count 3661 # cumulative count of insts written-back
451 system.cpu.iew.wb_producers 1709 # num instructions producing a value
452 system.cpu.iew.wb_consumers 2209 # num instructions consuming a value
453 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
454 system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle
455 system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back
456 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
457 system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit
458 system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
459 system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
460 system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle
461 system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
464 system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle
465 system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle
466 system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle
467 system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle
468 system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle
469 system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle
470 system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle
471 system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle
472 system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle
473 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
474 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
475 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
476 system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle
477 system.cpu.commit.committedInsts 2576 # Number of instructions committed
478 system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
479 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
480 system.cpu.commit.refs 709 # Number of memory references committed
481 system.cpu.commit.loads 415 # Number of loads committed
482 system.cpu.commit.membars 0 # Number of memory barriers committed
483 system.cpu.commit.branches 396 # Number of branches committed
484 system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
485 system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
486 system.cpu.commit.function_calls 71 # Number of function calls committed.
487 system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached
488 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
489 system.cpu.rob.rob_reads 12303 # The number of ROB reads
490 system.cpu.rob.rob_writes 11127 # The number of ROB writes
491 system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself
492 system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling
493 system.cpu.committedInsts 2387 # Number of Instructions Simulated
494 system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
495 system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
496 system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction
497 system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads
498 system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle
499 system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads
500 system.cpu.int_regfile_reads 4674 # number of integer regfile reads
501 system.cpu.int_regfile_writes 2826 # number of integer regfile writes
502 system.cpu.fp_regfile_reads 6 # number of floating regfile reads
503 system.cpu.misc_regfile_reads 1 # number of misc regfile reads
504 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
505 system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s)
506 system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution
507 system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
508 system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
509 system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
510 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes)
511 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes)
512 system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes)
513 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes)
514 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes)
515 system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
516 system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes)
517 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
518 system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
519 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
520 system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks)
521 system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
522 system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks)
523 system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
524 system.cpu.icache.tags.replacements 0 # number of replacements
525 system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use
526 system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks.
527 system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
528 system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks.
529 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
530 system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor
531 system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy
532 system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy
533 system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits
534 system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits
535 system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits
536 system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits
537 system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits
538 system.cpu.icache.overall_hits::total 816 # number of overall hits
539 system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses
540 system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses
541 system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses
542 system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses
543 system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses
544 system.cpu.icache.overall_misses::total 251 # number of overall misses
545 system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles
546 system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles
547 system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles
548 system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles
549 system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles
550 system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles
551 system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses)
552 system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses)
553 system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses
554 system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses
555 system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses
556 system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses
557 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses
558 system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses
559 system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses
560 system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses
561 system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses
562 system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses
563 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency
564 system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency
565 system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency
566 system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency
567 system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency
568 system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency
569 system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked
570 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
571 system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
572 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
573 system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked
574 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
575 system.cpu.icache.fast_writes 0 # number of fast writes performed
576 system.cpu.icache.cache_copies 0 # number of cache copies performed
577 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits
578 system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
579 system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits
580 system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits
581 system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits
582 system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits
583 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
584 system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
585 system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
586 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
587 system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
588 system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
589 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12795749 # number of ReadReq MSHR miss cycles
590 system.cpu.icache.ReadReq_mshr_miss_latency::total 12795749 # number of ReadReq MSHR miss cycles
591 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12795749 # number of demand (read+write) MSHR miss cycles
592 system.cpu.icache.demand_mshr_miss_latency::total 12795749 # number of demand (read+write) MSHR miss cycles
593 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12795749 # number of overall MSHR miss cycles
594 system.cpu.icache.overall_mshr_miss_latency::total 12795749 # number of overall MSHR miss cycles
595 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for ReadReq accesses
596 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176195 # mshr miss rate for ReadReq accesses
597 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for demand accesses
598 system.cpu.icache.demand_mshr_miss_rate::total 0.176195 # mshr miss rate for demand accesses
599 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses
600 system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses
601 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency
602 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency
603 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency
604 system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency
605 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency
606 system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency
607 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
608 system.cpu.l2cache.tags.replacements 0 # number of replacements
609 system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use
610 system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
611 system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
612 system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
613 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
614 system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor
615 system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor
616 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy
617 system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy
618 system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy
619 system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
620 system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
621 system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
622 system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
623 system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
624 system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses
625 system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
626 system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses
627 system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
628 system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
629 system.cpu.l2cache.overall_misses::total 273 # number of overall misses
630 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12607000 # number of ReadReq miss cycles
631 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4547250 # number of ReadReq miss cycles
632 system.cpu.l2cache.ReadReq_miss_latency::total 17154250 # number of ReadReq miss cycles
633 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1720750 # number of ReadExReq miss cycles
634 system.cpu.l2cache.ReadExReq_miss_latency::total 1720750 # number of ReadExReq miss cycles
635 system.cpu.l2cache.demand_miss_latency::cpu.inst 12607000 # number of demand (read+write) miss cycles
636 system.cpu.l2cache.demand_miss_latency::cpu.data 6268000 # number of demand (read+write) miss cycles
637 system.cpu.l2cache.demand_miss_latency::total 18875000 # number of demand (read+write) miss cycles
638 system.cpu.l2cache.overall_miss_latency::cpu.inst 12607000 # number of overall miss cycles
639 system.cpu.l2cache.overall_miss_latency::cpu.data 6268000 # number of overall miss cycles
640 system.cpu.l2cache.overall_miss_latency::total 18875000 # number of overall miss cycles
641 system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
642 system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
643 system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
644 system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
645 system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
646 system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses
647 system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
648 system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses
649 system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses
650 system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
651 system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses
652 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
653 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
654 system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
655 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
656 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
657 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
658 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
659 system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
660 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
661 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
662 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
663 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67058.510638 # average ReadReq miss latency
664 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency
665 system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency
666 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency
667 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency
668 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency
669 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency
670 system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency
671 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency
672 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency
673 system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency
674 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
675 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
676 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
677 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
678 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
679 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
680 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
681 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
682 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
683 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
684 system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
685 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
686 system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
687 system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
688 system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
689 system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
690 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
691 system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
692 system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
693 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles
694 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles
695 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles
696 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles
697 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles
698 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles
699 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles
700 system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles
701 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles
702 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles
703 system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles
704 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
705 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
706 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
707 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
708 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
709 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
710 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
711 system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
712 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
713 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
714 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
715 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency
716 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency
717 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency
718 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency
719 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency
720 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency
721 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency
722 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency
723 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency
724 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency
725 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency
726 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
727 system.cpu.dcache.tags.replacements 0 # number of replacements
728 system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use
729 system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks.
730 system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
731 system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks.
732 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
733 system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor
734 system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy
735 system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy
736 system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits
737 system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits
738 system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
739 system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
740 system.cpu.dcache.demand_hits::cpu.data 758 # number of demand (read+write) hits
741 system.cpu.dcache.demand_hits::total 758 # number of demand (read+write) hits
742 system.cpu.dcache.overall_hits::cpu.data 758 # number of overall hits
743 system.cpu.dcache.overall_hits::total 758 # number of overall hits
744 system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses
745 system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses
746 system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
747 system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
748 system.cpu.dcache.demand_misses::cpu.data 194 # number of demand (read+write) misses
749 system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses
750 system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses
751 system.cpu.dcache.overall_misses::total 194 # number of overall misses
752 system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles
753 system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles
754 system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles
755 system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles
756 system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles
757 system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles
758 system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles
759 system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles
760 system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses)
761 system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses)
762 system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
763 system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
764 system.cpu.dcache.demand_accesses::cpu.data 952 # number of demand (read+write) accesses
765 system.cpu.dcache.demand_accesses::total 952 # number of demand (read+write) accesses
766 system.cpu.dcache.overall_accesses::cpu.data 952 # number of overall (read+write) accesses
767 system.cpu.dcache.overall_accesses::total 952 # number of overall (read+write) accesses
768 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.171733 # miss rate for ReadReq accesses
769 system.cpu.dcache.ReadReq_miss_rate::total 0.171733 # miss rate for ReadReq accesses
770 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
771 system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
772 system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 # miss rate for demand accesses
773 system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses
774 system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses
775 system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses
776 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency
777 system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency
778 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency
779 system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency
780 system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency
781 system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency
782 system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency
783 system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency
784 system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
785 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
786 system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
787 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
788 system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.250000 # average number of cycles each access was blocked
789 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
790 system.cpu.dcache.fast_writes 0 # number of fast writes performed
791 system.cpu.dcache.cache_copies 0 # number of cache copies performed
792 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
793 system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
794 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
795 system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
796 system.cpu.dcache.demand_mshr_hits::cpu.data 109 # number of demand (read+write) MSHR hits
797 system.cpu.dcache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits
798 system.cpu.dcache.overall_mshr_hits::cpu.data 109 # number of overall MSHR hits
799 system.cpu.dcache.overall_mshr_hits::total 109 # number of overall MSHR hits
800 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
801 system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
802 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
803 system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
804 system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
805 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
806 system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
807 system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
808 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles
809 system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles
810 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles
811 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles
812 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles
813 system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles
814 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles
815 system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles
816 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses
817 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses
818 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
819 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
820 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for demand accesses
821 system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses
822 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses
823 system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses
824 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency
825 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency
826 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency
827 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency
828 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency
829 system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency
830 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency
831 system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency
832 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
834 ---------- End Simulation Statistics ----------
projects / gem5.git / blob