2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000007 # Number of seconds simulated
4 sim_ticks 6833000 # Number of ticks simulated
5 final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 46364 # Simulator instruction rate (inst/s)
8 host_tick_rate 132671945 # Simulator tick rate (ticks/s)
9 host_mem_usage 207164 # Number of bytes of host memory used
10 host_seconds 0.05 # Real time elapsed on the host
11 sim_insts 2387 # Number of instructions simulated
12 system.physmem.bytes_read 17280 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 270 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.dtb.fetch_hits 0 # ITB hits
22 system.cpu.dtb.fetch_misses 0 # ITB misses
23 system.cpu.dtb.fetch_acv 0 # ITB acv
24 system.cpu.dtb.fetch_accesses 0 # ITB accesses
25 system.cpu.dtb.read_hits 679 # DTB read hits
26 system.cpu.dtb.read_misses 26 # DTB read misses
27 system.cpu.dtb.read_acv 1 # DTB read access violations
28 system.cpu.dtb.read_accesses 705 # DTB read accesses
29 system.cpu.dtb.write_hits 356 # DTB write hits
30 system.cpu.dtb.write_misses 18 # DTB write misses
31 system.cpu.dtb.write_acv 0 # DTB write access violations
32 system.cpu.dtb.write_accesses 374 # DTB write accesses
33 system.cpu.dtb.data_hits 1035 # DTB hits
34 system.cpu.dtb.data_misses 44 # DTB misses
35 system.cpu.dtb.data_acv 1 # DTB access violations
36 system.cpu.dtb.data_accesses 1079 # DTB accesses
37 system.cpu.itb.fetch_hits 941 # ITB hits
38 system.cpu.itb.fetch_misses 30 # ITB misses
39 system.cpu.itb.fetch_acv 0 # ITB acv
40 system.cpu.itb.fetch_accesses 971 # ITB accesses
41 system.cpu.itb.read_hits 0 # DTB read hits
42 system.cpu.itb.read_misses 0 # DTB read misses
43 system.cpu.itb.read_acv 0 # DTB read access violations
44 system.cpu.itb.read_accesses 0 # DTB read accesses
45 system.cpu.itb.write_hits 0 # DTB write hits
46 system.cpu.itb.write_misses 0 # DTB write misses
47 system.cpu.itb.write_acv 0 # DTB write access violations
48 system.cpu.itb.write_accesses 0 # DTB write accesses
49 system.cpu.itb.data_hits 0 # DTB hits
50 system.cpu.itb.data_misses 0 # DTB misses
51 system.cpu.itb.data_acv 0 # DTB access violations
52 system.cpu.itb.data_accesses 0 # DTB accesses
53 system.cpu.workload.num_syscalls 4 # Number of system calls
54 system.cpu.numCycles 13667 # number of cpu cycles simulated
55 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
56 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
57 system.cpu.BPredUnit.lookups 1038 # Number of BP lookups
58 system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted
59 system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect
60 system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups
61 system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
62 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
63 system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target.
64 system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions.
65 system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss
66 system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed
67 system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered
68 system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken
69 system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked
70 system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing
71 system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked
72 system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
73 system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
74 system.cpu.fetch.CacheLines 941 # Number of cache lines fetched
75 system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed
76 system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total)
77 system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total)
78 system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total)
79 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
80 system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total)
81 system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total)
82 system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total)
83 system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total)
84 system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total)
85 system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle
94 system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle
95 system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle
96 system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked
97 system.cpu.decode.RunCycles 1081 # Number of cycles decode is running
98 system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking
99 system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing
100 system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
101 system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction
102 system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode
103 system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode
104 system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing
105 system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle
106 system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking
107 system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst
108 system.cpu.rename.RunCycles 995 # Number of cycles rename is running
109 system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking
110 system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename
111 system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full
112 system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed
113 system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made
114 system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups
115 system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
116 system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
117 system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing
118 system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
119 system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
120 system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer
121 system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit.
122 system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit.
123 system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
124 system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
125 system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec)
126 system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
127 system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued
128 system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued
129 system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling
130 system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph
131 system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
132 system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle
133 system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle
134 system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle
135 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
136 system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle
137 system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle
138 system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle
139 system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle
140 system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle
141 system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle
142 system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle
144 system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle
149 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
150 system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available
151 system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available
152 system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available
153 system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available
154 system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available
155 system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available
156 system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available
157 system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available
158 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
159 system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available
160 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available
161 system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available
162 system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available
163 system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available
164 system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available
165 system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available
166 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available
167 system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available
168 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
179 system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available
180 system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available
181 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
182 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
183 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
184 system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued
185 system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued
186 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued
187 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued
188 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued
189 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued
190 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued
191 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued
192 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued
193 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued
194 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued
195 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued
196 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued
197 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued
198 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued
199 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued
200 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued
201 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued
202 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued
213 system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued
214 system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued
215 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
216 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
217 system.cpu.iq.FU_type_0::total 3881 # Type of FU issued
218 system.cpu.iq.rate 0.283969 # Inst issue rate
219 system.cpu.iq.fu_busy_cnt 41 # FU busy when requested
220 system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst)
221 system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads
222 system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes
223 system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses
224 system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
225 system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
226 system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
227 system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses
228 system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
229 system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores
230 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
231 system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed
232 system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
233 system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
234 system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed
235 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
236 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
237 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
238 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
239 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
240 system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing
241 system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking
242 system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
243 system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ
244 system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch
245 system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions
246 system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions
247 system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
248 system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
249 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
250 system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
251 system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
252 system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly
253 system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute
254 system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions
255 system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed
256 system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute
257 system.cpu.iew.exec_swp 0 # number of swp insts executed
258 system.cpu.iew.exec_nop 338 # number of nop insts executed
259 system.cpu.iew.exec_refs 1080 # number of memory reference insts executed
260 system.cpu.iew.exec_branches 629 # Number of branches executed
261 system.cpu.iew.exec_stores 374 # Number of stores executed
262 system.cpu.iew.exec_rate 0.274310 # Inst execution rate
263 system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit
264 system.cpu.iew.wb_count 3579 # cumulative count of insts written-back
265 system.cpu.iew.wb_producers 1702 # num instructions producing a value
266 system.cpu.iew.wb_consumers 2165 # num instructions consuming a value
267 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
268 system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle
269 system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back
270 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
271 system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
272 system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit
273 system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
274 system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted
275 system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle
276 system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle
277 system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle
278 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
279 system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle
280 system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle
281 system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle
282 system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle
283 system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle
284 system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle
286 system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle
287 system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle
288 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
289 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
290 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
291 system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle
292 system.cpu.commit.count 2576 # Number of instructions committed
293 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
294 system.cpu.commit.refs 709 # Number of memory references committed
295 system.cpu.commit.loads 415 # Number of loads committed
296 system.cpu.commit.membars 0 # Number of memory barriers committed
297 system.cpu.commit.branches 396 # Number of branches committed
298 system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
299 system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
300 system.cpu.commit.function_calls 71 # Number of function calls committed.
301 system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached
302 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
303 system.cpu.rob.rob_reads 10645 # The number of ROB reads
304 system.cpu.rob.rob_writes 10410 # The number of ROB writes
305 system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself
306 system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling
307 system.cpu.committedInsts 2387 # Number of Instructions Simulated
308 system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
309 system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction
310 system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads
311 system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle
312 system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads
313 system.cpu.int_regfile_reads 4520 # number of integer regfile reads
314 system.cpu.int_regfile_writes 2768 # number of integer regfile writes
315 system.cpu.fp_regfile_reads 6 # number of floating regfile reads
316 system.cpu.misc_regfile_reads 1 # number of misc regfile reads
317 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
318 system.cpu.icache.replacements 0 # number of replacements
319 system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use
320 system.cpu.icache.total_refs 700 # Total number of references to valid blocks.
321 system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks.
322 system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks.
323 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
324 system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context
325 system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy
326 system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits
327 system.cpu.icache.demand_hits 700 # number of demand (read+write) hits
328 system.cpu.icache.overall_hits 700 # number of overall hits
329 system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
330 system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
331 system.cpu.icache.overall_misses 241 # number of overall misses
332 system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles
333 system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles
334 system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles
335 system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses)
336 system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses
337 system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses
338 system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses
339 system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses
340 system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses
341 system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency
342 system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency
343 system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency
344 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
345 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
346 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
347 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
348 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
349 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
350 system.cpu.icache.fast_writes 0 # number of fast writes performed
351 system.cpu.icache.cache_copies 0 # number of cache copies performed
352 system.cpu.icache.writebacks 0 # number of writebacks
353 system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
354 system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
355 system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
356 system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses
357 system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
358 system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses
359 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
360 system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles
361 system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles
362 system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles
363 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
364 system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses
365 system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses
366 system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses
367 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency
368 system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency
369 system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency
370 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
371 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
372 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
373 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
374 system.cpu.dcache.replacements 0 # number of replacements
375 system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use
376 system.cpu.dcache.total_refs 765 # Total number of references to valid blocks.
377 system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
378 system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks.
379 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
380 system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context
381 system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy
382 system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits
383 system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits
384 system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits
385 system.cpu.dcache.overall_hits 765 # number of overall hits
386 system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses
387 system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses
388 system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses
389 system.cpu.dcache.overall_misses 173 # number of overall misses
390 system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles
391 system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles
392 system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles
393 system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles
394 system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses)
395 system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
396 system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses
397 system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses
398 system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses
399 system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses
400 system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses
401 system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses
402 system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency
403 system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency
404 system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency
405 system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency
406 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
407 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
408 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
409 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
410 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
411 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
412 system.cpu.dcache.fast_writes 0 # number of fast writes performed
413 system.cpu.dcache.cache_copies 0 # number of cache copies performed
414 system.cpu.dcache.writebacks 0 # number of writebacks
415 system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits
416 system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits
417 system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits
418 system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits
419 system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
420 system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
421 system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
422 system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
423 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
424 system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles
425 system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles
426 system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles
427 system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles
428 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
429 system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses
430 system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
431 system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses
432 system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses
433 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency
434 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency
435 system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency
436 system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency
437 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
438 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
439 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
440 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
441 system.cpu.l2cache.replacements 0 # number of replacements
442 system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use
443 system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
444 system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks.
445 system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
446 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
447 system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context
448 system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy
449 system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
450 system.cpu.l2cache.overall_hits 0 # number of overall hits
451 system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses
452 system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
453 system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses
454 system.cpu.l2cache.overall_misses 270 # number of overall misses
455 system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles
456 system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles
457 system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles
458 system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles
459 system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses)
460 system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
461 system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses
462 system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses
463 system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
464 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
465 system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
466 system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
467 system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency
468 system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency
469 system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency
470 system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency
471 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
472 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
473 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
474 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
475 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
476 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
477 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
478 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
479 system.cpu.l2cache.writebacks 0 # number of writebacks
480 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
481 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
482 system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses
483 system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
484 system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses
485 system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses
486 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
487 system.cpu.l2cache.ReadReq_mshr_miss_latency 7661500 # number of ReadReq MSHR miss cycles
488 system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
489 system.cpu.l2cache.demand_mshr_miss_latency 8417500 # number of demand (read+write) MSHR miss cycles
490 system.cpu.l2cache.overall_mshr_miss_latency 8417500 # number of overall MSHR miss cycles
491 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
492 system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
493 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
494 system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
495 system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
496 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943 # average ReadReq mshr miss latency
497 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
498 system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency
499 system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency
500 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
501 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
502 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
503 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
505 ---------- End Simulation Statistics ----------
projects / gem5.git / blob