2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000007 # Number of seconds simulated
4 sim_ticks 7079000 # Number of ticks simulated
5 final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 8209 # Simulator instruction rate (inst/s)
8 host_op_rate 8209 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 24342914 # Simulator tick rate (ticks/s)
10 host_mem_usage 218360 # Number of bytes of host memory used
11 host_seconds 0.29 # Real time elapsed on the host
12 sim_insts 2387 # Number of instructions simulated
13 sim_ops 2387 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s)
30 system.cpu.dtb.fetch_hits 0 # ITB hits
31 system.cpu.dtb.fetch_misses 0 # ITB misses
32 system.cpu.dtb.fetch_acv 0 # ITB acv
33 system.cpu.dtb.fetch_accesses 0 # ITB accesses
34 system.cpu.dtb.read_hits 712 # DTB read hits
35 system.cpu.dtb.read_misses 34 # DTB read misses
36 system.cpu.dtb.read_acv 1 # DTB read access violations
37 system.cpu.dtb.read_accesses 746 # DTB read accesses
38 system.cpu.dtb.write_hits 367 # DTB write hits
39 system.cpu.dtb.write_misses 20 # DTB write misses
40 system.cpu.dtb.write_acv 0 # DTB write access violations
41 system.cpu.dtb.write_accesses 387 # DTB write accesses
42 system.cpu.dtb.data_hits 1079 # DTB hits
43 system.cpu.dtb.data_misses 54 # DTB misses
44 system.cpu.dtb.data_acv 1 # DTB access violations
45 system.cpu.dtb.data_accesses 1133 # DTB accesses
46 system.cpu.itb.fetch_hits 1015 # ITB hits
47 system.cpu.itb.fetch_misses 30 # ITB misses
48 system.cpu.itb.fetch_acv 0 # ITB acv
49 system.cpu.itb.fetch_accesses 1045 # ITB accesses
50 system.cpu.itb.read_hits 0 # DTB read hits
51 system.cpu.itb.read_misses 0 # DTB read misses
52 system.cpu.itb.read_acv 0 # DTB read access violations
53 system.cpu.itb.read_accesses 0 # DTB read accesses
54 system.cpu.itb.write_hits 0 # DTB write hits
55 system.cpu.itb.write_misses 0 # DTB write misses
56 system.cpu.itb.write_acv 0 # DTB write access violations
57 system.cpu.itb.write_accesses 0 # DTB write accesses
58 system.cpu.itb.data_hits 0 # DTB hits
59 system.cpu.itb.data_misses 0 # DTB misses
60 system.cpu.itb.data_acv 0 # DTB access violations
61 system.cpu.itb.data_accesses 0 # DTB accesses
62 system.cpu.workload.num_syscalls 4 # Number of system calls
63 system.cpu.numCycles 14159 # number of cpu cycles simulated
64 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
65 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
66 system.cpu.BPredUnit.lookups 1131 # Number of BP lookups
67 system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
68 system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect
69 system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups
70 system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
71 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
72 system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target.
73 system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
74 system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss
75 system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed
76 system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered
77 system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken
78 system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked
79 system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing
80 system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked
81 system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
82 system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps
83 system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched
84 system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed
85 system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total)
86 system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total)
94 system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total)
95 system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total)
96 system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total)
97 system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total)
98 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
99 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
100 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
101 system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total)
102 system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle
103 system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle
104 system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle
105 system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
106 system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
107 system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking
108 system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing
109 system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch
110 system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
111 system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode
112 system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
113 system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing
114 system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle
115 system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking
116 system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst
117 system.cpu.rename.RunCycles 1058 # Number of cycles rename is running
118 system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking
119 system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename
120 system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full
121 system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
122 system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed
123 system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made
124 system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups
125 system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
126 system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
127 system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing
128 system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
129 system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
130 system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer
131 system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit.
132 system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit.
133 system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
134 system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
135 system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec)
136 system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
137 system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued
138 system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued
139 system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling
140 system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph
141 system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
142 system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle
143 system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle
144 system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle
149 system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle
150 system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle
151 system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle
152 system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle
153 system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle
154 system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle
155 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
156 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
157 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
158 system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle
159 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
160 system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available
161 system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available
162 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available
163 system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available
164 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available
165 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available
166 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available
167 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available
168 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
169 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available
170 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available
181 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available
182 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available
183 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available
184 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available
185 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available
186 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available
187 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available
188 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
189 system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available
190 system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
191 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
192 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
193 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
194 system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued
195 system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued
196 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
197 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
198 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
199 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
200 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
201 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
202 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
203 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
204 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
215 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
216 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued
217 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued
218 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
219 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued
220 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
221 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued
222 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
223 system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued
224 system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued
225 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
226 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
227 system.cpu.iq.FU_type_0::total 4054 # Type of FU issued
228 system.cpu.iq.rate 0.286320 # Inst issue rate
229 system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
230 system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst)
231 system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads
232 system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes
233 system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses
234 system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
235 system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
236 system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
237 system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses
238 system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
239 system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
240 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
241 system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed
242 system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
243 system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
244 system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed
245 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
246 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
247 system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
248 system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
249 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
250 system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing
251 system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking
252 system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
253 system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ
254 system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
255 system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions
256 system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions
257 system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
258 system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
259 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
260 system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
261 system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly
262 system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly
263 system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute
264 system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions
265 system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed
266 system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute
267 system.cpu.iew.exec_swp 0 # number of swp insts executed
268 system.cpu.iew.exec_nop 342 # number of nop insts executed
269 system.cpu.iew.exec_refs 1134 # number of memory reference insts executed
270 system.cpu.iew.exec_branches 652 # Number of branches executed
271 system.cpu.iew.exec_stores 387 # Number of stores executed
272 system.cpu.iew.exec_rate 0.275019 # Inst execution rate
273 system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit
274 system.cpu.iew.wb_count 3708 # cumulative count of insts written-back
275 system.cpu.iew.wb_producers 1740 # num instructions producing a value
276 system.cpu.iew.wb_consumers 2258 # num instructions consuming a value
277 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
278 system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle
279 system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back
280 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
281 system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit
282 system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
283 system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted
284 system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle
285 system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle
286 system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle
287 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
288 system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle
289 system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle
290 system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle
291 system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle
292 system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle
293 system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle
294 system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle
295 system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle
296 system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle
297 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
298 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
299 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
300 system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle
301 system.cpu.commit.committedInsts 2576 # Number of instructions committed
302 system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
303 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
304 system.cpu.commit.refs 709 # Number of memory references committed
305 system.cpu.commit.loads 415 # Number of loads committed
306 system.cpu.commit.membars 0 # Number of memory barriers committed
307 system.cpu.commit.branches 396 # Number of branches committed
308 system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
309 system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
310 system.cpu.commit.function_calls 71 # Number of function calls committed.
311 system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached
312 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
313 system.cpu.rob.rob_reads 11671 # The number of ROB reads
314 system.cpu.rob.rob_writes 11260 # The number of ROB writes
315 system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
316 system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling
317 system.cpu.committedInsts 2387 # Number of Instructions Simulated
318 system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
319 system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
320 system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction
321 system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads
322 system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle
323 system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads
324 system.cpu.int_regfile_reads 4712 # number of integer regfile reads
325 system.cpu.int_regfile_writes 2874 # number of integer regfile writes
326 system.cpu.fp_regfile_reads 6 # number of floating regfile reads
327 system.cpu.misc_regfile_reads 1 # number of misc regfile reads
328 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
329 system.cpu.icache.replacements 0 # number of replacements
330 system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use
331 system.cpu.icache.total_refs 767 # Total number of references to valid blocks.
332 system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks.
333 system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks.
334 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
335 system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor
336 system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy
337 system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy
338 system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits
339 system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits
340 system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits
341 system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits
342 system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits
343 system.cpu.icache.overall_hits::total 767 # number of overall hits
344 system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses
345 system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses
346 system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses
347 system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses
348 system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses
349 system.cpu.icache.overall_misses::total 248 # number of overall misses
350 system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles
351 system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles
352 system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles
353 system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles
354 system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles
355 system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles
356 system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses)
357 system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses)
358 system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses
359 system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses
360 system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses
361 system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses
362 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses
363 system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses
364 system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses
365 system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses
366 system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses
367 system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses
368 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency
369 system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency
370 system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency
371 system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency
372 system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency
373 system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency
374 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
375 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
376 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
377 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
378 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
379 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
380 system.cpu.icache.fast_writes 0 # number of fast writes performed
381 system.cpu.icache.cache_copies 0 # number of cache copies performed
382 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits
383 system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
384 system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits
385 system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits
386 system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits
387 system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits
388 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
389 system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
390 system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
391 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
392 system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
393 system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
394 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6948500 # number of ReadReq MSHR miss cycles
395 system.cpu.icache.ReadReq_mshr_miss_latency::total 6948500 # number of ReadReq MSHR miss cycles
396 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6948500 # number of demand (read+write) MSHR miss cycles
397 system.cpu.icache.demand_mshr_miss_latency::total 6948500 # number of demand (read+write) MSHR miss cycles
398 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6948500 # number of overall MSHR miss cycles
399 system.cpu.icache.overall_mshr_miss_latency::total 6948500 # number of overall MSHR miss cycles
400 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses
401 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses
402 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses
403 system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses
404 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses
405 system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses
406 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency
407 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency
408 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency
409 system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency
410 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency
411 system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency
412 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
413 system.cpu.dcache.replacements 0 # number of replacements
414 system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use
415 system.cpu.dcache.total_refs 773 # Total number of references to valid blocks.
416 system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
417 system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks.
418 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
419 system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor
420 system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy
421 system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy
422 system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits
423 system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits
424 system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
425 system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
426 system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits
427 system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits
428 system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits
429 system.cpu.dcache.overall_hits::total 773 # number of overall hits
430 system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses
431 system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses
432 system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
433 system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
434 system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
435 system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
436 system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
437 system.cpu.dcache.overall_misses::total 202 # number of overall misses
438 system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles
439 system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles
440 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles
441 system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles
442 system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles
443 system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles
444 system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles
445 system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles
446 system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses)
447 system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses)
448 system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
449 system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
450 system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses
451 system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses
452 system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses
453 system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses
454 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses
455 system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses
456 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
457 system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
458 system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses
459 system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses
460 system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses
461 system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses
462 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency
463 system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency
464 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency
465 system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency
466 system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency
467 system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency
468 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency
469 system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency
470 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
471 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
472 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
473 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
474 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
475 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
476 system.cpu.dcache.fast_writes 0 # number of fast writes performed
477 system.cpu.dcache.cache_copies 0 # number of cache copies performed
478 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
479 system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
480 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
481 system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
482 system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits
483 system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits
484 system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits
485 system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits
486 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
487 system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
488 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
489 system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
490 system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
491 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
492 system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
493 system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
494 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles
495 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles
496 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles
497 system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles
498 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles
499 system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles
500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles
501 system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles
502 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses
503 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses
504 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
505 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
506 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses
507 system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses
508 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses
509 system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses
510 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency
511 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency
512 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency
513 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency
514 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency
515 system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency
516 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency
517 system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency
518 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
519 system.cpu.l2cache.replacements 0 # number of replacements
520 system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use
521 system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
522 system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks.
523 system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
524 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
525 system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor
526 system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor
527 system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy
528 system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy
529 system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy
530 system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
531 system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
532 system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
533 system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
534 system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
535 system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses
536 system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
537 system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses
538 system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
539 system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
540 system.cpu.l2cache.overall_misses::total 273 # number of overall misses
541 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles
542 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles
543 system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles
544 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles
545 system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles
546 system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles
547 system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles
548 system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles
549 system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles
550 system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles
551 system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles
552 system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
553 system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
554 system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
555 system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
556 system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
557 system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses
558 system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
559 system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses
560 system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses
561 system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
562 system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses
563 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
564 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
565 system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
566 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
567 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
568 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
569 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
570 system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
571 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
572 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
573 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
574 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency
575 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency
576 system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency
577 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency
578 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency
579 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency
580 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency
581 system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency
582 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency
583 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency
584 system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency
585 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
586 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
587 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
588 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
589 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
590 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
591 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
592 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
593 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
594 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
595 system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
596 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
597 system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
598 system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
599 system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
600 system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
601 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
602 system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
603 system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
604 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles
605 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles
606 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles
607 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles
608 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles
609 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles
610 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles
611 system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles
612 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles
613 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles
614 system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles
615 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
616 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
617 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
618 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
619 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
620 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
621 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
622 system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
623 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
625 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
626 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency
627 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency
628 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency
629 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency
630 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency
631 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency
632 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency
633 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency
634 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency
635 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency
636 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency
637 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
639 ---------- End Simulation Statistics ----------
projects / gem5.git / blob