8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
23 memories=system.physmem
27 work_begin_ckpt_count=0
28 work_begin_cpu_id_exit=-1
29 work_begin_exit_count=0
30 work_cpus_ckpt_count=0
34 system_port=system.membus.slave[0]
40 voltage_domain=system.voltage_domain
44 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
46 clk_domain=system.cpu_clk_domain
48 do_checkpoint_insts=true
50 do_statistics_insts=true
54 function_trace_start=0
55 interrupts=system.cpu.interrupts
58 max_insts_all_threads=0
59 max_insts_any_thread=0
60 max_loads_all_threads=0
61 max_loads_any_thread=0
68 tracer=system.cpu.tracer
69 workload=system.cpu.workload
70 dcache_port=system.cpu.dcache.cpu_side
71 icache_port=system.cpu.icache.cpu_side
76 addr_ranges=0:18446744073709551615
78 clk_domain=system.cpu_clk_domain
85 prefetch_on_access=false
88 sequential_access=false
91 tags=system.cpu.dcache.tags
95 cpu_side=system.cpu.dcache_port
96 mem_side=system.cpu.toL2Bus.slave[1]
98 [system.cpu.dcache.tags]
102 clk_domain=system.cpu_clk_domain
105 sequential_access=false
116 addr_ranges=0:18446744073709551615
118 clk_domain=system.cpu_clk_domain
125 prefetch_on_access=false
128 sequential_access=false
131 tags=system.cpu.icache.tags
135 cpu_side=system.cpu.icache_port
136 mem_side=system.cpu.toL2Bus.slave[0]
138 [system.cpu.icache.tags]
142 clk_domain=system.cpu_clk_domain
145 sequential_access=false
148 [system.cpu.interrupts]
165 addr_ranges=0:18446744073709551615
167 clk_domain=system.cpu_clk_domain
174 prefetch_on_access=false
177 sequential_access=false
180 tags=system.cpu.l2cache.tags
184 cpu_side=system.cpu.toL2Bus.master[0]
185 mem_side=system.membus.slave[1]
187 [system.cpu.l2cache.tags]
191 clk_domain=system.cpu_clk_domain
194 sequential_access=false
199 clk_domain=system.cpu_clk_domain
203 use_default_range=false
205 master=system.cpu.l2cache.cpu_side
206 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
212 [system.cpu.workload]
221 executable=/dist/test-progs/hello/bin/alpha/tru64/hello
224 max_stack_size=67108864
232 [system.cpu_clk_domain]
236 voltage_domain=system.voltage_domain
240 clk_domain=system.clk_domain
244 use_default_range=false
246 master=system.physmem.port
247 slave=system.system_port system.cpu.l2cache.mem_side
252 clk_domain=system.clk_domain
253 conf_table_reported=true
260 port=system.membus.master[0]
262 [system.voltage_domain]