stats: update stats for cache occupancy and clock domain changes
[gem5.git] / tests / quick / se / 00.hello / ref / alpha / tru64 / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=false
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=System
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
14 boot_osflags=a
15 cache_line_size=64
16 clk_domain=system.clk_domain
17 eventq_index=0
18 init_param=0
19 kernel=
20 load_addr_mask=1099511627775
21 mem_mode=timing
22 mem_ranges=
23 memories=system.physmem
24 num_work_ids=16
25 readfile=
26 symbolfile=
27 work_begin_ckpt_count=0
28 work_begin_cpu_id_exit=-1
29 work_begin_exit_count=0
30 work_cpus_ckpt_count=0
31 work_end_ckpt_count=0
32 work_end_exit_count=0
33 work_item_id=-1
34 system_port=system.membus.slave[0]
35
36 [system.clk_domain]
37 type=SrcClockDomain
38 clock=1000
39 eventq_index=0
40 voltage_domain=system.voltage_domain
41
42 [system.cpu]
43 type=TimingSimpleCPU
44 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
45 checker=Null
46 clk_domain=system.cpu_clk_domain
47 cpu_id=0
48 do_checkpoint_insts=true
49 do_quiesce=true
50 do_statistics_insts=true
51 dtb=system.cpu.dtb
52 eventq_index=0
53 function_trace=false
54 function_trace_start=0
55 interrupts=system.cpu.interrupts
56 isa=system.cpu.isa
57 itb=system.cpu.itb
58 max_insts_all_threads=0
59 max_insts_any_thread=0
60 max_loads_all_threads=0
61 max_loads_any_thread=0
62 numThreads=1
63 profile=0
64 progress_interval=0
65 simpoint_start_insts=
66 switched_out=false
67 system=system
68 tracer=system.cpu.tracer
69 workload=system.cpu.workload
70 dcache_port=system.cpu.dcache.cpu_side
71 icache_port=system.cpu.icache.cpu_side
72
73 [system.cpu.dcache]
74 type=BaseCache
75 children=tags
76 addr_ranges=0:18446744073709551615
77 assoc=2
78 clk_domain=system.cpu_clk_domain
79 eventq_index=0
80 forward_snoops=true
81 hit_latency=2
82 is_top_level=true
83 max_miss_count=0
84 mshrs=4
85 prefetch_on_access=false
86 prefetcher=Null
87 response_latency=2
88 sequential_access=false
89 size=262144
90 system=system
91 tags=system.cpu.dcache.tags
92 tgts_per_mshr=20
93 two_queue=false
94 write_buffers=8
95 cpu_side=system.cpu.dcache_port
96 mem_side=system.cpu.toL2Bus.slave[1]
97
98 [system.cpu.dcache.tags]
99 type=LRU
100 assoc=2
101 block_size=64
102 clk_domain=system.cpu_clk_domain
103 eventq_index=0
104 hit_latency=2
105 sequential_access=false
106 size=262144
107
108 [system.cpu.dtb]
109 type=AlphaTLB
110 eventq_index=0
111 size=64
112
113 [system.cpu.icache]
114 type=BaseCache
115 children=tags
116 addr_ranges=0:18446744073709551615
117 assoc=2
118 clk_domain=system.cpu_clk_domain
119 eventq_index=0
120 forward_snoops=true
121 hit_latency=2
122 is_top_level=true
123 max_miss_count=0
124 mshrs=4
125 prefetch_on_access=false
126 prefetcher=Null
127 response_latency=2
128 sequential_access=false
129 size=131072
130 system=system
131 tags=system.cpu.icache.tags
132 tgts_per_mshr=20
133 two_queue=false
134 write_buffers=8
135 cpu_side=system.cpu.icache_port
136 mem_side=system.cpu.toL2Bus.slave[0]
137
138 [system.cpu.icache.tags]
139 type=LRU
140 assoc=2
141 block_size=64
142 clk_domain=system.cpu_clk_domain
143 eventq_index=0
144 hit_latency=2
145 sequential_access=false
146 size=131072
147
148 [system.cpu.interrupts]
149 type=AlphaInterrupts
150 eventq_index=0
151
152 [system.cpu.isa]
153 type=AlphaISA
154 eventq_index=0
155 system=system
156
157 [system.cpu.itb]
158 type=AlphaTLB
159 eventq_index=0
160 size=48
161
162 [system.cpu.l2cache]
163 type=BaseCache
164 children=tags
165 addr_ranges=0:18446744073709551615
166 assoc=8
167 clk_domain=system.cpu_clk_domain
168 eventq_index=0
169 forward_snoops=true
170 hit_latency=20
171 is_top_level=false
172 max_miss_count=0
173 mshrs=20
174 prefetch_on_access=false
175 prefetcher=Null
176 response_latency=20
177 sequential_access=false
178 size=2097152
179 system=system
180 tags=system.cpu.l2cache.tags
181 tgts_per_mshr=12
182 two_queue=false
183 write_buffers=8
184 cpu_side=system.cpu.toL2Bus.master[0]
185 mem_side=system.membus.slave[1]
186
187 [system.cpu.l2cache.tags]
188 type=LRU
189 assoc=8
190 block_size=64
191 clk_domain=system.cpu_clk_domain
192 eventq_index=0
193 hit_latency=20
194 sequential_access=false
195 size=2097152
196
197 [system.cpu.toL2Bus]
198 type=CoherentBus
199 clk_domain=system.cpu_clk_domain
200 eventq_index=0
201 header_cycles=1
202 system=system
203 use_default_range=false
204 width=32
205 master=system.cpu.l2cache.cpu_side
206 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
207
208 [system.cpu.tracer]
209 type=ExeTracer
210 eventq_index=0
211
212 [system.cpu.workload]
213 type=LiveProcess
214 cmd=hello
215 cwd=
216 egid=100
217 env=
218 errout=cerr
219 euid=100
220 eventq_index=0
221 executable=/dist/test-progs/hello/bin/alpha/tru64/hello
222 gid=100
223 input=cin
224 max_stack_size=67108864
225 output=cout
226 pid=100
227 ppid=99
228 simpoint=0
229 system=system
230 uid=100
231
232 [system.cpu_clk_domain]
233 type=SrcClockDomain
234 clock=500
235 eventq_index=0
236 voltage_domain=system.voltage_domain
237
238 [system.membus]
239 type=CoherentBus
240 clk_domain=system.clk_domain
241 eventq_index=0
242 header_cycles=1
243 system=system
244 use_default_range=false
245 width=8
246 master=system.physmem.port
247 slave=system.system_port system.cpu.l2cache.mem_side
248
249 [system.physmem]
250 type=SimpleMemory
251 bandwidth=73.000000
252 clk_domain=system.clk_domain
253 conf_table_reported=true
254 eventq_index=0
255 in_addr_map=true
256 latency=30000
257 latency_var=0
258 null=false
259 range=0:134217727
260 port=system.membus.master[0]
261
262 [system.voltage_domain]
263 type=VoltageDomain
264 eventq_index=0
265 voltage=1.000000
266