2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000018 # Number of seconds simulated
4 sim_ticks 18239500 # Number of ticks simulated
5 final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 339288 # Simulator instruction rate (inst/s)
8 host_op_rate 338780 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2394585777 # Simulator tick rate (ticks/s)
10 host_mem_usage 246188 # Number of bytes of host memory used
11 host_seconds 0.01 # Real time elapsed on the host
12 sim_insts 2577 # Number of instructions simulated
13 sim_ops 2577 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s)
32 system.cpu_clk_domain.clock 500 # Clock period in ticks
33 system.cpu.dtb.fetch_hits 0 # ITB hits
34 system.cpu.dtb.fetch_misses 0 # ITB misses
35 system.cpu.dtb.fetch_acv 0 # ITB acv
36 system.cpu.dtb.fetch_accesses 0 # ITB accesses
37 system.cpu.dtb.read_hits 415 # DTB read hits
38 system.cpu.dtb.read_misses 4 # DTB read misses
39 system.cpu.dtb.read_acv 0 # DTB read access violations
40 system.cpu.dtb.read_accesses 419 # DTB read accesses
41 system.cpu.dtb.write_hits 294 # DTB write hits
42 system.cpu.dtb.write_misses 4 # DTB write misses
43 system.cpu.dtb.write_acv 0 # DTB write access violations
44 system.cpu.dtb.write_accesses 298 # DTB write accesses
45 system.cpu.dtb.data_hits 709 # DTB hits
46 system.cpu.dtb.data_misses 8 # DTB misses
47 system.cpu.dtb.data_acv 0 # DTB access violations
48 system.cpu.dtb.data_accesses 717 # DTB accesses
49 system.cpu.itb.fetch_hits 2586 # ITB hits
50 system.cpu.itb.fetch_misses 11 # ITB misses
51 system.cpu.itb.fetch_acv 0 # ITB acv
52 system.cpu.itb.fetch_accesses 2597 # ITB accesses
53 system.cpu.itb.read_hits 0 # DTB read hits
54 system.cpu.itb.read_misses 0 # DTB read misses
55 system.cpu.itb.read_acv 0 # DTB read access violations
56 system.cpu.itb.read_accesses 0 # DTB read accesses
57 system.cpu.itb.write_hits 0 # DTB write hits
58 system.cpu.itb.write_misses 0 # DTB write misses
59 system.cpu.itb.write_acv 0 # DTB write access violations
60 system.cpu.itb.write_accesses 0 # DTB write accesses
61 system.cpu.itb.data_hits 0 # DTB hits
62 system.cpu.itb.data_misses 0 # DTB misses
63 system.cpu.itb.data_acv 0 # DTB access violations
64 system.cpu.itb.data_accesses 0 # DTB accesses
65 system.cpu.workload.num_syscalls 4 # Number of system calls
66 system.cpu.numCycles 36479 # number of cpu cycles simulated
67 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69 system.cpu.committedInsts 2577 # Number of instructions committed
70 system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
71 system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
72 system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
73 system.cpu.num_func_calls 140 # number of times a function call or return occured
74 system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
75 system.cpu.num_int_insts 2375 # number of integer instructions
76 system.cpu.num_fp_insts 6 # number of float instructions
77 system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
78 system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
79 system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
80 system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
81 system.cpu.num_mem_refs 717 # number of memory refs
82 system.cpu.num_load_insts 419 # Number of load instructions
83 system.cpu.num_store_insts 298 # Number of store instructions
84 system.cpu.num_idle_cycles 0 # Number of idle cycles
85 system.cpu.num_busy_cycles 36479 # Number of busy cycles
86 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
87 system.cpu.idle_fraction 0 # Percentage of idle cycles
88 system.cpu.Branches 396 # Number of branches fetched
89 system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
90 system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
91 system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
92 system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
93 system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
94 system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
95 system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
96 system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
97 system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
98 system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
99 system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
100 system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
101 system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
102 system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
103 system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
104 system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
105 system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
106 system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
107 system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
108 system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
109 system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
110 system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
111 system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
112 system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
113 system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
114 system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
115 system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
116 system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
117 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
118 system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
119 system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
120 system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
121 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
122 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
123 system.cpu.op_class::total 2585 # Class of executed instruction
124 system.cpu.dcache.tags.replacements 0 # number of replacements
125 system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use
126 system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
127 system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
128 system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
129 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
130 system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor
131 system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy
132 system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy
133 system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
134 system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
135 system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
136 system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
137 system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
138 system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
139 system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
140 system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
141 system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
142 system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
143 system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
144 system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
145 system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
146 system.cpu.dcache.overall_hits::total 627 # number of overall hits
147 system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
148 system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
149 system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
150 system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
151 system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
152 system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
153 system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
154 system.cpu.dcache.overall_misses::total 82 # number of overall misses
155 system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
156 system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
157 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles
158 system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles
159 system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles
160 system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles
161 system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles
162 system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles
163 system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
164 system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
165 system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
166 system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
167 system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
168 system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
169 system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
170 system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
171 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
172 system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
173 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
174 system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
175 system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
176 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
177 system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
178 system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
179 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
180 system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
181 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
182 system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
183 system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
184 system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
185 system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
186 system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
187 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
188 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
189 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
190 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
191 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
192 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
193 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
194 system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
195 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
196 system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
197 system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
198 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
199 system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
200 system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
201 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
202 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
203 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles
204 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles
205 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles
206 system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles
207 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles
208 system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles
209 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
210 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
211 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
212 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
213 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
214 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
215 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
216 system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
217 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
218 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
219 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
220 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
221 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
222 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
223 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
224 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
225 system.cpu.icache.tags.replacements 0 # number of replacements
226 system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use
227 system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
228 system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
229 system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
230 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
231 system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor
232 system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy
233 system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy
234 system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
235 system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
236 system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
237 system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
238 system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
239 system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
240 system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
241 system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
242 system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
243 system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
244 system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
245 system.cpu.icache.overall_hits::total 2423 # number of overall hits
246 system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
247 system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
248 system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
249 system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
250 system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
251 system.cpu.icache.overall_misses::total 163 # number of overall misses
252 system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles
253 system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles
254 system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles
255 system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles
256 system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles
257 system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles
258 system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
259 system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
260 system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
261 system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
262 system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
263 system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
264 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
265 system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
266 system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
267 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
268 system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
269 system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
270 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency
271 system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency
272 system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
273 system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency
274 system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
275 system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency
276 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
277 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
278 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
279 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
280 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
281 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
282 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
283 system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
284 system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
285 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
286 system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
287 system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
288 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles
289 system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles
290 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles
291 system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles
292 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles
293 system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles
294 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
295 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
296 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
297 system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
298 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
299 system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
300 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency
301 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency
302 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
303 system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
304 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
305 system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
306 system.cpu.l2cache.tags.replacements 0 # number of replacements
307 system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use
308 system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
309 system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
310 system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
311 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
312 system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor
313 system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor
314 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy
315 system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy
316 system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy
317 system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
318 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
319 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
320 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
321 system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
322 system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
323 system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
324 system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
325 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses
326 system.cpu.l2cache.ReadCleanReq_misses::total 163 # number of ReadCleanReq misses
327 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses
328 system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses
329 system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
330 system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
331 system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
332 system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
333 system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
334 system.cpu.l2cache.overall_misses::total 245 # number of overall misses
335 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles
336 system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles
337 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles
338 system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles
339 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
340 system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
341 system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles
342 system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles
343 system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles
344 system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles
345 system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles
346 system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles
347 system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
348 system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
349 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses)
350 system.cpu.l2cache.ReadCleanReq_accesses::total 163 # number of ReadCleanReq accesses(hits+misses)
351 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses)
352 system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses)
353 system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
354 system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
355 system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
356 system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
357 system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
358 system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
359 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
360 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
361 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
362 system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
363 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
364 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
365 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
366 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
367 system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
368 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
369 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
370 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
371 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
372 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
373 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency
374 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency
375 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
376 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
377 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
378 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
379 system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency
380 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
381 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
382 system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency
383 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
386 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
387 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
390 system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
391 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses
392 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 163 # number of ReadCleanReq MSHR misses
393 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses
394 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses
395 system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
396 system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
397 system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
398 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
399 system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
400 system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
401 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles
402 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles
403 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles
404 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles
405 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
406 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
407 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles
408 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles
409 system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles
410 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles
411 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles
412 system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles
413 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
414 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
415 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
416 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
417 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
418 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
419 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
420 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
421 system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
422 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
423 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
424 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
425 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
426 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
427 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency
428 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency
429 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
430 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
431 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
432 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
433 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
434 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
435 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
436 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
437 system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
438 system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
439 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
440 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
441 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
442 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
443 system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
444 system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
445 system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
446 system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution
447 system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution
448 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes)
449 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes)
450 system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
451 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes)
452 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes)
453 system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
454 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
455 system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram
456 system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
457 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
458 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
459 system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
460 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
461 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
462 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
463 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
464 system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
465 system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram
466 system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
467 system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
468 system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
469 system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
470 system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
471 system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
472 system.membus.trans_dist::ReadResp 218 # Transaction distribution
473 system.membus.trans_dist::ReadExReq 27 # Transaction distribution
474 system.membus.trans_dist::ReadExResp 27 # Transaction distribution
475 system.membus.trans_dist::ReadSharedReq 218 # Transaction distribution
476 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
477 system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
478 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
479 system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
480 system.membus.snoops 0 # Total snoops (count)
481 system.membus.snoop_fanout::samples 245 # Request fanout histogram
482 system.membus.snoop_fanout::mean 0 # Request fanout histogram
483 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
484 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
485 system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
486 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
487 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
488 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
489 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
490 system.membus.snoop_fanout::total 245 # Request fanout histogram
491 system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
492 system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
493 system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks)
494 system.membus.respLayer1.utilization 6.7 # Layer utilization (%)
496 ---------- End Simulation Statistics ----------
projects / gem5.git / blob