tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 multi_thread=false
  28 num_work_ids=16
  29 readfile=
  30 symbolfile=
  31 work_begin_ckpt_count=0
  32 work_begin_cpu_id_exit=-1
  33 work_begin_exit_count=0
  34 work_cpus_ckpt_count=0
  35 work_end_ckpt_count=0
  36 work_end_exit_count=0
  37 work_item_id=-1
  38 system_port=system.membus.slave[0]
  39
  40 [system.clk_domain]
  41 type=SrcClockDomain
  42 clock=1000
  43 domain_id=-1
  44 eventq_index=0
  45 init_perf_level=0
  46 voltage_domain=system.voltage_domain
  47
  48 [system.cpu]
  49 type=MinorCPU
  50 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  51 branchPred=system.cpu.branchPred
  52 checker=Null
  53 clk_domain=system.cpu_clk_domain
  54 cpu_id=0
  55 decodeCycleInput=true
  56 decodeInputBufferSize=3
  57 decodeInputWidth=2
  58 decodeToExecuteForwardDelay=1
  59 do_checkpoint_insts=true
  60 do_quiesce=true
  61 do_statistics_insts=true
  62 dstage2_mmu=system.cpu.dstage2_mmu
  63 dtb=system.cpu.dtb
  64 enableIdling=true
  65 eventq_index=0
  66 executeAllowEarlyMemoryIssue=true
  67 executeBranchDelay=1
  68 executeCommitLimit=2
  69 executeCycleInput=true
  70 executeFuncUnits=system.cpu.executeFuncUnits
  71 executeInputBufferSize=7
  72 executeInputWidth=2
  73 executeIssueLimit=2
  74 executeLSQMaxStoreBufferStoresPerCycle=2
  75 executeLSQRequestsQueueSize=1
  76 executeLSQStoreBufferSize=5
  77 executeLSQTransfersQueueSize=2
  78 executeMaxAccessesInMemory=2
  79 executeMemoryCommitLimit=1
  80 executeMemoryIssueLimit=1
  81 executeMemoryWidth=0
  82 executeSetTraceTimeOnCommit=true
  83 executeSetTraceTimeOnIssue=false
  84 fetch1FetchLimit=1
  85 fetch1LineSnapWidth=0
  86 fetch1LineWidth=0
  87 fetch1ToFetch2BackwardDelay=1
  88 fetch1ToFetch2ForwardDelay=1
  89 fetch2CycleInput=true
  90 fetch2InputBufferSize=2
  91 fetch2ToDecodeForwardDelay=1
  92 function_trace=false
  93 function_trace_start=0
  94 interrupts=system.cpu.interrupts
  95 isa=system.cpu.isa
  96 istage2_mmu=system.cpu.istage2_mmu
  97 itb=system.cpu.itb
  98 max_insts_all_threads=0
  99 max_insts_any_thread=0
 100 max_loads_all_threads=0
 101 max_loads_any_thread=0
 102 numThreads=1
 103 profile=0
 104 progress_interval=0
 105 simpoint_start_insts=
 106 socket_id=0
 107 switched_out=false
 108 system=system
 109 tracer=system.cpu.tracer
 110 workload=system.cpu.workload
 111 dcache_port=system.cpu.dcache.cpu_side
 112 icache_port=system.cpu.icache.cpu_side
 113
 114 [system.cpu.branchPred]
 115 type=TournamentBP
 116 BTBEntries=4096
 117 BTBTagSize=16
 118 RASSize=16
 119 choiceCtrBits=2
 120 choicePredictorSize=8192
 121 eventq_index=0
 122 globalCtrBits=2
 123 globalPredictorSize=8192
 124 instShiftAmt=2
 125 localCtrBits=2
 126 localHistoryTableSize=2048
 127 localPredictorSize=2048
 128 numThreads=1
 129
 130 [system.cpu.dcache]
 131 type=Cache
 132 children=tags
 133 addr_ranges=0:18446744073709551615
 134 assoc=2
 135 clk_domain=system.cpu_clk_domain
 136 clusivity=mostly_incl
 137 demand_mshr_reserve=1
 138 eventq_index=0
 139 forward_snoops=true
 140 hit_latency=2
 141 is_read_only=false
 142 max_miss_count=0
 143 mshrs=4
 144 prefetch_on_access=false
 145 prefetcher=Null
 146 response_latency=2
 147 sequential_access=false
 148 size=262144
 149 system=system
 150 tags=system.cpu.dcache.tags
 151 tgts_per_mshr=20
 152 write_buffers=8
 153 writeback_clean=false
 154 cpu_side=system.cpu.dcache_port
 155 mem_side=system.cpu.toL2Bus.slave[1]
 156
 157 [system.cpu.dcache.tags]
 158 type=LRU
 159 assoc=2
 160 block_size=64
 161 clk_domain=system.cpu_clk_domain
 162 eventq_index=0
 163 hit_latency=2
 164 sequential_access=false
 165 size=262144
 166
 167 [system.cpu.dstage2_mmu]
 168 type=ArmStage2MMU
 169 children=stage2_tlb
 170 eventq_index=0
 171 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 172 sys=system
 173 tlb=system.cpu.dtb
 174
 175 [system.cpu.dstage2_mmu.stage2_tlb]
 176 type=ArmTLB
 177 children=walker
 178 eventq_index=0
 179 is_stage2=true
 180 size=32
 181 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 182
 183 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 184 type=ArmTableWalker
 185 clk_domain=system.cpu_clk_domain
 186 eventq_index=0
 187 is_stage2=true
 188 num_squash_per_cycle=2
 189 sys=system
 190
 191 [system.cpu.dtb]
 192 type=ArmTLB
 193 children=walker
 194 eventq_index=0
 195 is_stage2=false
 196 size=64
 197 walker=system.cpu.dtb.walker
 198
 199 [system.cpu.dtb.walker]
 200 type=ArmTableWalker
 201 clk_domain=system.cpu_clk_domain
 202 eventq_index=0
 203 is_stage2=false
 204 num_squash_per_cycle=2
 205 sys=system
 206 port=system.cpu.toL2Bus.slave[3]
 207
 208 [system.cpu.executeFuncUnits]
 209 type=MinorFUPool
 210 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 211 eventq_index=0
 212 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 213
 214 [system.cpu.executeFuncUnits.funcUnits0]
 215 type=MinorFU
 216 children=opClasses timings
 217 cantForwardFromFUIndices=
 218 eventq_index=0
 219 issueLat=1
 220 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 221 opLat=3
 222 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 223
 224 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 225 type=MinorOpClassSet
 226 children=opClasses
 227 eventq_index=0
 228 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 229
 230 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 231 type=MinorOpClass
 232 eventq_index=0
 233 opClass=IntAlu
 234
 235 [system.cpu.executeFuncUnits.funcUnits0.timings]
 236 type=MinorFUTiming
 237 children=opClasses
 238 description=Int
 239 eventq_index=0
 240 extraAssumedLat=0
 241 extraCommitLat=0
 242 extraCommitLatExpr=Null
 243 mask=0
 244 match=0
 245 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 246 srcRegsRelativeLats=2
 247 suppress=false
 248
 249 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 250 type=MinorOpClassSet
 251 eventq_index=0
 252 opClasses=
 253
 254 [system.cpu.executeFuncUnits.funcUnits1]
 255 type=MinorFU
 256 children=opClasses timings
 257 cantForwardFromFUIndices=
 258 eventq_index=0
 259 issueLat=1
 260 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 261 opLat=3
 262 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 263
 264 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 265 type=MinorOpClassSet
 266 children=opClasses
 267 eventq_index=0
 268 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 269
 270 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 271 type=MinorOpClass
 272 eventq_index=0
 273 opClass=IntAlu
 274
 275 [system.cpu.executeFuncUnits.funcUnits1.timings]
 276 type=MinorFUTiming
 277 children=opClasses
 278 description=Int
 279 eventq_index=0
 280 extraAssumedLat=0
 281 extraCommitLat=0
 282 extraCommitLatExpr=Null
 283 mask=0
 284 match=0
 285 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 286 srcRegsRelativeLats=2
 287 suppress=false
 288
 289 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 290 type=MinorOpClassSet
 291 eventq_index=0
 292 opClasses=
 293
 294 [system.cpu.executeFuncUnits.funcUnits2]
 295 type=MinorFU
 296 children=opClasses timings
 297 cantForwardFromFUIndices=
 298 eventq_index=0
 299 issueLat=1
 300 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 301 opLat=3
 302 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 303
 304 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 305 type=MinorOpClassSet
 306 children=opClasses
 307 eventq_index=0
 308 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 309
 310 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 311 type=MinorOpClass
 312 eventq_index=0
 313 opClass=IntMult
 314
 315 [system.cpu.executeFuncUnits.funcUnits2.timings]
 316 type=MinorFUTiming
 317 children=opClasses
 318 description=Mul
 319 eventq_index=0
 320 extraAssumedLat=0
 321 extraCommitLat=0
 322 extraCommitLatExpr=Null
 323 mask=0
 324 match=0
 325 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 326 srcRegsRelativeLats=0
 327 suppress=false
 328
 329 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 330 type=MinorOpClassSet
 331 eventq_index=0
 332 opClasses=
 333
 334 [system.cpu.executeFuncUnits.funcUnits3]
 335 type=MinorFU
 336 children=opClasses
 337 cantForwardFromFUIndices=
 338 eventq_index=0
 339 issueLat=9
 340 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 341 opLat=9
 342 timings=
 343
 344 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 345 type=MinorOpClassSet
 346 children=opClasses
 347 eventq_index=0
 348 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 349
 350 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 351 type=MinorOpClass
 352 eventq_index=0
 353 opClass=IntDiv
 354
 355 [system.cpu.executeFuncUnits.funcUnits4]
 356 type=MinorFU
 357 children=opClasses timings
 358 cantForwardFromFUIndices=
 359 eventq_index=0
 360 issueLat=1
 361 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 362 opLat=6
 363 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 364
 365 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 366 type=MinorOpClassSet
 367 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 368 eventq_index=0
 369 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 370
 371 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 372 type=MinorOpClass
 373 eventq_index=0
 374 opClass=FloatAdd
 375
 376 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 377 type=MinorOpClass
 378 eventq_index=0
 379 opClass=FloatCmp
 380
 381 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 382 type=MinorOpClass
 383 eventq_index=0
 384 opClass=FloatCvt
 385
 386 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 387 type=MinorOpClass
 388 eventq_index=0
 389 opClass=FloatMult
 390
 391 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 392 type=MinorOpClass
 393 eventq_index=0
 394 opClass=FloatDiv
 395
 396 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 397 type=MinorOpClass
 398 eventq_index=0
 399 opClass=FloatSqrt
 400
 401 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 402 type=MinorOpClass
 403 eventq_index=0
 404 opClass=SimdAdd
 405
 406 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 407 type=MinorOpClass
 408 eventq_index=0
 409 opClass=SimdAddAcc
 410
 411 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 412 type=MinorOpClass
 413 eventq_index=0
 414 opClass=SimdAlu
 415
 416 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 417 type=MinorOpClass
 418 eventq_index=0
 419 opClass=SimdCmp
 420
 421 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 422 type=MinorOpClass
 423 eventq_index=0
 424 opClass=SimdCvt
 425
 426 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 427 type=MinorOpClass
 428 eventq_index=0
 429 opClass=SimdMisc
 430
 431 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 432 type=MinorOpClass
 433 eventq_index=0
 434 opClass=SimdMult
 435
 436 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 437 type=MinorOpClass
 438 eventq_index=0
 439 opClass=SimdMultAcc
 440
 441 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 442 type=MinorOpClass
 443 eventq_index=0
 444 opClass=SimdShift
 445
 446 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 447 type=MinorOpClass
 448 eventq_index=0
 449 opClass=SimdShiftAcc
 450
 451 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 452 type=MinorOpClass
 453 eventq_index=0
 454 opClass=SimdSqrt
 455
 456 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 457 type=MinorOpClass
 458 eventq_index=0
 459 opClass=SimdFloatAdd
 460
 461 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 462 type=MinorOpClass
 463 eventq_index=0
 464 opClass=SimdFloatAlu
 465
 466 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 467 type=MinorOpClass
 468 eventq_index=0
 469 opClass=SimdFloatCmp
 470
 471 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 472 type=MinorOpClass
 473 eventq_index=0
 474 opClass=SimdFloatCvt
 475
 476 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 477 type=MinorOpClass
 478 eventq_index=0
 479 opClass=SimdFloatDiv
 480
 481 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 482 type=MinorOpClass
 483 eventq_index=0
 484 opClass=SimdFloatMisc
 485
 486 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 487 type=MinorOpClass
 488 eventq_index=0
 489 opClass=SimdFloatMult
 490
 491 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 492 type=MinorOpClass
 493 eventq_index=0
 494 opClass=SimdFloatMultAcc
 495
 496 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 497 type=MinorOpClass
 498 eventq_index=0
 499 opClass=SimdFloatSqrt
 500
 501 [system.cpu.executeFuncUnits.funcUnits4.timings]
 502 type=MinorFUTiming
 503 children=opClasses
 504 description=FloatSimd
 505 eventq_index=0
 506 extraAssumedLat=0
 507 extraCommitLat=0
 508 extraCommitLatExpr=Null
 509 mask=0
 510 match=0
 511 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 512 srcRegsRelativeLats=2
 513 suppress=false
 514
 515 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 516 type=MinorOpClassSet
 517 eventq_index=0
 518 opClasses=
 519
 520 [system.cpu.executeFuncUnits.funcUnits5]
 521 type=MinorFU
 522 children=opClasses timings
 523 cantForwardFromFUIndices=
 524 eventq_index=0
 525 issueLat=1
 526 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 527 opLat=1
 528 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 529
 530 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 531 type=MinorOpClassSet
 532 children=opClasses0 opClasses1
 533 eventq_index=0
 534 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 535
 536 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 537 type=MinorOpClass
 538 eventq_index=0
 539 opClass=MemRead
 540
 541 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 542 type=MinorOpClass
 543 eventq_index=0
 544 opClass=MemWrite
 545
 546 [system.cpu.executeFuncUnits.funcUnits5.timings]
 547 type=MinorFUTiming
 548 children=opClasses
 549 description=Mem
 550 eventq_index=0
 551 extraAssumedLat=2
 552 extraCommitLat=0
 553 extraCommitLatExpr=Null
 554 mask=0
 555 match=0
 556 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 557 srcRegsRelativeLats=1
 558 suppress=false
 559
 560 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 561 type=MinorOpClassSet
 562 eventq_index=0
 563 opClasses=
 564
 565 [system.cpu.executeFuncUnits.funcUnits6]
 566 type=MinorFU
 567 children=opClasses
 568 cantForwardFromFUIndices=
 569 eventq_index=0
 570 issueLat=1
 571 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 572 opLat=1
 573 timings=
 574
 575 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 576 type=MinorOpClassSet
 577 children=opClasses0 opClasses1
 578 eventq_index=0
 579 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 580
 581 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 582 type=MinorOpClass
 583 eventq_index=0
 584 opClass=IprAccess
 585
 586 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 587 type=MinorOpClass
 588 eventq_index=0
 589 opClass=InstPrefetch
 590
 591 [system.cpu.icache]
 592 type=Cache
 593 children=tags
 594 addr_ranges=0:18446744073709551615
 595 assoc=2
 596 clk_domain=system.cpu_clk_domain
 597 clusivity=mostly_incl
 598 demand_mshr_reserve=1
 599 eventq_index=0
 600 forward_snoops=true
 601 hit_latency=2
 602 is_read_only=true
 603 max_miss_count=0
 604 mshrs=4
 605 prefetch_on_access=false
 606 prefetcher=Null
 607 response_latency=2
 608 sequential_access=false
 609 size=131072
 610 system=system
 611 tags=system.cpu.icache.tags
 612 tgts_per_mshr=20
 613 write_buffers=8
 614 writeback_clean=true
 615 cpu_side=system.cpu.icache_port
 616 mem_side=system.cpu.toL2Bus.slave[0]
 617
 618 [system.cpu.icache.tags]
 619 type=LRU
 620 assoc=2
 621 block_size=64
 622 clk_domain=system.cpu_clk_domain
 623 eventq_index=0
 624 hit_latency=2
 625 sequential_access=false
 626 size=131072
 627
 628 [system.cpu.interrupts]
 629 type=ArmInterrupts
 630 eventq_index=0
 631
 632 [system.cpu.isa]
 633 type=ArmISA
 634 decoderFlavour=Generic
 635 eventq_index=0
 636 fpsid=1090793632
 637 id_aa64afr0_el1=0
 638 id_aa64afr1_el1=0
 639 id_aa64dfr0_el1=1052678
 640 id_aa64dfr1_el1=0
 641 id_aa64isar0_el1=0
 642 id_aa64isar1_el1=0
 643 id_aa64mmfr0_el1=15728642
 644 id_aa64mmfr1_el1=0
 645 id_aa64pfr0_el1=17
 646 id_aa64pfr1_el1=0
 647 id_isar0=34607377
 648 id_isar1=34677009
 649 id_isar2=555950401
 650 id_isar3=17899825
 651 id_isar4=268501314
 652 id_isar5=0
 653 id_mmfr0=270536963
 654 id_mmfr1=0
 655 id_mmfr2=19070976
 656 id_mmfr3=34611729
 657 id_pfr0=49
 658 id_pfr1=4113
 659 midr=1091551472
 660 pmu=Null
 661 system=system
 662
 663 [system.cpu.istage2_mmu]
 664 type=ArmStage2MMU
 665 children=stage2_tlb
 666 eventq_index=0
 667 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 668 sys=system
 669 tlb=system.cpu.itb
 670
 671 [system.cpu.istage2_mmu.stage2_tlb]
 672 type=ArmTLB
 673 children=walker
 674 eventq_index=0
 675 is_stage2=true
 676 size=32
 677 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 678
 679 [system.cpu.istage2_mmu.stage2_tlb.walker]
 680 type=ArmTableWalker
 681 clk_domain=system.cpu_clk_domain
 682 eventq_index=0
 683 is_stage2=true
 684 num_squash_per_cycle=2
 685 sys=system
 686
 687 [system.cpu.itb]
 688 type=ArmTLB
 689 children=walker
 690 eventq_index=0
 691 is_stage2=false
 692 size=64
 693 walker=system.cpu.itb.walker
 694
 695 [system.cpu.itb.walker]
 696 type=ArmTableWalker
 697 clk_domain=system.cpu_clk_domain
 698 eventq_index=0
 699 is_stage2=false
 700 num_squash_per_cycle=2
 701 sys=system
 702 port=system.cpu.toL2Bus.slave[2]
 703
 704 [system.cpu.l2cache]
 705 type=Cache
 706 children=tags
 707 addr_ranges=0:18446744073709551615
 708 assoc=8
 709 clk_domain=system.cpu_clk_domain
 710 clusivity=mostly_incl
 711 demand_mshr_reserve=1
 712 eventq_index=0
 713 forward_snoops=true
 714 hit_latency=20
 715 is_read_only=false
 716 max_miss_count=0
 717 mshrs=20
 718 prefetch_on_access=false
 719 prefetcher=Null
 720 response_latency=20
 721 sequential_access=false
 722 size=2097152
 723 system=system
 724 tags=system.cpu.l2cache.tags
 725 tgts_per_mshr=12
 726 write_buffers=8
 727 writeback_clean=false
 728 cpu_side=system.cpu.toL2Bus.master[0]
 729 mem_side=system.membus.slave[1]
 730
 731 [system.cpu.l2cache.tags]
 732 type=LRU
 733 assoc=8
 734 block_size=64
 735 clk_domain=system.cpu_clk_domain
 736 eventq_index=0
 737 hit_latency=20
 738 sequential_access=false
 739 size=2097152
 740
 741 [system.cpu.toL2Bus]
 742 type=CoherentXBar
 743 children=snoop_filter
 744 clk_domain=system.cpu_clk_domain
 745 eventq_index=0
 746 forward_latency=0
 747 frontend_latency=1
 748 response_latency=1
 749 snoop_filter=system.cpu.toL2Bus.snoop_filter
 750 snoop_response_latency=1
 751 system=system
 752 use_default_range=false
 753 width=32
 754 master=system.cpu.l2cache.cpu_side
 755 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 756
 757 [system.cpu.toL2Bus.snoop_filter]
 758 type=SnoopFilter
 759 eventq_index=0
 760 lookup_latency=0
 761 max_capacity=8388608
 762 system=system
 763
 764 [system.cpu.tracer]
 765 type=ExeTracer
 766 eventq_index=0
 767
 768 [system.cpu.workload]
 769 type=LiveProcess
 770 cmd=hello
 771 cwd=
 772 drivers=
 773 egid=100
 774 env=
 775 errout=cerr
 776 euid=100
 777 eventq_index=0
 778 executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 779 gid=100
 780 input=cin
 781 kvmInSE=false
 782 max_stack_size=67108864
 783 output=cout
 784 pid=100
 785 ppid=99
 786 simpoint=0
 787 system=system
 788 uid=100
 789 useArchPT=false
 790
 791 [system.cpu_clk_domain]
 792 type=SrcClockDomain
 793 clock=500
 794 domain_id=-1
 795 eventq_index=0
 796 init_perf_level=0
 797 voltage_domain=system.voltage_domain
 798
 799 [system.dvfs_handler]
 800 type=DVFSHandler
 801 domains=
 802 enable=false
 803 eventq_index=0
 804 sys_clk_domain=system.clk_domain
 805 transition_latency=100000000
 806
 807 [system.membus]
 808 type=CoherentXBar
 809 clk_domain=system.clk_domain
 810 eventq_index=0
 811 forward_latency=4
 812 frontend_latency=3
 813 response_latency=2
 814 snoop_filter=Null
 815 snoop_response_latency=4
 816 system=system
 817 use_default_range=false
 818 width=16
 819 master=system.physmem.port
 820 slave=system.system_port system.cpu.l2cache.mem_side
 821
 822 [system.physmem]
 823 type=DRAMCtrl
 824 IDD0=0.075000
 825 IDD02=0.000000
 826 IDD2N=0.050000
 827 IDD2N2=0.000000
 828 IDD2P0=0.000000
 829 IDD2P02=0.000000
 830 IDD2P1=0.000000
 831 IDD2P12=0.000000
 832 IDD3N=0.057000
 833 IDD3N2=0.000000
 834 IDD3P0=0.000000
 835 IDD3P02=0.000000
 836 IDD3P1=0.000000
 837 IDD3P12=0.000000
 838 IDD4R=0.187000
 839 IDD4R2=0.000000
 840 IDD4W=0.165000
 841 IDD4W2=0.000000
 842 IDD5=0.220000
 843 IDD52=0.000000
 844 IDD6=0.000000
 845 IDD62=0.000000
 846 VDD=1.500000
 847 VDD2=0.000000
 848 activation_limit=4
 849 addr_mapping=RoRaBaCoCh
 850 bank_groups_per_rank=0
 851 banks_per_rank=8
 852 burst_length=8
 853 channels=1
 854 clk_domain=system.clk_domain
 855 conf_table_reported=true
 856 device_bus_width=8
 857 device_rowbuffer_size=1024
 858 device_size=536870912
 859 devices_per_rank=8
 860 dll=true
 861 eventq_index=0
 862 in_addr_map=true
 863 max_accesses_per_row=16
 864 mem_sched_policy=frfcfs
 865 min_writes_per_switch=16
 866 null=false
 867 page_policy=open_adaptive
 868 range=0:134217727
 869 ranks_per_channel=2
 870 read_buffer_size=32
 871 static_backend_latency=10000
 872 static_frontend_latency=10000
 873 tBURST=5000
 874 tCCD_L=0
 875 tCK=1250
 876 tCL=13750
 877 tCS=2500
 878 tRAS=35000
 879 tRCD=13750
 880 tREFI=7800000
 881 tRFC=260000
 882 tRP=13750
 883 tRRD=6000
 884 tRRD_L=0
 885 tRTP=7500
 886 tRTW=2500
 887 tWR=15000
 888 tWTR=7500
 889 tXAW=30000
 890 tXP=0
 891 tXPDLL=0
 892 tXS=0
 893 tXSDLL=0
 894 write_buffer_size=64
 895 write_high_thresh_perc=85
 896 write_low_thresh_perc=50
 897 port=system.membus.master[0]
 898
 899 [system.voltage_domain]
 900 type=VoltageDomain
 901 eventq_index=0
 902 voltage=1.000000
 903