2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000028 # Number of seconds simulated
4 sim_ticks 27911000 # Number of ticks simulated
5 final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 3437 # Simulator instruction rate (inst/s)
8 host_op_rate 4023 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 20833659 # Simulator tick rate (ticks/s)
10 host_mem_usage 251612 # Number of bytes of host memory used
11 host_seconds 1.34 # Real time elapsed on the host
12 sim_insts 4604 # Number of instructions simulated
13 sim_ops 5390 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
17 system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
18 system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
19 system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
20 system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s)
27 system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.readReqs 420 # Number of read requests accepted
29 system.physmem.writeReqs 0 # Number of write requests accepted
30 system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
31 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32 system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
33 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35 system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
36 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40 system.physmem.perBankRdBursts::0 91 # Per bank write bursts
41 system.physmem.perBankRdBursts::1 51 # Per bank write bursts
42 system.physmem.perBankRdBursts::2 20 # Per bank write bursts
43 system.physmem.perBankRdBursts::3 42 # Per bank write bursts
44 system.physmem.perBankRdBursts::4 23 # Per bank write bursts
45 system.physmem.perBankRdBursts::5 41 # Per bank write bursts
46 system.physmem.perBankRdBursts::6 36 # Per bank write bursts
47 system.physmem.perBankRdBursts::7 12 # Per bank write bursts
48 system.physmem.perBankRdBursts::8 5 # Per bank write bursts
49 system.physmem.perBankRdBursts::9 6 # Per bank write bursts
50 system.physmem.perBankRdBursts::10 27 # Per bank write bursts
51 system.physmem.perBankRdBursts::11 42 # Per bank write bursts
52 system.physmem.perBankRdBursts::12 9 # Per bank write bursts
53 system.physmem.perBankRdBursts::13 8 # Per bank write bursts
54 system.physmem.perBankRdBursts::14 0 # Per bank write bursts
55 system.physmem.perBankRdBursts::15 7 # Per bank write bursts
56 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74 system.physmem.totGap 27825500 # Total gap between requests
75 system.physmem.readPktSize::0 0 # Read request sizes (log2)
76 system.physmem.readPktSize::1 0 # Read request sizes (log2)
77 system.physmem.readPktSize::2 0 # Read request sizes (log2)
78 system.physmem.readPktSize::3 0 # Read request sizes (log2)
79 system.physmem.readPktSize::4 0 # Read request sizes (log2)
80 system.physmem.readPktSize::5 0 # Read request sizes (log2)
81 system.physmem.readPktSize::6 420 # Read request sizes (log2)
82 system.physmem.writePktSize::0 0 # Write request sizes (log2)
83 system.physmem.writePktSize::1 0 # Write request sizes (log2)
84 system.physmem.writePktSize::2 0 # Write request sizes (log2)
85 system.physmem.writePktSize::3 0 # Write request sizes (log2)
86 system.physmem.writePktSize::4 0 # Write request sizes (log2)
87 system.physmem.writePktSize::5 0 # Write request sizes (log2)
88 system.physmem.writePktSize::6 0 # Write request sizes (log2)
89 system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
90 system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
91 system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
92 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
121 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
122 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
123 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
124 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
125 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185 system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
198 system.physmem.totQLat 2575500 # Total ticks spent queuing
199 system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
200 system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
201 system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
202 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
203 system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
204 system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
205 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
206 system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
207 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
208 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
209 system.physmem.busUtil 7.52 # Data bus utilization in percentage
210 system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
211 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
212 system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
213 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
214 system.physmem.readRowHits 348 # Number of row buffer hits during reads
215 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
216 system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
217 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
218 system.physmem.avgGap 66251.19 # Average gap between requests
219 system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined
220 system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
221 system.physmem.memoryStateTime::REF 780000 # Time in different power states
222 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
223 system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
224 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
225 system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ)
226 system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ)
227 system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ)
228 system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ)
229 system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ)
230 system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ)
231 system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
232 system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
233 system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ)
234 system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ)
235 system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ)
236 system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ)
237 system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ)
238 system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ)
239 system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ)
240 system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ)
241 system.physmem.averagePower::0 856.166817 # Core power per rank (mW)
242 system.physmem.averagePower::1 786.636676 # Core power per rank (mW)
243 system.membus.trans_dist::ReadReq 377 # Transaction distribution
244 system.membus.trans_dist::ReadResp 377 # Transaction distribution
245 system.membus.trans_dist::ReadExReq 43 # Transaction distribution
246 system.membus.trans_dist::ReadExResp 43 # Transaction distribution
247 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
248 system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
249 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
250 system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
251 system.membus.snoops 0 # Total snoops (count)
252 system.membus.snoop_fanout::samples 420 # Request fanout histogram
253 system.membus.snoop_fanout::mean 0 # Request fanout histogram
254 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
255 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
256 system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
257 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
258 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
259 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
260 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
261 system.membus.snoop_fanout::total 420 # Request fanout histogram
262 system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
263 system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
264 system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
265 system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
266 system.cpu_clk_domain.clock 500 # Clock period in ticks
267 system.cpu.branchPred.lookups 1903 # Number of BP lookups
268 system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
269 system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
270 system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
271 system.cpu.branchPred.BTBHits 325 # Number of BTB hits
272 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
273 system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
274 system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
275 system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
276 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
277 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
278 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
279 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
280 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
281 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
282 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
283 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
284 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
285 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
286 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
287 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
288 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
289 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
290 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
291 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
292 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
293 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
294 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
295 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
296 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
297 system.cpu.dtb.inst_hits 0 # ITB inst hits
298 system.cpu.dtb.inst_misses 0 # ITB inst misses
299 system.cpu.dtb.read_hits 0 # DTB read hits
300 system.cpu.dtb.read_misses 0 # DTB read misses
301 system.cpu.dtb.write_hits 0 # DTB write hits
302 system.cpu.dtb.write_misses 0 # DTB write misses
303 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
304 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
305 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
306 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
307 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
308 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
309 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
310 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
311 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
312 system.cpu.dtb.read_accesses 0 # DTB read accesses
313 system.cpu.dtb.write_accesses 0 # DTB write accesses
314 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
315 system.cpu.dtb.hits 0 # DTB hits
316 system.cpu.dtb.misses 0 # DTB misses
317 system.cpu.dtb.accesses 0 # DTB accesses
318 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
319 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
320 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
321 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
322 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
323 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
324 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
325 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
326 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
327 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
328 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
329 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
330 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
331 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
332 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
333 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
334 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
335 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
336 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
337 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
338 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
339 system.cpu.itb.inst_hits 0 # ITB inst hits
340 system.cpu.itb.inst_misses 0 # ITB inst misses
341 system.cpu.itb.read_hits 0 # DTB read hits
342 system.cpu.itb.read_misses 0 # DTB read misses
343 system.cpu.itb.write_hits 0 # DTB write hits
344 system.cpu.itb.write_misses 0 # DTB write misses
345 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
346 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
347 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
348 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
349 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
350 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
351 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
352 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
353 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
354 system.cpu.itb.read_accesses 0 # DTB read accesses
355 system.cpu.itb.write_accesses 0 # DTB write accesses
356 system.cpu.itb.inst_accesses 0 # ITB inst accesses
357 system.cpu.itb.hits 0 # DTB hits
358 system.cpu.itb.misses 0 # DTB misses
359 system.cpu.itb.accesses 0 # DTB accesses
360 system.cpu.workload.num_syscalls 13 # Number of system calls
361 system.cpu.numCycles 55822 # number of cpu cycles simulated
362 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
363 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
364 system.cpu.committedInsts 4604 # Number of instructions committed
365 system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
366 system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit
367 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
368 system.cpu.cpi 12.124674 # CPI: cycles per instruction
369 system.cpu.ipc 0.082476 # IPC: instructions per cycle
370 system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
371 system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
372 system.cpu.icache.tags.replacements 3 # number of replacements
373 system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
374 system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
375 system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
376 system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks.
377 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
378 system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
379 system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
380 system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
381 system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
382 system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
383 system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
384 system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
385 system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses
386 system.cpu.icache.tags.data_accesses 4801 # Number of data accesses
387 system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
388 system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
389 system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
390 system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
391 system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
392 system.cpu.icache.overall_hits::total 1919 # number of overall hits
393 system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
394 system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
395 system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
396 system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
397 system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
398 system.cpu.icache.overall_misses::total 321 # number of overall misses
399 system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
400 system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
401 system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
402 system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
403 system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
404 system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
405 system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses)
406 system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses)
407 system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses
408 system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses
409 system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses
410 system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses
411 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses
412 system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses
413 system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses
414 system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses
415 system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses
416 system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses
417 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
418 system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
419 system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
420 system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
421 system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
422 system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
423 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
424 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
425 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
426 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
427 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
428 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
429 system.cpu.icache.fast_writes 0 # number of fast writes performed
430 system.cpu.icache.cache_copies 0 # number of cache copies performed
431 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
432 system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
433 system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
434 system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
435 system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
436 system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
437 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
438 system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
439 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
440 system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
441 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
442 system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
443 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses
444 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses
445 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses
446 system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses
447 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses
448 system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses
449 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
450 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
451 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
452 system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
453 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
454 system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
455 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
456 system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
457 system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
458 system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
459 system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
460 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
461 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
462 system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
463 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
464 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
465 system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
466 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
467 system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
468 system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
469 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
470 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
471 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
472 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
473 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
474 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
475 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
476 system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
477 system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
478 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
479 system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
480 system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
481 system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
482 system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
483 system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
484 system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
485 system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
486 system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
487 system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
488 system.cpu.l2cache.tags.replacements 0 # number of replacements
489 system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
490 system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
491 system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
492 system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
493 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
494 system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
495 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
496 system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
497 system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
498 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
499 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
500 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
501 system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses
502 system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses
503 system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
504 system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
505 system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
506 system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
507 system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
508 system.cpu.l2cache.overall_hits::total 39 # number of overall hits
509 system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
510 system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses
511 system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
512 system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
513 system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses
514 system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
515 system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
516 system.cpu.l2cache.overall_misses::total 428 # number of overall misses
517 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
518 system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
519 system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
520 system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
521 system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
522 system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
523 system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
524 system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
525 system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
526 system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
527 system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
528 system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
529 system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses
530 system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
531 system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses
532 system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
533 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses
534 system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses
535 system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
536 system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
537 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses
538 system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
539 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
540 system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
541 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
542 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
543 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
544 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
545 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
546 system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
547 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
548 system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
549 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
552 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
553 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
556 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
557 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
558 system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
559 system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
560 system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
561 system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
562 system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
563 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
564 system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
565 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
566 system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
567 system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
568 system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
569 system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
570 system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
571 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
572 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
573 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
574 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
575 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
576 system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
577 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
578 system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
579 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
580 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
581 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
582 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
583 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses
584 system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
585 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
586 system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
587 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
588 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
589 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
590 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
591 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
592 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
593 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
594 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
595 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596 system.cpu.dcache.tags.replacements 0 # number of replacements
597 system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
598 system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
599 system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
600 system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
601 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
602 system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
603 system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
604 system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
605 system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
606 system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
607 system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
608 system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
609 system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses
610 system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses
611 system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits
612 system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits
613 system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
614 system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
615 system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
616 system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
617 system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
618 system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
619 system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits
620 system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits
621 system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits
622 system.cpu.dcache.overall_hits::total 1897 # number of overall hits
623 system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
624 system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
625 system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
626 system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
627 system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses
628 system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
629 system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
630 system.cpu.dcache.overall_misses::total 182 # number of overall misses
631 system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
632 system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
633 system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
634 system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
635 system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
636 system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
637 system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
638 system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
639 system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
640 system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
641 system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
642 system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
643 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
644 system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
645 system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
646 system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
647 system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses
648 system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses
649 system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses
650 system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses
651 system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses
652 system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses
653 system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
654 system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
655 system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses
656 system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
657 system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
658 system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
659 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
660 system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
661 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
662 system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
663 system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
664 system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
665 system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
666 system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
667 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
668 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
669 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
670 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
671 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
672 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
673 system.cpu.dcache.fast_writes 0 # number of fast writes performed
674 system.cpu.dcache.cache_copies 0 # number of cache copies performed
675 system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
676 system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
677 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits
678 system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits
679 system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits
680 system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits
681 system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits
682 system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits
683 system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses
684 system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
685 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses
686 system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
687 system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses
688 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
689 system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
690 system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
691 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
692 system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
693 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
694 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
695 system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
696 system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
697 system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
698 system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
699 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
700 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
701 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
702 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
703 system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses
704 system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
705 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
706 system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
707 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
708 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
709 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
710 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
711 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
712 system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
713 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
714 system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
715 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
717 ---------- End Simulation Statistics ----------
projects / gem5.git / blob