tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 load_offset=0
  22 mem_mode=timing
  23 mem_ranges=
  24 memories=system.physmem
  25 num_work_ids=16
  26 readfile=
  27 symbolfile=
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.slave[0]
  36
  37 [system.clk_domain]
  38 type=SrcClockDomain
  39 clock=1000
  40 eventq_index=0
  41 voltage_domain=system.voltage_domain
  42
  43 [system.cpu]
  44 type=DerivO3CPU
  45 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  46 LFSTSize=1024
  47 LQEntries=32
  48 LSQCheckLoads=true
  49 LSQDepCheckShift=4
  50 SQEntries=32
  51 SSITSize=1024
  52 activity=0
  53 backComSize=5
  54 branchPred=system.cpu.branchPred
  55 cachePorts=200
  56 checker=Null
  57 clk_domain=system.cpu_clk_domain
  58 commitToDecodeDelay=1
  59 commitToFetchDelay=1
  60 commitToIEWDelay=1
  61 commitToRenameDelay=1
  62 commitWidth=8
  63 cpu_id=0
  64 decodeToFetchDelay=1
  65 decodeToRenameDelay=1
  66 decodeWidth=8
  67 dispatchWidth=8
  68 do_checkpoint_insts=true
  69 do_quiesce=true
  70 do_statistics_insts=true
  71 dstage2_mmu=system.cpu.dstage2_mmu
  72 dtb=system.cpu.dtb
  73 eventq_index=0
  74 fetchBufferSize=64
  75 fetchToDecodeDelay=1
  76 fetchTrapLatency=1
  77 fetchWidth=8
  78 forwardComSize=5
  79 fuPool=system.cpu.fuPool
  80 function_trace=false
  81 function_trace_start=0
  82 iewToCommitDelay=1
  83 iewToDecodeDelay=1
  84 iewToFetchDelay=1
  85 iewToRenameDelay=1
  86 interrupts=system.cpu.interrupts
  87 isa=system.cpu.isa
  88 issueToExecuteDelay=1
  89 issueWidth=8
  90 istage2_mmu=system.cpu.istage2_mmu
  91 itb=system.cpu.itb
  92 max_insts_all_threads=0
  93 max_insts_any_thread=0
  94 max_loads_all_threads=0
  95 max_loads_any_thread=0
  96 needsTSO=false
  97 numIQEntries=64
  98 numPhysCCRegs=0
  99 numPhysFloatRegs=256
 100 numPhysIntRegs=256
 101 numROBEntries=192
 102 numRobs=1
 103 numThreads=1
 104 profile=0
 105 progress_interval=0
 106 renameToDecodeDelay=1
 107 renameToFetchDelay=1
 108 renameToIEWDelay=2
 109 renameToROBDelay=1
 110 renameWidth=8
 111 simpoint_start_insts=
 112 smtCommitPolicy=RoundRobin
 113 smtFetchPolicy=SingleThread
 114 smtIQPolicy=Partitioned
 115 smtIQThreshold=100
 116 smtLSQPolicy=Partitioned
 117 smtLSQThreshold=100
 118 smtNumFetchingThreads=1
 119 smtROBPolicy=Partitioned
 120 smtROBThreshold=100
 121 socket_id=0
 122 squashWidth=8
 123 store_set_clear_period=250000
 124 switched_out=false
 125 system=system
 126 tracer=system.cpu.tracer
 127 trapLatency=13
 128 wbDepth=1
 129 wbWidth=8
 130 workload=system.cpu.workload
 131 dcache_port=system.cpu.dcache.cpu_side
 132 icache_port=system.cpu.icache.cpu_side
 133
 134 [system.cpu.branchPred]
 135 type=BranchPredictor
 136 BTBEntries=4096
 137 BTBTagSize=16
 138 RASSize=16
 139 choiceCtrBits=2
 140 choicePredictorSize=8192
 141 eventq_index=0
 142 globalCtrBits=2
 143 globalPredictorSize=8192
 144 instShiftAmt=2
 145 localCtrBits=2
 146 localHistoryTableSize=2048
 147 localPredictorSize=2048
 148 numThreads=1
 149 predType=tournament
 150
 151 [system.cpu.dcache]
 152 type=BaseCache
 153 children=tags
 154 addr_ranges=0:18446744073709551615
 155 assoc=2
 156 clk_domain=system.cpu_clk_domain
 157 eventq_index=0
 158 forward_snoops=true
 159 hit_latency=2
 160 is_top_level=true
 161 max_miss_count=0
 162 mshrs=4
 163 prefetch_on_access=false
 164 prefetcher=Null
 165 response_latency=2
 166 sequential_access=false
 167 size=262144
 168 system=system
 169 tags=system.cpu.dcache.tags
 170 tgts_per_mshr=20
 171 two_queue=false
 172 write_buffers=8
 173 cpu_side=system.cpu.dcache_port
 174 mem_side=system.cpu.toL2Bus.slave[1]
 175
 176 [system.cpu.dcache.tags]
 177 type=LRU
 178 assoc=2
 179 block_size=64
 180 clk_domain=system.cpu_clk_domain
 181 eventq_index=0
 182 hit_latency=2
 183 sequential_access=false
 184 size=262144
 185
 186 [system.cpu.dstage2_mmu]
 187 type=ArmStage2MMU
 188 children=stage2_tlb
 189 eventq_index=0
 190 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 191 tlb=system.cpu.dtb
 192
 193 [system.cpu.dstage2_mmu.stage2_tlb]
 194 type=ArmTLB
 195 children=walker
 196 eventq_index=0
 197 is_stage2=true
 198 size=32
 199 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 200
 201 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 202 type=ArmTableWalker
 203 clk_domain=system.cpu_clk_domain
 204 eventq_index=0
 205 is_stage2=true
 206 num_squash_per_cycle=2
 207 sys=system
 208 port=system.cpu.toL2Bus.slave[5]
 209
 210 [system.cpu.dtb]
 211 type=ArmTLB
 212 children=walker
 213 eventq_index=0
 214 is_stage2=false
 215 size=64
 216 walker=system.cpu.dtb.walker
 217
 218 [system.cpu.dtb.walker]
 219 type=ArmTableWalker
 220 clk_domain=system.cpu_clk_domain
 221 eventq_index=0
 222 is_stage2=false
 223 num_squash_per_cycle=2
 224 sys=system
 225 port=system.cpu.toL2Bus.slave[3]
 226
 227 [system.cpu.fuPool]
 228 type=FUPool
 229 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 230 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 231 eventq_index=0
 232
 233 [system.cpu.fuPool.FUList0]
 234 type=FUDesc
 235 children=opList
 236 count=6
 237 eventq_index=0
 238 opList=system.cpu.fuPool.FUList0.opList
 239
 240 [system.cpu.fuPool.FUList0.opList]
 241 type=OpDesc
 242 eventq_index=0
 243 issueLat=1
 244 opClass=IntAlu
 245 opLat=1
 246
 247 [system.cpu.fuPool.FUList1]
 248 type=FUDesc
 249 children=opList0 opList1
 250 count=2
 251 eventq_index=0
 252 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 253
 254 [system.cpu.fuPool.FUList1.opList0]
 255 type=OpDesc
 256 eventq_index=0
 257 issueLat=1
 258 opClass=IntMult
 259 opLat=3
 260
 261 [system.cpu.fuPool.FUList1.opList1]
 262 type=OpDesc
 263 eventq_index=0
 264 issueLat=19
 265 opClass=IntDiv
 266 opLat=20
 267
 268 [system.cpu.fuPool.FUList2]
 269 type=FUDesc
 270 children=opList0 opList1 opList2
 271 count=4
 272 eventq_index=0
 273 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 274
 275 [system.cpu.fuPool.FUList2.opList0]
 276 type=OpDesc
 277 eventq_index=0
 278 issueLat=1
 279 opClass=FloatAdd
 280 opLat=2
 281
 282 [system.cpu.fuPool.FUList2.opList1]
 283 type=OpDesc
 284 eventq_index=0
 285 issueLat=1
 286 opClass=FloatCmp
 287 opLat=2
 288
 289 [system.cpu.fuPool.FUList2.opList2]
 290 type=OpDesc
 291 eventq_index=0
 292 issueLat=1
 293 opClass=FloatCvt
 294 opLat=2
 295
 296 [system.cpu.fuPool.FUList3]
 297 type=FUDesc
 298 children=opList0 opList1 opList2
 299 count=2
 300 eventq_index=0
 301 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 302
 303 [system.cpu.fuPool.FUList3.opList0]
 304 type=OpDesc
 305 eventq_index=0
 306 issueLat=1
 307 opClass=FloatMult
 308 opLat=4
 309
 310 [system.cpu.fuPool.FUList3.opList1]
 311 type=OpDesc
 312 eventq_index=0
 313 issueLat=12
 314 opClass=FloatDiv
 315 opLat=12
 316
 317 [system.cpu.fuPool.FUList3.opList2]
 318 type=OpDesc
 319 eventq_index=0
 320 issueLat=24
 321 opClass=FloatSqrt
 322 opLat=24
 323
 324 [system.cpu.fuPool.FUList4]
 325 type=FUDesc
 326 children=opList
 327 count=0
 328 eventq_index=0
 329 opList=system.cpu.fuPool.FUList4.opList
 330
 331 [system.cpu.fuPool.FUList4.opList]
 332 type=OpDesc
 333 eventq_index=0
 334 issueLat=1
 335 opClass=MemRead
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5]
 339 type=FUDesc
 340 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 341 count=4
 342 eventq_index=0
 343 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 344
 345 [system.cpu.fuPool.FUList5.opList00]
 346 type=OpDesc
 347 eventq_index=0
 348 issueLat=1
 349 opClass=SimdAdd
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList01]
 353 type=OpDesc
 354 eventq_index=0
 355 issueLat=1
 356 opClass=SimdAddAcc
 357 opLat=1
 358
 359 [system.cpu.fuPool.FUList5.opList02]
 360 type=OpDesc
 361 eventq_index=0
 362 issueLat=1
 363 opClass=SimdAlu
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList03]
 367 type=OpDesc
 368 eventq_index=0
 369 issueLat=1
 370 opClass=SimdCmp
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList04]
 374 type=OpDesc
 375 eventq_index=0
 376 issueLat=1
 377 opClass=SimdCvt
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList05]
 381 type=OpDesc
 382 eventq_index=0
 383 issueLat=1
 384 opClass=SimdMisc
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList06]
 388 type=OpDesc
 389 eventq_index=0
 390 issueLat=1
 391 opClass=SimdMult
 392 opLat=1
 393
 394 [system.cpu.fuPool.FUList5.opList07]
 395 type=OpDesc
 396 eventq_index=0
 397 issueLat=1
 398 opClass=SimdMultAcc
 399 opLat=1
 400
 401 [system.cpu.fuPool.FUList5.opList08]
 402 type=OpDesc
 403 eventq_index=0
 404 issueLat=1
 405 opClass=SimdShift
 406 opLat=1
 407
 408 [system.cpu.fuPool.FUList5.opList09]
 409 type=OpDesc
 410 eventq_index=0
 411 issueLat=1
 412 opClass=SimdShiftAcc
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList5.opList10]
 416 type=OpDesc
 417 eventq_index=0
 418 issueLat=1
 419 opClass=SimdSqrt
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList5.opList11]
 423 type=OpDesc
 424 eventq_index=0
 425 issueLat=1
 426 opClass=SimdFloatAdd
 427 opLat=1
 428
 429 [system.cpu.fuPool.FUList5.opList12]
 430 type=OpDesc
 431 eventq_index=0
 432 issueLat=1
 433 opClass=SimdFloatAlu
 434 opLat=1
 435
 436 [system.cpu.fuPool.FUList5.opList13]
 437 type=OpDesc
 438 eventq_index=0
 439 issueLat=1
 440 opClass=SimdFloatCmp
 441 opLat=1
 442
 443 [system.cpu.fuPool.FUList5.opList14]
 444 type=OpDesc
 445 eventq_index=0
 446 issueLat=1
 447 opClass=SimdFloatCvt
 448 opLat=1
 449
 450 [system.cpu.fuPool.FUList5.opList15]
 451 type=OpDesc
 452 eventq_index=0
 453 issueLat=1
 454 opClass=SimdFloatDiv
 455 opLat=1
 456
 457 [system.cpu.fuPool.FUList5.opList16]
 458 type=OpDesc
 459 eventq_index=0
 460 issueLat=1
 461 opClass=SimdFloatMisc
 462 opLat=1
 463
 464 [system.cpu.fuPool.FUList5.opList17]
 465 type=OpDesc
 466 eventq_index=0
 467 issueLat=1
 468 opClass=SimdFloatMult
 469 opLat=1
 470
 471 [system.cpu.fuPool.FUList5.opList18]
 472 type=OpDesc
 473 eventq_index=0
 474 issueLat=1
 475 opClass=SimdFloatMultAcc
 476 opLat=1
 477
 478 [system.cpu.fuPool.FUList5.opList19]
 479 type=OpDesc
 480 eventq_index=0
 481 issueLat=1
 482 opClass=SimdFloatSqrt
 483 opLat=1
 484
 485 [system.cpu.fuPool.FUList6]
 486 type=FUDesc
 487 children=opList
 488 count=0
 489 eventq_index=0
 490 opList=system.cpu.fuPool.FUList6.opList
 491
 492 [system.cpu.fuPool.FUList6.opList]
 493 type=OpDesc
 494 eventq_index=0
 495 issueLat=1
 496 opClass=MemWrite
 497 opLat=1
 498
 499 [system.cpu.fuPool.FUList7]
 500 type=FUDesc
 501 children=opList0 opList1
 502 count=4
 503 eventq_index=0
 504 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 505
 506 [system.cpu.fuPool.FUList7.opList0]
 507 type=OpDesc
 508 eventq_index=0
 509 issueLat=1
 510 opClass=MemRead
 511 opLat=1
 512
 513 [system.cpu.fuPool.FUList7.opList1]
 514 type=OpDesc
 515 eventq_index=0
 516 issueLat=1
 517 opClass=MemWrite
 518 opLat=1
 519
 520 [system.cpu.fuPool.FUList8]
 521 type=FUDesc
 522 children=opList
 523 count=1
 524 eventq_index=0
 525 opList=system.cpu.fuPool.FUList8.opList
 526
 527 [system.cpu.fuPool.FUList8.opList]
 528 type=OpDesc
 529 eventq_index=0
 530 issueLat=3
 531 opClass=IprAccess
 532 opLat=3
 533
 534 [system.cpu.icache]
 535 type=BaseCache
 536 children=tags
 537 addr_ranges=0:18446744073709551615
 538 assoc=2
 539 clk_domain=system.cpu_clk_domain
 540 eventq_index=0
 541 forward_snoops=true
 542 hit_latency=2
 543 is_top_level=true
 544 max_miss_count=0
 545 mshrs=4
 546 prefetch_on_access=false
 547 prefetcher=Null
 548 response_latency=2
 549 sequential_access=false
 550 size=131072
 551 system=system
 552 tags=system.cpu.icache.tags
 553 tgts_per_mshr=20
 554 two_queue=false
 555 write_buffers=8
 556 cpu_side=system.cpu.icache_port
 557 mem_side=system.cpu.toL2Bus.slave[0]
 558
 559 [system.cpu.icache.tags]
 560 type=LRU
 561 assoc=2
 562 block_size=64
 563 clk_domain=system.cpu_clk_domain
 564 eventq_index=0
 565 hit_latency=2
 566 sequential_access=false
 567 size=131072
 568
 569 [system.cpu.interrupts]
 570 type=ArmInterrupts
 571 eventq_index=0
 572
 573 [system.cpu.isa]
 574 type=ArmISA
 575 eventq_index=0
 576 fpsid=1090793632
 577 id_aa64afr0_el1=0
 578 id_aa64afr1_el1=0
 579 id_aa64dfr0_el1=1052678
 580 id_aa64dfr1_el1=0
 581 id_aa64isar0_el1=0
 582 id_aa64isar1_el1=0
 583 id_aa64mmfr0_el1=15728642
 584 id_aa64mmfr1_el1=0
 585 id_aa64pfr0_el1=17
 586 id_aa64pfr1_el1=0
 587 id_isar0=34607377
 588 id_isar1=34677009
 589 id_isar2=555950401
 590 id_isar3=17899825
 591 id_isar4=268501314
 592 id_isar5=0
 593 id_mmfr0=270536963
 594 id_mmfr1=0
 595 id_mmfr2=19070976
 596 id_mmfr3=34611729
 597 id_pfr0=49
 598 id_pfr1=4113
 599 midr=1091551472
 600 system=system
 601
 602 [system.cpu.istage2_mmu]
 603 type=ArmStage2MMU
 604 children=stage2_tlb
 605 eventq_index=0
 606 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 607 tlb=system.cpu.itb
 608
 609 [system.cpu.istage2_mmu.stage2_tlb]
 610 type=ArmTLB
 611 children=walker
 612 eventq_index=0
 613 is_stage2=true
 614 size=32
 615 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 616
 617 [system.cpu.istage2_mmu.stage2_tlb.walker]
 618 type=ArmTableWalker
 619 clk_domain=system.cpu_clk_domain
 620 eventq_index=0
 621 is_stage2=true
 622 num_squash_per_cycle=2
 623 sys=system
 624 port=system.cpu.toL2Bus.slave[4]
 625
 626 [system.cpu.itb]
 627 type=ArmTLB
 628 children=walker
 629 eventq_index=0
 630 is_stage2=false
 631 size=64
 632 walker=system.cpu.itb.walker
 633
 634 [system.cpu.itb.walker]
 635 type=ArmTableWalker
 636 clk_domain=system.cpu_clk_domain
 637 eventq_index=0
 638 is_stage2=false
 639 num_squash_per_cycle=2
 640 sys=system
 641 port=system.cpu.toL2Bus.slave[2]
 642
 643 [system.cpu.l2cache]
 644 type=BaseCache
 645 children=tags
 646 addr_ranges=0:18446744073709551615
 647 assoc=8
 648 clk_domain=system.cpu_clk_domain
 649 eventq_index=0
 650 forward_snoops=true
 651 hit_latency=20
 652 is_top_level=false
 653 max_miss_count=0
 654 mshrs=20
 655 prefetch_on_access=false
 656 prefetcher=Null
 657 response_latency=20
 658 sequential_access=false
 659 size=2097152
 660 system=system
 661 tags=system.cpu.l2cache.tags
 662 tgts_per_mshr=12
 663 two_queue=false
 664 write_buffers=8
 665 cpu_side=system.cpu.toL2Bus.master[0]
 666 mem_side=system.membus.slave[1]
 667
 668 [system.cpu.l2cache.tags]
 669 type=LRU
 670 assoc=8
 671 block_size=64
 672 clk_domain=system.cpu_clk_domain
 673 eventq_index=0
 674 hit_latency=20
 675 sequential_access=false
 676 size=2097152
 677
 678 [system.cpu.toL2Bus]
 679 type=CoherentBus
 680 clk_domain=system.cpu_clk_domain
 681 eventq_index=0
 682 header_cycles=1
 683 system=system
 684 use_default_range=false
 685 width=32
 686 master=system.cpu.l2cache.cpu_side
 687 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 688
 689 [system.cpu.tracer]
 690 type=ExeTracer
 691 eventq_index=0
 692
 693 [system.cpu.workload]
 694 type=LiveProcess
 695 cmd=hello
 696 cwd=
 697 egid=100
 698 env=
 699 errout=cerr
 700 euid=100
 701 eventq_index=0
 702 executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
 703 gid=100
 704 input=cin
 705 max_stack_size=67108864
 706 output=cout
 707 pid=100
 708 ppid=99
 709 simpoint=0
 710 system=system
 711 uid=100
 712
 713 [system.cpu_clk_domain]
 714 type=SrcClockDomain
 715 clock=500
 716 eventq_index=0
 717 voltage_domain=system.voltage_domain
 718
 719 [system.membus]
 720 type=CoherentBus
 721 clk_domain=system.clk_domain
 722 eventq_index=0
 723 header_cycles=1
 724 system=system
 725 use_default_range=false
 726 width=8
 727 master=system.physmem.port
 728 slave=system.system_port system.cpu.l2cache.mem_side
 729
 730 [system.physmem]
 731 type=DRAMCtrl
 732 activation_limit=4
 733 addr_mapping=RoRaBaChCo
 734 banks_per_rank=8
 735 burst_length=8
 736 channels=1
 737 clk_domain=system.clk_domain
 738 conf_table_reported=true
 739 device_bus_width=8
 740 device_rowbuffer_size=1024
 741 devices_per_rank=8
 742 eventq_index=0
 743 in_addr_map=true
 744 max_accesses_per_row=16
 745 mem_sched_policy=frfcfs
 746 min_writes_per_switch=16
 747 null=false
 748 page_policy=open_adaptive
 749 range=0:134217727
 750 ranks_per_channel=2
 751 read_buffer_size=32
 752 static_backend_latency=10000
 753 static_frontend_latency=10000
 754 tBURST=5000
 755 tCK=1250
 756 tCL=13750
 757 tRAS=35000
 758 tRCD=13750
 759 tREFI=7800000
 760 tRFC=260000
 761 tRP=13750
 762 tRRD=6000
 763 tRTP=7500
 764 tRTW=2500
 765 tWR=15000
 766 tWTR=7500
 767 tXAW=30000
 768 write_buffer_size=64
 769 write_high_thresh_perc=85
 770 write_low_thresh_perc=50
 771 port=system.membus.master[0]
 772
 773 [system.voltage_domain]
 774 type=VoltageDomain
 775 eventq_index=0
 776 voltage=1.000000
 777